llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

# Tries to emit a foldable G_PTR_ADD with (p1, s32) operands.
---
name:            test_ptradd_crash__offset_smaller
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_ptradd_crash__offset_smaller
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64)
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1)
    ; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
    %1:_(p1) = G_CONSTANT i64 0
    %3:_(s32) = G_CONSTANT i32 3
    %0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
    $sgpr0 = COPY %2
    SI_RETURN_TO_EPILOG implicit $sgpr0
...

# Tries to emit a foldable G_PTR_ADD with (p1, s128) operands.
---
name:            test_ptradd_crash__offset_wider
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_ptradd_crash__offset_wider
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64)
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1)
    ; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
    %1:_(p1) = G_CONSTANT i64 0
    %3:_(s32) = G_CONSTANT i32 3
    %0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
    $sgpr0 = COPY %2
    SI_RETURN_TO_EPILOG implicit $sgpr0
...