[X86] Autogenerate complete checks. NFC
diff --git a/llvm/test/CodeGen/X86/zext-logicop-shift-load.ll b/llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
index 26182fe..319c177 100644
--- a/llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
+++ b/llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
@@ -1,12 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
define i64 @test1(i8* %data) {
; CHECK-LABEL: test1:
-; CHECK: movzbl
-; CHECK-NEXT: shlq
-; CHECK-NEXT: andl
-; CHECK-NEXT: retq
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzbl (%rdi), %eax
+; CHECK-NEXT: shlq $2, %rax
+; CHECK-NEXT: andl $60, %eax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%bf.clear = shl i8 %bf.load, 2
@@ -17,10 +19,11 @@
define i8* @test2(i8* %data) {
; CHECK-LABEL: test2:
-; CHECK: movzbl
-; CHECK-NEXT: andl
-; CHECK-NEXT: leaq
-; CHECK-NEXT: retq
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzbl (%rdi), %eax
+; CHECK-NEXT: andl $15, %eax
+; CHECK-NEXT: leaq (%rdi,%rax,4), %rax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%bf.clear = shl i8 %bf.load, 2
@@ -33,11 +36,12 @@
; If the shift op is SHL, the logic op can only be AND.
define i64 @test3(i8* %data) {
; CHECK-LABEL: test3:
-; CHECK: movb
-; CHECK-NEXT: shlb
-; CHECK-NEXT: xorb
-; CHECK-NEXT: movzbl
-; CHECK-NEXT: retq
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movb (%rdi), %al
+; CHECK-NEXT: shlb $2, %al
+; CHECK-NEXT: xorb $60, %al
+; CHECK-NEXT: movzbl %al, %eax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%bf.clear = shl i8 %bf.load, 2
@@ -48,10 +52,11 @@
define i64 @test4(i8* %data) {
; CHECK-LABEL: test4:
-; CHECK: movzbl
-; CHECK-NEXT: shrq
-; CHECK-NEXT: andl
-; CHECK-NEXT: retq
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzbl (%rdi), %eax
+; CHECK-NEXT: shrq $2, %rax
+; CHECK-NEXT: andl $60, %eax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%bf.clear = lshr i8 %bf.load, 2
@@ -62,10 +67,11 @@
define i64 @test5(i8* %data) {
; CHECK-LABEL: test5:
-; CHECK: movzbl
-; CHECK-NEXT: shrq
-; CHECK-NEXT: xorq
-; CHECK-NEXT: retq
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzbl (%rdi), %eax
+; CHECK-NEXT: shrq $2, %rax
+; CHECK-NEXT: xorq $60, %rax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%bf.clear = lshr i8 %bf.load, 2
@@ -76,10 +82,11 @@
define i64 @test6(i8* %data) {
; CHECK-LABEL: test6:
-; CHECK: movzbl
-; CHECK-NEXT: shrq
-; CHECK-NEXT: orq
-; CHECK-NEXT: retq
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movzbl (%rdi), %eax
+; CHECK-NEXT: shrq $2, %rax
+; CHECK-NEXT: orq $60, %rax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%bf.clear = lshr i8 %bf.load, 2
@@ -91,10 +98,13 @@
; Load is folded with sext.
define i64 @test8(i8* %data) {
; CHECK-LABEL: test8:
-; CHECK: movsbl
-; CHECK-NEXT: movzwl
-; CHECK-NEXT: shrl
-; CHECK-NEXT: orl
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movsbl (%rdi), %eax
+; CHECK-NEXT: movzwl %ax, %eax
+; CHECK-NEXT: shrl $2, %eax
+; CHECK-NEXT: orl $60, %eax
+; CHECK-NEXT: movl %eax, %eax
+; CHECK-NEXT: retq
entry:
%bf.load = load i8, i8* %data, align 4
%ext = sext i8 %bf.load to i16
