[AArch64] Simplify the scheduling predicates (NFC)
The instruction encodings make it unnecessary to distinguish extended W-form
from X-form instructions.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
index 7014c0c..f8533d1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
@@ -35,21 +35,13 @@
"isExynosExtFast",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
- IsArithExt32Op.ValidOpcodes,
+ IsArithExtOp.ValidOpcodes,
MCReturnStatement<
CheckAny<[CheckExtBy0,
CheckAll<
- [CheckExtUXTW,
- CheckAny<
- [CheckExtBy1,
- CheckExtBy2,
- CheckExtBy3]>]>]>>>,
- MCOpcodeSwitchCase<
- IsArithExt64Op.ValidOpcodes,
- MCReturnStatement<
- CheckAny<[CheckExtBy0,
- CheckAll<
- [CheckExtUXTX,
+ [CheckAny<
+ [CheckExtUXTW,
+ CheckExtUXTX]>,
CheckAny<
[CheckExtBy1,
CheckExtBy2,
@@ -57,6 +49,20 @@
MCReturnStatement<FalsePred>>>;
def ExynosExtPred : MCSchedPredicate<ExynosExtFn>;
+// Identify a load or store using the register offset addressing mode
+// with a scaled non-extended register.
+def ExynosScaledIdxFn : TIIPredicate<"isExynosScaledAddr",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ IsLoadStoreRegOffsetOp.ValidOpcodes,
+ MCReturnStatement<
+ CheckAny<
+ [CheckMemExtSXTW,
+ CheckMemExtUXTW,
+ CheckMemScaled]>>>],
+ MCReturnStatement<FalsePred>>>;
+def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
+
// Identify FP instructions.
def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckDForm, CheckQForm]>>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index a151c5a..a48f1dc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -132,12 +132,10 @@
CheckRegOperand<0, Q31>]>]>;
// Identify arithmetic instructions with extend.
-def IsArithExt32Op : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
- SUBWrx, SUBXrx, SUBSWrx, SUBSXrx]>;
-def IsArithExt64Op : CheckOpcode<[ADDXrx64, ADDSXrx64,
+def IsArithExtOp : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
+ SUBWrx, SUBXrx, SUBSWrx, SUBSXrx,
+ ADDXrx64, ADDSXrx64,
SUBXrx64, SUBSXrx64]>;
-def IsArithExtOp : CheckOpcode<!listconcat(IsArithExt32Op.ValidOpcodes,
- IsArithExt64Op.ValidOpcodes)>;
// Identify arithmetic immediate instructions.
def IsArithImmOp : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri,