commit | 733b8571b4a3d432caed5e48c94784f930bc0687 | [log] [tgz] |
---|---|---|
author | Matt Arsenault <Matthew.Arsenault@amd.com> | Wed Mar 27 16:12:26 2019 +0000 |
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Wed Mar 27 16:12:26 2019 +0000 |
tree | f2e1b0ea68570260aba96090e8ad5a8eca370b1c | |
parent | 566fba03de5a3449b9ca8cb5eb64d53080b3fc03 [diff] |
MIR: Freeze reserved regs after parsing everything The AMDGPU implementation of getReservedRegs depends on MachineFunctionInfo fields that are parsed from the YAML section. This was reserving the wrong register since it was setting the reserved regs before parsing the correct one. Some tests were relying on the default reserved set for the assumed default calling convention. llvm-svn: 357083