[DAGCombiner] reduce indent; NFC
Unlike some of the folds in hoistLogicOpWithSameOpcodeHands()
above this shuffle transform, this has the expected hasOneUse()
checks in place.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d9834cf..db5e10b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3810,9 +3810,8 @@
// or second operand, then it might still be profitable to move the shuffle
// after the xor/and/or operation.
if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
- ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
- ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
-
+ auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
+ auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
"Inputs to shuffles are not the same type");
@@ -3820,42 +3819,36 @@
// the same length because the result vector type is the same.
// Check also that shuffles have only one use to avoid introducing extra
// instructions.
- if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
- SVN0->getMask().equals(SVN1->getMask())) {
- SDValue ShOp = N0->getOperand(1);
+ if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
+ !SVN0->getMask().equals(SVN1->getMask()))
+ return SDValue();
- // Don't try to fold this node if it requires introducing a
- // build vector of all zeros that might be illegal at this stage.
- if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
- ShOp = tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
+ // Don't try to fold this node if it requires introducing a
+ // build vector of all zeros that might be illegal at this stage.
+ SDValue ShOp = N0->getOperand(1);
+ if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
+ ShOp = tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
- // (AND (shuf (A, C), shuf (B, C))) -> shuf (AND (A, B), C)
- // (OR (shuf (A, C), shuf (B, C))) -> shuf (OR (A, B), C)
- // (XOR (shuf (A, C), shuf (B, C))) -> shuf (XOR (A, B), V_0)
- if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
- SDValue NewNode = DAG.getNode(LogicOpcode, SDLoc(N), VT,
- N0->getOperand(0), N1->getOperand(0));
- AddToWorklist(NewNode.getNode());
- return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
- SVN0->getMask());
- }
+ // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
+ if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
+ SDValue NewNode = DAG.getNode(LogicOpcode, SDLoc(N), VT,
+ N0->getOperand(0), N1->getOperand(0));
+ AddToWorklist(NewNode.getNode());
+ return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp, SVN0->getMask());
+ }
- // Don't try to fold this node if it requires introducing a
- // build vector of all zeros that might be illegal at this stage.
- ShOp = N0->getOperand(0);
- if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
- ShOp = tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
+ // Don't try to fold this node if it requires introducing a
+ // build vector of all zeros that might be illegal at this stage.
+ ShOp = N0->getOperand(0);
+ if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
+ ShOp = tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
- // (AND (shuf (C, A), shuf (C, B))) -> shuf (C, AND (A, B))
- // (OR (shuf (C, A), shuf (C, B))) -> shuf (C, OR (A, B))
- // (XOR (shuf (C, A), shuf (C, B))) -> shuf (V_0, XOR (A, B))
- if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
- SDValue NewNode = DAG.getNode(LogicOpcode, SDLoc(N), VT,
- N0->getOperand(1), N1->getOperand(1));
- AddToWorklist(NewNode.getNode());
- return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
- SVN0->getMask());
- }
+ // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
+ if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
+ SDValue NewNode = DAG.getNode(LogicOpcode, SDLoc(N), VT,
+ N0->getOperand(1), N1->getOperand(1));
+ AddToWorklist(NewNode.getNode());
+ return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode, SVN0->getMask());
}
}
