| # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| --- | |
| define void @test_s1() { ret void } |
| define void @test_s8() { ret void } |
| define void @test_s16() { ret void } |
| define void @test_s32() { ret void } |
| |
| define void @test_gep() { ret void } |
| |
| define void @test_load_from_stack() { ret void } |
| ... |
| --- |
| name: test_s1 |
| # CHECK-LABEL: name: test_s1 |
| legalized: true |
| regBankSelected: true |
| selected: false |
| # CHECK: selected: true |
| registers: |
| - { id: 0, class: gprb } |
| - { id: 1, class: gprb } |
| body: | |
| bb.0: |
| liveins: $r0 |
| |
| %0(p0) = COPY $r0 |
| ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 |
| |
| %1(s1) = G_LOAD %0(p0) :: (load 1) |
| ; CHECK: %[[V8:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1) |
| |
| G_STORE %1(s1), %0(p0) :: (store 1) |
| ; CHECK: %[[V1:[0-9]+]]:rgpr = t2ANDri %[[V8]], 1, 14, $noreg |
| ; CHECK: t2STRBi12 %[[V1]], %[[P]], 0, 14, $noreg :: (store 1) |
| |
| BX_RET 14, $noreg |
| ; CHECK: BX_RET 14, $noreg |
| ... |
| --- |
| name: test_s8 |
| # CHECK-LABEL: name: test_s8 |
| legalized: true |
| regBankSelected: true |
| selected: false |
| # CHECK: selected: true |
| registers: |
| - { id: 0, class: gprb } |
| - { id: 1, class: gprb } |
| body: | |
| bb.0: |
| liveins: $r0 |
| |
| %0(p0) = COPY $r0 |
| ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 |
| |
| %1(s8) = G_LOAD %0(p0) :: (load 1) |
| ; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1) |
| |
| G_STORE %1(s8), %0(p0) :: (store 1) |
| ; CHECK: t2STRBi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 1) |
| |
| BX_RET 14, $noreg |
| ; CHECK: BX_RET 14, $noreg |
| ... |
| --- |
| name: test_s16 |
| # CHECK-LABEL: name: test_s16 |
| legalized: true |
| regBankSelected: true |
| selected: false |
| # CHECK: selected: true |
| registers: |
| - { id: 0, class: gprb } |
| - { id: 1, class: gprb } |
| body: | |
| bb.0: |
| liveins: $r0 |
| |
| %0(p0) = COPY $r0 |
| ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 |
| |
| %1(s16) = G_LOAD %0(p0) :: (load 2) |
| ; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRHi12 %[[P]], 0, 14, $noreg :: (load 2) |
| |
| G_STORE %1(s16), %0(p0) :: (store 2) |
| ; CHECK: t2STRHi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 2) |
| |
| BX_RET 14, $noreg |
| ; CHECK: BX_RET 14, $noreg |
| ... |
| --- |
| name: test_s32 |
| # CHECK-LABEL: name: test_s32 |
| legalized: true |
| regBankSelected: true |
| selected: false |
| # CHECK: selected: true |
| registers: |
| - { id: 0, class: gprb } |
| - { id: 1, class: gprb } |
| body: | |
| bb.0: |
| liveins: $r0 |
| |
| %0(p0) = COPY $r0 |
| ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 |
| |
| %1(s32) = G_LOAD %0(p0) :: (load 4) |
| ; CHECK: %[[V:[0-9]+]]:gpr = t2LDRi12 %[[P]], 0, 14, $noreg :: (load 4) |
| |
| G_STORE %1(s32), %0(p0) :: (store 4) |
| ; CHECK: t2STRi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 4) |
| |
| BX_RET 14, $noreg |
| ; CHECK: BX_RET 14, $noreg |
| ... |
| --- |
| name: test_gep |
| # CHECK-LABEL: name: test_gep |
| legalized: true |
| regBankSelected: true |
| selected: false |
| # CHECK: selected: true |
| registers: |
| - { id: 0, class: gprb } |
| - { id: 1, class: gprb } |
| - { id: 2, class: gprb } |
| body: | |
| bb.0: |
| liveins: $r0, $r1 |
| |
| %0(p0) = COPY $r0 |
| ; CHECK: [[PTR:%[0-9]+]]:gprnopc = COPY $r0 |
| |
| %1(s32) = COPY $r1 |
| ; CHECK: [[OFF:%[0-9]+]]:rgpr = COPY $r1 |
| |
| %2(p0) = G_GEP %0, %1(s32) |
| ; CHECK: [[GEP:%[0-9]+]]:gprnopc = t2ADDrr [[PTR]], [[OFF]], 14, $noreg, $noreg |
| |
| $r0 = COPY %2(p0) |
| ; CHECK: $r0 = COPY [[GEP]] |
| |
| BX_RET 14, $noreg, implicit $r0 |
| ; CHECK: BX_RET 14, $noreg, implicit $r0 |
| ... |
| --- |
| name: test_load_from_stack |
| # CHECK-LABEL: name: test_load_from_stack |
| legalized: true |
| regBankSelected: true |
| selected: false |
| # CHECK: selected: true |
| registers: |
| - { id: 0, class: gprb } |
| - { id: 1, class: gprb } |
| - { id: 2, class: gprb } |
| - { id: 3, class: gprb } |
| - { id: 4, class: gprb } |
| fixedStack: |
| - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } |
| - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } |
| - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } |
| # CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 |
| # CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 |
| body: | |
| bb.0: |
| liveins: $r0, $r1, $r2, $r3 |
| |
| %0(p0) = G_FRAME_INDEX %fixed-stack.2 |
| ; CHECK: [[FI32VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg |
| |
| %1(s32) = G_LOAD %0(p0) :: (load 4) |
| ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg |
| |
| $r0 = COPY %1 |
| ; CHECK: $r0 = COPY [[LD32VREG]] |
| |
| %2(p0) = G_FRAME_INDEX %fixed-stack.0 |
| ; CHECK: [[FI1VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg |
| |
| %3(s1) = G_LOAD %2(p0) :: (load 1) |
| ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg |
| |
| %4(s32) = G_ANYEXT %3(s1) |
| ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] |
| |
| $r0 = COPY %4 |
| ; CHECK: $r0 = COPY [[RES]] |
| |
| BX_RET 14, $noreg |
| ; CHECK: BX_RET 14, $noreg |
| ... |