llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5

; RUN: llc -mtriple=amdgcn  < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga  < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900  < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100  < %s | FileCheck -check-prefixes=GFX11 %s

define <22 x i32> @bitcast_v11i64_to_v22i32(<11 x i64> %a, i32 %b) {
; GCN-LABEL: bitcast_v11i64_to_v22i32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22
; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT:    s_cbranch_execz .LBB0_2
; GCN-NEXT:  ; %bb.1: ; %cmp.true
; GCN-NEXT:    v_add_i32_e32 v20, vcc, 3, v20
; GCN-NEXT:    v_addc_u32_e32 v21, vcc, 0, v21, vcc
; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v18
; GCN-NEXT:    v_addc_u32_e32 v19, vcc, 0, v19, vcc
; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT:    v_addc_u32_e32 v17, vcc, 0, v17, vcc
; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v14
; GCN-NEXT:    v_addc_u32_e32 v15, vcc, 0, v15, vcc
; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT:    v_addc_u32_e32 v13, vcc, 0, v13, vcc
; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v10
; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT:  .LBB0_2: ; %end
; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v11i64_to_v22i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB0_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT:    v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT:    v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT:    v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT:    v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT:    v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT:    v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT:    v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT:    v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT:    v_addc_u32_e32 v13, vcc, 0, v13, vcc
; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT:  .LBB0_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v11i64_to_v22i32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB0_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT:    v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT:    v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT:    v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v14, vcc, 3, v14
; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT:  .LBB0_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v11i64_to_v22i32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v22
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB0_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT:  .LBB0_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <11 x i64> %a, splat (i64 3)
  %a2 = bitcast <11 x i64> %a1 to <22 x i32>
  br label %end

cmp.false:
  %a3 = bitcast <11 x i64> %a to <22 x i32>
  br label %end

end:
  %phi = phi <22 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <22 x i32> %phi
}

define <11 x i64> @bitcast_v22i32_to_v11i64(<22 x i32> %a, i32 %b) {
; GCN-LABEL: bitcast_v22i32_to_v11i64:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22
; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT:    s_cbranch_execz .LBB1_2
; GCN-NEXT:  ; %bb.1: ; %cmp.true
; GCN-NEXT:    v_add_i32_e32 v21, vcc, 3, v21
; GCN-NEXT:    v_add_i32_e32 v20, vcc, 3, v20
; GCN-NEXT:    v_add_i32_e32 v19, vcc, 3, v19
; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v18
; GCN-NEXT:    v_add_i32_e32 v17, vcc, 3, v17
; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v16
; GCN-NEXT:    v_add_i32_e32 v15, vcc, 3, v15
; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v14
; GCN-NEXT:    v_add_i32_e32 v13, vcc, 3, v13
; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v12
; GCN-NEXT:    v_add_i32_e32 v11, vcc, 3, v11
; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v10
; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT:  .LBB1_2: ; %end
; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
; GCN-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v22i32_to_v11i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22
; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT:    s_cbranch_execz .LBB1_2
; VI-NEXT:  ; %bb.1: ; %cmp.true
; VI-NEXT:    v_add_u32_e32 v21, vcc, 3, v21
; VI-NEXT:    v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT:    v_add_u32_e32 v19, vcc, 3, v19
; VI-NEXT:    v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT:    v_add_u32_e32 v17, vcc, 3, v17
; VI-NEXT:    v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT:    v_add_u32_e32 v15, vcc, 3, v15
; VI-NEXT:    v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT:    v_add_u32_e32 v13, vcc, 3, v13
; VI-NEXT:    v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT:    v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT:  .LBB1_2: ; %end
; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
; VI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v22i32_to_v11i64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22
; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT:    s_cbranch_execz .LBB1_2
; GFX9-NEXT:  ; %bb.1: ; %cmp.true
; GFX9-NEXT:    v_add_u32_e32 v21, 3, v21
; GFX9-NEXT:    v_add_u32_e32 v20, 3, v20
; GFX9-NEXT:    v_add_u32_e32 v19, 3, v19
; GFX9-NEXT:    v_add_u32_e32 v18, 3, v18
; GFX9-NEXT:    v_add_u32_e32 v17, 3, v17
; GFX9-NEXT:    v_add_u32_e32 v16, 3, v16
; GFX9-NEXT:    v_add_u32_e32 v15, 3, v15
; GFX9-NEXT:    v_add_u32_e32 v14, 3, v14
; GFX9-NEXT:    v_add_u32_e32 v13, 3, v13
; GFX9-NEXT:    v_add_u32_e32 v12, 3, v12
; GFX9-NEXT:    v_add_u32_e32 v11, 3, v11
; GFX9-NEXT:    v_add_u32_e32 v10, 3, v10
; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
; GFX9-NEXT:  .LBB1_2: ; %end
; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v22i32_to_v11i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v22
; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT:    s_cbranch_execz .LBB1_2
; GFX11-NEXT:  ; %bb.1: ; %cmp.true
; GFX11-NEXT:    v_add_nc_u32_e32 v21, 3, v21
; GFX11-NEXT:    v_add_nc_u32_e32 v20, 3, v20
; GFX11-NEXT:    v_add_nc_u32_e32 v19, 3, v19
; GFX11-NEXT:    v_add_nc_u32_e32 v18, 3, v18
; GFX11-NEXT:    v_add_nc_u32_e32 v17, 3, v17
; GFX11-NEXT:    v_add_nc_u32_e32 v16, 3, v16
; GFX11-NEXT:    v_add_nc_u32_e32 v15, 3, v15
; GFX11-NEXT:    v_add_nc_u32_e32 v14, 3, v14
; GFX11-NEXT:    v_add_nc_u32_e32 v13, 3, v13
; GFX11-NEXT:    v_add_nc_u32_e32 v12, 3, v12
; GFX11-NEXT:    v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT:  .LBB1_2: ; %end
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %cmp = icmp eq i32 %b, 0
  br i1 %cmp, label %cmp.true, label %cmp.false

cmp.true:
  %a1 = add <22 x i32> %a, splat (i32 3)
  %a2 = bitcast <22 x i32> %a1 to <11 x i64>
  br label %end

cmp.false:
  %a3 = bitcast <22 x i32> %a to <11 x i64>
  br label %end

end:
  %phi = phi <11 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
  ret <11 x i64> %phi
}