[GlobalISel][AArch64] Legalize/select G_(S/Z/ANY)_EXT for v8s8s
This adds legalization for G_SEXT, G_ZEXT, and G_ANYEXT for v8s8s.
We were falling back on G_ZEXT in arm64-vabs.ll before, preventing us from
selecting the @llvm.aarch64.neon.sabd.v8i8 intrinsic.
This adds legalizer support for those 3, which gives us selection via the
importer. Update the relevant tests (legalize-ext.mir, select-int-ext.mir) and
add a GISel line to arm64-vabs.ll.
Differential Revision: https://reviews.llvm.org/D60881
llvm-svn: 358715
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index 19fd1d1..4fb09bb 100644
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -316,7 +316,8 @@
// Extensions
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
- .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
+ .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32})
+ .legalFor({v8s16, v8s8});
getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index bb845ff..1b9eb2d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -169,3 +169,61 @@
$w0 = COPY %3(s32)
...
+---
+name: test_zext_v8s16_from_v8s8
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+ ; CHECK-LABEL: name: test_zext_v8s16_from_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK: $q0 = COPY [[ZEXT]](<8 x s16>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %1:fpr(<8 x s8>) = COPY $d0
+ %2:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
+ $q0 = COPY %2(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_sext_v8s16_from_v8s8
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+ ; CHECK-LABEL: name: test_sext_v8s16_from_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK: $q0 = COPY [[SEXT]](<8 x s16>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %1:fpr(<8 x s8>) = COPY $d0
+ %2:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
+ $q0 = COPY %2(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_anyext_v8s16_from_v8s8
+alignment: 2
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+ ; CHECK-LABEL: name: test_anyext_v8s16_from_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
+ ; CHECK: $q0 = COPY [[ANYEXT]](<8 x s16>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %1:fpr(<8 x s8>) = COPY $d0
+ %2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
+ $q0 = COPY %2(<8 x s16>)
+ RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
index 18764b3..eef07ba 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -6,16 +6,19 @@
define void @anyext_s64_from_s32() { ret void }
define void @anyext_s32_from_s8() { ret void }
+ define void @anyext_v8s16_from_v8s8() { ret void }
define void @zext_s64_from_s32() { ret void }
define void @zext_s32_from_s16() { ret void }
define void @zext_s32_from_s8() { ret void }
define void @zext_s16_from_s8() { ret void }
+ define void @zext_v8s16_from_v8s8() { ret void }
define void @sext_s64_from_s32() { ret void }
define void @sext_s32_from_s16() { ret void }
define void @sext_s32_from_s8() { ret void }
define void @sext_s16_from_s8() { ret void }
+ define void @sext_v8s16_from_v8s8() { ret void }
...
---
@@ -64,6 +67,31 @@
...
---
+name: anyext_v8s16_from_v8s8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: anyext_v8s16_from_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
+ ; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s8>) = COPY $d0
+ %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+---
name: zext_s64_from_s32
legalized: true
regBankSelected: true
@@ -158,6 +186,33 @@
...
---
+name: zext_v8s16_from_v8s8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: zext_v8s16_from_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
+ ; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s8>) = COPY $d0
+ %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+
+---
name: sext_s64_from_s32
legalized: true
regBankSelected: true
@@ -250,3 +305,30 @@
%3:gpr(s32) = G_ANYEXT %1
$w0 = COPY %3(s32)
...
+
+---
+name: sext_v8s16_from_v8s8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: sext_v8s16_from_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
+ ; CHECK: $q0 = COPY [[SSHLLv8i8_shift]]
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:fpr(<8 x s8>) = COPY $d0
+ %1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index c6af680b..36a0999 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1,9 +1,13 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
-
+; FALLBACK-NOT: remark:{{.*}}(<8 x s16>) = G_ZEXT %4:_(<8 x s8>)
+; FALLBACK-NOT: remark:{{.*}} sabdl8h
define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
;CHECK-LABEL: sabdl8h:
;CHECK: sabdl.8h
+;GISEL-LABEL: sabdl8h:
+;GISEL: sabdl.8h
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
