Merging r319130:
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r319130 | matze | 2017-11-27 17:17:52 -0800 (Mon, 27 Nov 2017) | 7 lines
ARM: Fix PR32578
https://llvm.org/PR32578
I simplified and converted the reproducer into a lit test.
Patch by Vedant Kumar!
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llvm-svn: 319181
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 6f380ae..00b788a 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -479,7 +479,7 @@
if (DPRCSSize > 0) {
// Since vpush register list cannot have gaps, there may be multiple vpush
// instructions in the prologue.
- while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
+ while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
LastPush = MBBI++;
}
diff --git a/llvm/test/CodeGen/ARM/pr32578.ll b/llvm/test/CodeGen/ARM/pr32578.ll
new file mode 100644
index 0000000..541ba35
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/pr32578.ll
@@ -0,0 +1,27 @@
+; RUN: llc -o - %s | FileCheck %s
+target triple = "armv7"
+
+; CHECK-LABEL: func:
+; CHECK: push {r11, lr}
+; CHECK: vpush {d8}
+; CEHCK: b .LBB0_2
+define arm_aapcscc double @func() {
+ br label %tailrecurse
+
+tailrecurse:
+ %v0 = load i16, i16* undef, align 8
+ %cond36.i = icmp eq i16 %v0, 3
+ br i1 %cond36.i, label %sw.bb.i, label %sw.epilog.i
+
+sw.bb.i:
+ %v1 = load double, double* undef, align 8
+ %call21.i = tail call arm_aapcscc double @func()
+ %mul.i = fmul double %v1, %call21.i
+ ret double %mul.i
+
+sw.epilog.i:
+ tail call arm_aapcscc void @_ZNK10shared_ptrdeEv()
+ br label %tailrecurse
+}
+
+declare arm_aapcscc void @_ZNK10shared_ptrdeEv() local_unnamed_addr
