services/system/common/vz_physheap_tc.c

/*************************************************************************/ /*!
@File           vz_physheap_tc.c
@Title          System virtualization physheap configuration
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description    System virtualization physical heap configuration
@License        MIT

The contents of this file are subject to the MIT license as set out below.

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

This License is also included in this distribution in the file called
"MIT-COPYING".

EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/
#include "allocmem.h"
#include "physheap.h"
#include "rgxdevice.h"
#include "pvrsrv_device.h"
#include "rgxfwutils.h"

#include "dma_support.h"
#include "vz_support.h"
#include "vz_vmm_pvz.h"
#include "vz_physheap.h"

/* Valid values for the TC_MEMORY_CONFIG configuration option */
#define TC_MEMORY_LOCAL			(1)
#define TC_MEMORY_HOST			(2)
#define TC_MEMORY_HYBRID		(3)

/* Valid values for PHYS_HEAP_CONFIG identification */
#define PHYS_HEAP_ID_DISPLAY	(1)

static PVRSRV_ERROR
SysVzCreateDisplayPhysHeap(PVRSRV_DEVICE_CONFIG *psDevConfig)
{
#if defined(SUPPORT_DISPLAY_CLASS) && defined(CONFIG_L4)
	IMG_UINT32 ui32Idx;

	/* First, we locate the display physical heap configuration via ID */
	for (ui32Idx = 0; ui32Idx < psDevConfig->ui32PhysHeapCount; ui32Idx++)
	{
		if (psDevConfig->pasPhysHeaps[ui32Idx].ui32PhysHeapID == PHYS_HEAP_ID_DISPLAY)
		{
			PVR_ASSERT(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].sStartAddr.uiAddr);
			PVR_ASSERT(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].uiSize);
			break;
		}
	}

	if (ui32Idx >= psDevConfig->ui32PhysHeapCount)
	{
		PVR_DPF((PVR_DBG_ERROR,
				"SysVzCreateDisplayPhysHeap: No display physical heap present\n"));
		return PVRSRV_ERROR_INVALID_PARAMS;
	}

	/* Technically, only one OSID/VM should be using the PDP at any one time though more than
	   one OSID/VM can have this mapped with concurrent usage leading to display corruption */
	psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].hPrivData =
		OSMapPhysToLin(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].sStartAddr,
					   psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].uiSize,
					   PVRSRV_MEMALLOCFLAG_CPU_UNCACHED);
	if (psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].hPrivData == NULL)
	{
		PVR_DPF((PVR_DBG_ERROR,
				"SysVzCreateDisplayPhysHeap: OSMapPhysToLin: paddr: %llx, size: %llx failed\n",
				(IMG_UINT64)psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].sStartAddr.uiAddr,
				(IMG_UINT64)psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].uiSize));
		return PVRSRV_ERROR_DEVICEMEM_MAP_FAILED;
	}
#else
	PVR_UNREFERENCED_PARAMETER(psDevConfig);
#endif
	return PVRSRV_OK;
}

static void
SysVzDestroyDisplayPhysHeap(PVRSRV_DEVICE_CONFIG *psDevConfig)
{
#if defined(SUPPORT_DISPLAY_CLASS) && defined(CONFIG_L4)
	IMG_UINT32 ui32Idx;

	for (ui32Idx = 0; ui32Idx < psDevConfig->ui32PhysHeapCount; ui32Idx++)
	{
		if (psDevConfig->pasPhysHeaps[ui32Idx].ui32PhysHeapID == PHYS_HEAP_ID_DISPLAY)
		{
			PVR_ASSERT(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].sStartAddr.uiAddr);
			PVR_ASSERT(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].hPrivData);
			PVR_ASSERT(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].uiSize);
			break;
		}
	}

	if (ui32Idx == psDevConfig->ui32PhysHeapCount)
	{
		return;
	}

	OSUnMapPhysToLin(psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].hPrivData,
					 psDevConfig->pasPhysHeaps[ui32Idx].pasRegions[0].uiSize,
					 PVRSRV_MEMALLOCFLAG_CPU_UNCACHED);
#else
	PVR_UNREFERENCED_PARAMETER(psDevConfig);
#endif
}

static PVRSRV_ERROR
SysVzCreateGpuFwPhysHeap(PVRSRV_DEVICE_CONFIG *psDevConfig)
{
	PVRSRV_ERROR eError = PVRSRV_OK;
	PVRSRV_DEVICE_PHYS_HEAP eHeapType;
	PHYS_HEAP_CONFIG *psPhysHeapConfig;
	PHYS_HEAP_CONFIG *psGpuPhysHeapConfig = NULL;
#if defined(CONFIG_L4)
	IMG_CPU_PHYADDR sPhysHeapConfigMapAddr;
#endif

	for (eHeapType=0; eHeapType < PVRSRV_DEVICE_PHYS_HEAP_LAST; eHeapType++)
	{
		switch(eHeapType)
		{
			/* Only interested in these physheap */
			case PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL:
			case PVRSRV_DEVICE_PHYS_HEAP_FW_LOCAL:
				break;
			default:
				continue;
		}

		/* Look up the firmware/graphics physical heap configuration */
		psPhysHeapConfig = SysVzGetPhysHeapConfig(psDevConfig, eHeapType);
		PVR_ASSERT(psPhysHeapConfig && psPhysHeapConfig->pasRegions);
		psPhysHeapConfig->pasRegions[0].hPrivData = NULL;

		eError = SysVzGetPhysHeapAddrSize(psDevConfig,
										  eHeapType,
										  SysVzGetMemoryConfigPhysHeapType(),
										  &psPhysHeapConfig->pasRegions[0].sCardBase,
										  &psPhysHeapConfig->pasRegions[0].uiSize);
		if (eError != PVRSRV_OK)
		{
			return eError;
		}
		else
		{
			if (psPhysHeapConfig->ui32NumOfRegions == 0)
			{
				psPhysHeapConfig->ui32NumOfRegions++;
			}
		}

		switch(eHeapType)
		{
			case PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL:
				psGpuPhysHeapConfig = psPhysHeapConfig;
#if (TC_MEMORY_CONFIG == TC_MEMORY_HOST)
				/* In this config all OSID point to their respective carve-out
				   as both device and processor view of memory is identical */
				psPhysHeapConfig->pasRegions[0].sStartAddr.uiAddr =
						psPhysHeapConfig->pasRegions[0].sCardBase.uiAddr;
#endif
				PVR_ASSERT(psPhysHeapConfig->pasRegions[0].sCardBase.uiAddr != 0);
				PVR_ASSERT(psPhysHeapConfig->pasRegions[0].uiSize != 0);
				break;

			case PVRSRV_DEVICE_PHYS_HEAP_FW_LOCAL:
#if (TC_MEMORY_CONFIG == TC_MEMORY_LOCAL)
				/* In this config, sStartAddr has already been looked-up in the
				   system layer using PCI/BAR; this value is identical for all
				   OSID hence all OSID point to the same CPU start address */
				psPhysHeapConfig->pasRegions[0].sStartAddr.uiAddr =
						psGpuPhysHeapConfig->pasRegions[0].sStartAddr.uiAddr;
#elif (TC_MEMORY_CONFIG == TC_MEMORY_HOST)
				psPhysHeapConfig->pasRegions[0].sStartAddr.uiAddr =
						psPhysHeapConfig->pasRegions[0].sCardBase.uiAddr;
				PVR_ASSERT(psPhysHeapConfig->pasRegions[0].sCardBase.uiAddr != 0);
#endif
				PVR_ASSERT(psPhysHeapConfig->pasRegions[0].uiSize != 0);
				break;

			default:
				PVR_ASSERT(0);
		}

#if defined(CONFIG_L4)
		sPhysHeapConfigMapAddr.uiAddr =
				psPhysHeapConfig->pasRegions[0].sStartAddr.uiAddr;

#if (TC_MEMORY_CONFIG == TC_MEMORY_LOCAL)
		/* Technically we do not need this but for security each
		   OSID should map its own subset of the LMA card memory,
		   this way, we protect device memory from CPU VM side
		   memory corruption */
		sPhysHeapConfigMapAddr.uiAddr += 
				psPhysHeapConfig->pasRegions[0].sCardBase.uiAddr;
#endif

		/* On Fiasco.OC/l4linux, ioremap physheap now */
		psPhysHeapConfig->pasRegions[0].hPrivData =
							OSMapPhysToLin(
								sPhysHeapConfigMapAddr,
								psPhysHeapConfig->pasRegions[0].uiSize,
								PVRSRV_MEMALLOCFLAG_CPU_UNCACHED
							);
		if (psPhysHeapConfig->pasRegions[0].hPrivData == NULL)
		{
			PVR_DPF((PVR_DBG_ERROR,
					"l4linux: OSMapPhysToLin: paddr: %llx, size: %llx failed\n",
					(IMG_UINT64)sPhysHeapConfigMapAddr.uiAddr,
					(IMG_UINT64)psPhysHeapConfig->pasRegions[0].uiSize));
			return PVRSRV_ERROR_DEVICEMEM_MAP_FAILED;
		}
#endif
	}

	return  eError;
}

static void
SysVzDestroyGpuFwPhysHeap(PVRSRV_DEVICE_CONFIG *psDevConfig)
{
	PVRSRV_DEVICE_PHYS_HEAP eHeapType;
	PHYS_HEAP_CONFIG *psPhysHeapConfig;

	for (eHeapType=0; eHeapType < PVRSRV_DEVICE_PHYS_HEAP_LAST; eHeapType++)
	{
		switch(eHeapType)
		{
			case PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL:
			case PVRSRV_DEVICE_PHYS_HEAP_FW_LOCAL:
				break;
			default:
				continue;
		}

		psPhysHeapConfig = SysVzGetPhysHeapConfig(psDevConfig, eHeapType);
		PVR_ASSERT(psPhysHeapConfig && psPhysHeapConfig->pasRegions);

#if defined(CONFIG_L4)
		OSUnMapPhysToLin(psPhysHeapConfig->pasRegions[0].hPrivData,
						 psPhysHeapConfig->pasRegions[0].uiSize,
						 PVRSRV_MEMALLOCFLAG_CPU_UNCACHED);
		psPhysHeapConfig->pasRegions[0].hPrivData = NULL;
#endif
	}
}

PHYS_HEAP_TYPE SysVzGetMemoryConfigPhysHeapType(void)
{
#if (TC_MEMORY_CONFIG == TC_MEMORY_HOST)
	return PHYS_HEAP_TYPE_UMA;
#else
	return PHYS_HEAP_TYPE_LMA;
#endif
}

PVRSRV_ERROR SysVzInitDevPhysHeaps(PVRSRV_DEVICE_CONFIG *psDevConfig)
{
	PVRSRV_ERROR eError;

	eError = SysVzCreateGpuFwPhysHeap(psDevConfig);
	if (eError == PVRSRV_OK)
	{
		eError = SysVzCreateDisplayPhysHeap(psDevConfig);
	}

	return eError;
}

void SysVzDeInitDevPhysHeaps(PVRSRV_DEVICE_CONFIG *psDevConfig)
{
	SysVzDestroyDisplayPhysHeap(psDevConfig);
	SysVzDestroyGpuFwPhysHeap(psDevConfig);
}

/******************************************************************************
 End of file (vz_physheap_tc.c)
******************************************************************************/