CPU spin equivalent for sparc. (#217)
Normally tailored for each model but here the least common denominator as reading the Conditions Code Register couple of time.
diff --git a/rpmalloc/rpmalloc.c b/rpmalloc/rpmalloc.c
index a5c6ad6..4149283 100644
--- a/rpmalloc/rpmalloc.c
+++ b/rpmalloc/rpmalloc.c
@@ -755,6 +755,8 @@
#elif defined(__powerpc__) || defined(__powerpc64__)
// No idea if ever been compiled in such archs but ... as precaution
__asm__ volatile("or 27,27,27");
+#elif defined(__sparc__)
+ __asm__ volatile("rd %ccr, %g0 \n\trd %ccr, %g0 \n\trd %ccr, %g0");
#else
struct timespec ts = {0};
nanosleep(&ts, 0);
