| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s |
| |
| --- | |
| define dso_local <4 x i32> @invariant_predicated_add_use(i16* nocapture readonly %a, i32* %c, i32 %N, <4 x i32> %pass) #0 { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> |
| %acc.next = tail call <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32> %pass, <4 x i32> %tmp10, <4 x i1> %tmp8, <4 x i32> undef) |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp12 = icmp ne i32 %tmp11, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp12, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi <4 x i32> [ zeroinitializer, %entry ], [ %acc.next, %vector.body ] |
| ret <4 x i32> %res |
| } |
| |
| declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) |
| declare void @llvm.set.loop.iterations.i32(i32) |
| declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) |
| declare <4 x i1> @llvm.arm.mve.vctp32(i32) |
| declare <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) |
| |
| ... |
| --- |
| name: invariant_predicated_add_use |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: invariant_predicated_add_use |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCBZ $r2, %bb.3 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r2 |
| ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000) |
| ; CHECK: liveins: $lr, $q0, $r0 |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, undef renamable $q1 |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 |
| ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 |
| ; CHECK: bb.4.exit: |
| ; CHECK: liveins: $q1 |
| ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit killed $q1 |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 |
| bb.0.entry: |
| successors: %bb.3(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCBZ $r2, %bb.3 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r2 |
| |
| renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg |
| renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg |
| renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| t2DoLoopStart renamable $r3 |
| $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.4(0x04000000) |
| liveins: $q0, $r0, $r1, $r2 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| $lr = tMOVr $r1, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| MVE_VPST 4, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.4, 14 /* CC::al */, $noreg |
| |
| bb.3: |
| successors: %bb.4(0x80000000) |
| |
| renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 |
| |
| bb.4.exit: |
| liveins: $q1 |
| |
| renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg |
| renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit $q1 |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 |
| |
| ... |
