| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s |
| |
| --- | |
| define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(i32* noalias nocapture %0, i32* nocapture readonly %1, i32 %2, i32 %3) { |
| %5 = icmp eq i32 %3, 2 |
| %6 = select i1 %5, i32 2, i32 4 |
| %7 = icmp eq i32 %3, 4 |
| %8 = select i1 %7, i32 1, i32 %6 |
| %9 = shl i32 %2, %8 |
| %10 = icmp eq i32 %9, 0 |
| %11 = add i32 %9, 3 |
| %12 = lshr i32 %11, 2 |
| %13 = shl nuw i32 %12, 2 |
| %14 = add i32 %13, -4 |
| %15 = lshr i32 %14, 2 |
| %16 = add nuw nsw i32 %15, 1 |
| br i1 %10, label %34, label %17 |
| |
| 17: ; preds = %4 |
| call void @llvm.set.loop.iterations.i32(i32 %16) |
| br label %18 |
| |
| 18: ; preds = %18, %17 |
| %19 = phi i32* [ %31, %18 ], [ %0, %17 ] |
| %20 = phi i32* [ %30, %18 ], [ %1, %17 ] |
| %21 = phi i32 [ %16, %17 ], [ %32, %18 ] |
| %22 = phi i32 [ %9, %17 ], [ %26, %18 ] |
| %23 = bitcast i32* %19 to <4 x i32>* |
| %24 = bitcast i32* %20 to <4 x i32>* |
| %25 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %22) |
| %26 = sub i32 %22, 4 |
| %27 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %24, i32 4, <4 x i1> %25, <4 x i32> undef) |
| %28 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %23, i32 4, <4 x i1> %25, <4 x i32> undef) |
| %29 = mul nsw <4 x i32> %28, %27 |
| call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %29, <4 x i32>* %23, i32 4, <4 x i1> %25) |
| %30 = getelementptr i32, i32* %20, i32 4 |
| %31 = getelementptr i32, i32* %19, i32 4 |
| %32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1) |
| %33 = icmp ne i32 %32, 0 |
| br i1 %33, label %18, label %34 |
| |
| 34: ; preds = %18, %4 |
| ret void |
| } |
| declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) |
| declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) |
| declare void @llvm.set.loop.iterations.i32(i32) |
| declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) |
| declare <4 x i1> @llvm.arm.mve.vctp32(i32) |
| |
| ... |
| --- |
| name: multi_cond_iter_count |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: multi_cond_iter_count |
| ; CHECK: bb.0 (%ir-block.4): |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 |
| ; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: t2IT 1, 8, implicit-def $itstate |
| ; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate |
| ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate |
| ; CHECK: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg |
| ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 |
| ; CHECK: bb.1 (%ir-block.18): |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r3 |
| ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg |
| ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg |
| ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg |
| ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 |
| ; CHECK: bb.2 (%ir-block.34): |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0 (%ir-block.4): |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r3, $lr |
| |
| frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| $r7 = frame-setup tMOVr $sp, 14, $noreg |
| frame-setup CFI_INSTRUCTION def_cfa_register $r7 |
| tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr |
| $r12 = tMOVr $r3, 14, $noreg |
| t2IT 1, 8, implicit-def $itstate |
| $r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate |
| tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| $r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate |
| renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg |
| renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg |
| $r3 = tMOVr $r0, 14, $noreg |
| t2DoLoopStart renamable $lr |
| |
| bb.1 (%ir-block.18): |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $lr, $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| MVE_VPST 4, implicit $vpr |
| renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr |
| renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg |
| renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| MVE_VPST 8, implicit $vpr |
| MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| $r0 = tMOVr $r3, 14, $noreg |
| t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14, $noreg |
| |
| bb.2 (%ir-block.34): |
| tPOP_RET 14, $noreg, def $r7, def $pc |
| |
| ... |
