llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir - third_party/github.com/llvm/llvm-project - Git at Google

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 --- |
   define dso_local void @incorrect_sub_16(i16* noalias nocapture %A, i16* noalias nocapture readonly %B, i16* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
   entry:
     %cmp8 = icmp sgt i32 %N, 0
     %0 = add i32 %N, 3
     %1 = lshr i32 %0, 2
     %2 = shl nuw i32 %1, 2
     %3 = add i32 %2, -4
     %4 = lshr i32 %3, 2
     %5 = add nuw nsw i32 %4, 1
     br i1 %cmp8, label %vector.ph, label %for.cond.cleanup

   vector.ph:                                        ; preds = %entry
     call void @llvm.set.loop.iterations.i32(i32 %5)
     br label %vector.body

   vector.body:                                      ; preds = %vector.body, %vector.ph
     %lsr.iv17 = phi i16* [ %scevgep18, %vector.body ], [ %A, %vector.ph ]
     %lsr.iv14 = phi i16* [ %scevgep15, %vector.body ], [ %C, %vector.ph ]
     %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %B, %vector.ph ]
     %6 = phi i32 [ %5, %vector.ph ], [ %11, %vector.body ]
     %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
     %lsr.iv13 = bitcast i16* %lsr.iv to <8 x i16>*
     %lsr.iv1416 = bitcast i16* %lsr.iv14 to <8 x i16>*
     %lsr.iv1719 = bitcast i16* %lsr.iv17 to <8 x i16>*
     %8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %7)
     %9 = sub i32 %7, 7
     %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv13, i32 4, <8 x i1> %8, <8 x i16> undef)
     %wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv1416, i32 4, <8 x i1> %8, <8 x i16> undef)
     %10 = add nsw <8 x i16> %wide.masked.load12, %wide.masked.load
     call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %10, <8 x i16>* %lsr.iv1719, i32 4, <8 x i1> %8)
     %scevgep = getelementptr i16, i16* %lsr.iv, i32 8
     %scevgep15 = getelementptr i16, i16* %lsr.iv14, i32 8
     %scevgep18 = getelementptr i16, i16* %lsr.iv17, i32 8
     %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
     %12 = icmp ne i32 %11, 0
     br i1 %12, label %vector.body, label %for.cond.cleanup

   for.cond.cleanup:                                 ; preds = %vector.body, %entry
     ret void
   }
   declare void @llvm.set.loop.iterations.i32(i32)
   declare <8 x i1> @llvm.arm.mve.vctp16(i32)
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
   declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
   declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
 ...
 ---
 name:            incorrect_sub_16
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 hasWinCFI:       false
 registers:       []
 liveins:
   - { reg: '$r0', virtual-reg: '' }
   - { reg: '$r1', virtual-reg: '' }
   - { reg: '$r2', virtual-reg: '' }
   - { reg: '$r3', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       8
   offsetAdjustment: 0
   maxAlignment:    4
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   cvBytesOfCalleeSavedRegisters: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:      []
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: incorrect_sub_16
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
   ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
   ; CHECK:   t2IT 11, 8, implicit-def $itstate
   ; CHECK:   tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
   ; CHECK:   renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
   ; CHECK:   $lr = t2DLS killed renamable $lr
   ; CHECK: bb.1.vector.body:
   ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
   ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
   ; CHECK:   renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
   ; CHECK:   MVE_VPST 4, implicit $vpr
   ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
   ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
   ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg
   ; CHECK:   renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   MVE_VPST 8, implicit $vpr
   ; CHECK:   renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
   ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.1
   ; CHECK: bb.2.for.cond.cleanup:
   ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1, $r2, $r3, $r7, $lr

     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr
     t2IT 11, 8, implicit-def $itstate
     tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate
     renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
     renamable $lr = t2MOVi 1, 14, $noreg, $noreg
     renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
     renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
     renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
     t2DoLoopStart renamable $lr

   bb.1.vector.body:
     successors: %bb.1(0x7c000000), %bb.2(0x04000000)
     liveins: $lr, $r0, $r1, $r2, $r3

     renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
     MVE_VPST 4, implicit $vpr
     renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
     renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
     renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg
     renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
     MVE_VPST 8, implicit $vpr
     renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
     tB %bb.2, 14, $noreg

   bb.2.for.cond.cleanup:
     tPOP_RET 14, $noreg, def $r7, def $pc

 ...
	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - \| FileCheck %s
	--- \|
	define dso_local void @incorrect_sub_16(i16* noalias nocapture %A, i16* noalias nocapture readonly %B, i16* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
	entry:
	%cmp8 = icmp sgt i32 %N, 0
	%0 = add i32 %N, 3
	%1 = lshr i32 %0, 2
	%2 = shl nuw i32 %1, 2
	%3 = add i32 %2, -4
	%4 = lshr i32 %3, 2
	%5 = add nuw nsw i32 %4, 1
	br i1 %cmp8, label %vector.ph, label %for.cond.cleanup

	vector.ph: ; preds = %entry
	call void @llvm.set.loop.iterations.i32(i32 %5)
	br label %vector.body

	vector.body: ; preds = %vector.body, %vector.ph
	%lsr.iv17 = phi i16* [ %scevgep18, %vector.body ], [ %A, %vector.ph ]
	%lsr.iv14 = phi i16* [ %scevgep15, %vector.body ], [ %C, %vector.ph ]
	%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %B, %vector.ph ]
	%6 = phi i32 [ %5, %vector.ph ], [ %11, %vector.body ]
	%7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
	%lsr.iv13 = bitcast i16* %lsr.iv to <8 x i16>*
	%lsr.iv1416 = bitcast i16* %lsr.iv14 to <8 x i16>*
	%lsr.iv1719 = bitcast i16* %lsr.iv17 to <8 x i16>*
	%8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %7)
	%9 = sub i32 %7, 7
	%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv13, i32 4, <8 x i1> %8, <8 x i16> undef)
	%wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv1416, i32 4, <8 x i1> %8, <8 x i16> undef)
	%10 = add nsw <8 x i16> %wide.masked.load12, %wide.masked.load
	call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %10, <8 x i16>* %lsr.iv1719, i32 4, <8 x i1> %8)
	%scevgep = getelementptr i16, i16* %lsr.iv, i32 8
	%scevgep15 = getelementptr i16, i16* %lsr.iv14, i32 8
	%scevgep18 = getelementptr i16, i16* %lsr.iv17, i32 8
	%11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
	%12 = icmp ne i32 %11, 0
	br i1 %12, label %vector.body, label %for.cond.cleanup

	for.cond.cleanup: ; preds = %vector.body, %entry
	ret void
	}
	declare void @llvm.set.loop.iterations.i32(i32)
	declare <8 x i1> @llvm.arm.mve.vctp16(i32)
	declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
	declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
	declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
	...
	---
	name: incorrect_sub_16
	alignment: 2
	exposesReturnsTwice: false
	legalized: false
	regBankSelected: false
	selected: false
	failedISel: false
	tracksRegLiveness: true
	hasWinCFI: false
	registers: []
	liveins:
	- { reg: '$r0', virtual-reg: '' }
	- { reg: '$r1', virtual-reg: '' }
	- { reg: '$r2', virtual-reg: '' }
	- { reg: '$r3', virtual-reg: '' }
	frameInfo:
	isFrameAddressTaken: false
	isReturnAddressTaken: false
	hasStackMap: false
	hasPatchPoint: false
	stackSize: 8
	offsetAdjustment: 0
	maxAlignment: 4
	adjustsStack: false
	hasCalls: false
	stackProtector: ''
	maxCallFrameSize: 0
	cvBytesOfCalleeSavedRegisters: 0
	hasOpaqueSPAdjustment: false
	hasVAStart: false
	hasMustTailInVarArgFunc: false
	localFrameSize: 0
	savePoint: ''
	restorePoint: ''
	fixedStack: []
	stack:
	- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
	stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
	debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
	- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
	stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
	debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
	callSites: []
	constants: []
	machineFunctionInfo: {}
	body: \|
	; CHECK-LABEL: name: incorrect_sub_16
	; CHECK: bb.0.entry:
	; CHECK: successors: %bb.1(0x80000000)
	; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7
	; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
	; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
	; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
	; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
	; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
	; CHECK: t2IT 11, 8, implicit-def $itstate
	; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
	; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
	; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
	; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
	; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
	; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
	; CHECK: $lr = t2DLS killed renamable $lr
	; CHECK: bb.1.vector.body:
	; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
	; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
	; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
	; CHECK: MVE_VPST 4, implicit $vpr
	; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
	; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
	; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg
	; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
	; CHECK: MVE_VPST 8, implicit $vpr
	; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
	; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
	; CHECK: bb.2.for.cond.cleanup:
	; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
	bb.0.entry:
	successors: %bb.1(0x80000000)
	liveins: $r0, $r1, $r2, $r3, $r7, $lr

	frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
	frame-setup CFI_INSTRUCTION def_cfa_offset 8
	frame-setup CFI_INSTRUCTION offset $lr, -4
	frame-setup CFI_INSTRUCTION offset $r7, -8
	tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr
	t2IT 11, 8, implicit-def $itstate
	tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate
	renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
	renamable $lr = t2MOVi 1, 14, $noreg, $noreg
	renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
	renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
	renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
	t2DoLoopStart renamable $lr

	bb.1.vector.body:
	successors: %bb.1(0x7c000000), %bb.2(0x04000000)
	liveins: $lr, $r0, $r1, $r2, $r3

	renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
	MVE_VPST 4, implicit $vpr
	renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
	renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
	renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg
	renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
	MVE_VPST 8, implicit $vpr
	renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
	renamable $lr = t2LoopDec killed renamable $lr, 1
	t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
	tB %bb.2, 14, $noreg

	bb.2.for.cond.cleanup:
	tPOP_RET 14, $noreg, def $r7, def $pc

	...