| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 |
| --- | |
| |
| @float_align1 = common global float 0.000000e+00, align 1 |
| @float_align4 = common global float 0.000000e+00, align 4 |
| @i32_align8 = common global i32 0, align 8 |
| |
| define float @load_float_align1() { |
| entry: |
| %0 = load float, float* @float_align1, align 1 |
| ret float %0 |
| } |
| |
| define float @load_float_align4() { |
| entry: |
| %0 = load float, float* @float_align4, align 4 |
| ret float %0 |
| } |
| |
| define i32 @load_i32_align8() { |
| entry: |
| %0 = load i32, i32* @i32_align8, align 8 |
| ret i32 %0 |
| } |
| |
| ... |
| --- |
| name: load_float_align1 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| ; MIPS32-LABEL: name: load_float_align1 |
| ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1 |
| ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1 |
| ; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF |
| ; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load 4 from @float_align1, align 1) |
| ; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load 4 from @float_align1, align 1) |
| ; MIPS32: $f0 = COPY [[LWR]] |
| ; MIPS32: RetRA implicit $f0 |
| %1:gprb(p0) = G_GLOBAL_VALUE @float_align1 |
| %0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1) |
| $f0 = COPY %0(s32) |
| RetRA implicit $f0 |
| |
| ... |
| --- |
| name: load_float_align4 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| ; MIPS32-LABEL: name: load_float_align4 |
| ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4 |
| ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4 |
| ; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align4) |
| ; MIPS32: $f0 = COPY [[LWC1_]] |
| ; MIPS32: RetRA implicit $f0 |
| %1:gprb(p0) = G_GLOBAL_VALUE @float_align4 |
| %0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4) |
| $f0 = COPY %0(s32) |
| RetRA implicit $f0 |
| |
| ... |
| --- |
| name: load_i32_align8 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| ; MIPS32-LABEL: name: load_i32_align8 |
| ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8 |
| ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8 |
| ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load 4 from @i32_align8, align 8) |
| ; MIPS32: $v0 = COPY [[LW]] |
| ; MIPS32: RetRA implicit $v0 |
| %1:gprb(p0) = G_GLOBAL_VALUE @i32_align8 |
| %0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8) |
| $v0 = COPY %0(s32) |
| RetRA implicit $v0 |
| |
| ... |