llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser can parse multiple register machine
# operands before '='.

# This tests that a MIR file with no vregs does not get altered by mir-canon.
# RUN: llc -mtriple=aarch64 -o - -run-pass mir-canonicalizer -verify-machineinstrs %s

--- |

  declare void @foo()

  define void @trivial_fp_func() {
  entry:
    call void @foo()
    ret void
  }

...
---
name:            trivial_fp_func
body: |
  bb.0.entry:
    liveins: $lr, $fp, $lr, $fp

    $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
    $fp = frame-setup ADDXri $sp, 0, 0
    BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
  ; CHECK: $sp, $fp, $lr = LDPXpost $sp, 2
    $sp, $fp, $lr = LDPXpost $sp, 2
    RET_ReallyLR
...