llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

---
name:            select_from_different_results_of_unmerge_values
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: select_from_different_results_of_unmerge_values
    ; GCN: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; GCN: [[DEF1:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
    ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
    ; GCN: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[DEF1]](s1), [[UV]], [[UV1]]
    ; GCN: $vgpr0 = COPY [[SELECT]](s32)
    ; GCN: SI_RETURN_TO_EPILOG $vgpr0
    %2:_(<2 x s32>) = G_IMPLICIT_DEF
    %4:_(s1) = G_IMPLICIT_DEF
    %0:_(s32), %1:_(s32) = G_UNMERGE_VALUES %2:_(<2 x s32>)
    %3:_(s32) = G_SELECT %4:_(s1), %0:_, %1:_
    $vgpr0 = COPY %3
    SI_RETURN_TO_EPILOG $vgpr0

...

---
name:            select_from_same_results_of_unmerge_values
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: select_from_same_results_of_unmerge_values
    ; GCN: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
    ; GCN: $vgpr0 = COPY [[UV]](s32)
    ; GCN: SI_RETURN_TO_EPILOG $vgpr0
    %2:_(<2 x s32>) = G_IMPLICIT_DEF
    %4:_(s1) = G_IMPLICIT_DEF
    %0:_(s32), %1:_(s32) = G_UNMERGE_VALUES %2:_(<2 x s32>)
    %3:_(s32) = G_SELECT %4:_(s1), %0:_, %0:_
    $vgpr0 = COPY %3
    SI_RETURN_TO_EPILOG $vgpr0

...