[X86] Add ACE v1 (AI Compute Extensions) support ACE v1 introduces new tile-based matrix operations with fixed 16x64 tile dimensions (Palette 2), unlike AMX's configurable dimensions. Key features: - New __acetile type with fixed 16x64 dimensions - __tile_ace_* intrinsics for ACE tile operations - Outer product instructions: TOP4BUUD, TOP4BUSD, TOP4BSSD, TOP4BSUD, TOP2BF16PS - Mixed precision FP8 instructions: TOP4MX variants - Tile movement: TILEMOVROW, TILEMOVCOL for ZMM<->tile transfers - BSR (Block Scale Register) operations for scaling factors - ACE tile spill/reload using TILEMOVROW + VMOVUPS row-by-row (ACE doesn't have TILELOADD/TILESTORED instructions) Backend changes: - X86LowerTileCopy handles ACE tile copies - X86PreTileConfig/X86FastPreTileConfig for ACE register allocation - Palette 2 tile configuration support Reused from AMX: - The x86_amx type - AMX-AVX512f definitions and TILE instruction definitions - Passes for lowering and handling the x86_amx type - Wrappers internally use rows and cols to use amx definitions This PR builds on PR #206888 and should be reviewed after/with it.
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