)]}' { "commit": "2fef65cf0d6c4830d6b5896c5597566f4ea97c20", "tree": "817e8fafbe551adfcf15df30b7811f99a12d9f50", "parents": [ "777ec1fff4502f6913818de5970a1c060a966877" ], "author": { "name": "Ganesh Gopalasubramanian", "email": "Ganesh.Gopalasubramanian@amd.com", "time": "Wed Jul 08 00:41:01 2026 +0530" }, "committer": { "name": "Ganesh Gopalasubramanian", "email": "Ganesh.Gopalasubramanian@amd.com", "time": "Thu Jul 09 16:28:12 2026 +0530" }, "message": "[X86] Add ACE v1 (AI Compute Extensions) support\n\nACE v1 introduces new tile-based matrix operations with fixed 16x64\ntile dimensions (Palette 2), unlike AMX\u0027s configurable dimensions.\n\nKey features:\n- New __acetile type with fixed 16x64 dimensions\n- __tile_ace_* intrinsics for ACE tile operations\n- Outer product instructions: TOP4BUUD, TOP4BUSD, TOP4BSSD, TOP4BSUD, TOP2BF16PS\n- Mixed precision FP8 instructions: TOP4MX variants\n- Tile movement: TILEMOVROW, TILEMOVCOL for ZMM\u003c-\u003etile transfers\n- BSR (Block Scale Register) operations for scaling factors\n- ACE tile spill/reload using TILEMOVROW + VMOVUPS row-by-row\n (ACE doesn\u0027t have TILELOADD/TILESTORED instructions)\n\nBackend changes:\n- X86LowerTileCopy handles ACE tile copies\n- X86PreTileConfig/X86FastPreTileConfig for ACE register allocation\n- Palette 2 tile configuration support\n\nReused from AMX:\n- The x86_amx type\n- AMX-AVX512f definitions and TILE instruction definitions\n- Passes for lowering and handling the x86_amx type\n- Wrappers internally use rows and cols to use amx definitions\n\nThis PR builds on PR #206888 and should be reviewed after/with it.\n", "tree_diff": [ { "type": "modify", "old_id": "0a98b3049df343afb2a1ad9449717242b957d824", "old_mode": 33188, "old_path": "clang/include/clang/Basic/BuiltinsX86_64.td", "new_id": "6f342561391443d080a8a3948b74579cdf4a433e", "new_mode": 33188, "new_path": "clang/include/clang/Basic/BuiltinsX86_64.td" }, { "type": "modify", "old_id": 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