)]}' { "commit": "4fd84d6fad4b02f989cc85bee2095d9b204bc23d", "tree": "de8f10184d9dc36578684ce329cc5705d5900b2c", "parents": [ "2fef65cf0d6c4830d6b5896c5597566f4ea97c20" ], "author": { "name": "Ganesh Gopalasubramanian", "email": "Ganesh.Gopalasubramanian@amd.com", "time": "Tue Sep 01 18:07:40 2026 +0530" }, "committer": { "name": "Ganesh Gopalasubramanian", "email": "Ganesh.Gopalasubramanian@amd.com", "time": "Tue Sep 01 19:06:11 2026 +0530" }, "message": "Address review comments\n\n- Rename the ACE tests and directories to acev1 for consistency\n- Build acev1 on top of avx10.1 rather than avx10.2\n- Fix test encodings and the BSR0 implicit defs\n- Make the scale register type consistent with the spec\n- Add memory operand tests for bsrmov\n- Confirm the ACEV1 ISA implication chain\n- Take the outer product ZMM sources by value instead of by register ID,\n so they are allocated conventionally, and mark the 512-bit ACE builtins\n with RequiredVectorWidth\u003c512\u003e\n- Use pseudos for SPILL and RELOAD. Spills use scratch zmm. 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