| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s |
| |
| target triple = "aarch64" |
| |
| ; Expected to transform |
| define <vscale x 4 x i32> @complex_add_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: complex_add_v4i32: |
| ; CHECK: // %bb.0: // %entry |
| ; CHECK-NEXT: cadd z1.s, z1.s, z0.s, #90 |
| ; CHECK-NEXT: mov z0.d, z1.d |
| ; CHECK-NEXT: ret |
| entry: |
| %a.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %a) |
| %a.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 0 |
| %a.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 1 |
| %b.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %b) |
| %b.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 0 |
| %b.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 1 |
| %0 = sub <vscale x 2 x i32> %b.real, %a.imag |
| %1 = add <vscale x 2 x i32> %b.imag, %a.real |
| %interleaved.vec = tail call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1) |
| ret <vscale x 4 x i32> %interleaved.vec |
| } |
| |
| ; Expected to transform |
| define <vscale x 8 x i32> @complex_add_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) { |
| ; CHECK-LABEL: complex_add_v8i32: |
| ; CHECK: // %bb.0: // %entry |
| ; CHECK-NEXT: cadd z3.s, z3.s, z1.s, #90 |
| ; CHECK-NEXT: cadd z2.s, z2.s, z0.s, #90 |
| ; CHECK-NEXT: mov z0.d, z2.d |
| ; CHECK-NEXT: mov z1.d, z3.d |
| ; CHECK-NEXT: ret |
| entry: |
| %a.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %a) |
| %a.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 0 |
| %a.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 1 |
| %b.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %b) |
| %b.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 0 |
| %b.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 1 |
| %0 = sub <vscale x 4 x i32> %b.real, %a.imag |
| %1 = add <vscale x 4 x i32> %b.imag, %a.real |
| %interleaved.vec = tail call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1) |
| ret <vscale x 8 x i32> %interleaved.vec |
| } |
| |
| ; Expected to transform |
| define <vscale x 16 x i32> @complex_add_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) { |
| ; CHECK-LABEL: complex_add_v16i32: |
| ; CHECK: // %bb.0: // %entry |
| ; CHECK-NEXT: cadd z6.s, z6.s, z2.s, #90 |
| ; CHECK-NEXT: cadd z4.s, z4.s, z0.s, #90 |
| ; CHECK-NEXT: cadd z5.s, z5.s, z1.s, #90 |
| ; CHECK-NEXT: cadd z7.s, z7.s, z3.s, #90 |
| ; CHECK-NEXT: mov z0.d, z4.d |
| ; CHECK-NEXT: mov z1.d, z5.d |
| ; CHECK-NEXT: mov z2.d, z6.d |
| ; CHECK-NEXT: mov z3.d, z7.d |
| ; CHECK-NEXT: ret |
| entry: |
| %a.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %a) |
| %a.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 0 |
| %a.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 1 |
| %b.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %b) |
| %b.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 0 |
| %b.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 1 |
| %0 = sub <vscale x 8 x i32> %b.real, %a.imag |
| %1 = add <vscale x 8 x i32> %b.imag, %a.real |
| %interleaved.vec = tail call <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1) |
| ret <vscale x 16 x i32> %interleaved.vec |
| } |
| |
| declare { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32>) |
| declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>) |
| |
| declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>) |
| declare <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>) |
| |
| declare { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32>) |
| declare <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32>, <vscale x 8 x i32>) |