llvm/test/Transforms/NewGVN/pr33196.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S -passes=newgvn %s | FileCheck %s


@d = global i32 1, align 4
@c = common global i32 0, align 4
@a = common global i32 0, align 4
@b = common global i32 0, align 4

define i32 @main() {
; CHECK-LABEL: define i32 @main() {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP:%.*]] = load i32, ptr @d, align 4
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @c, align 4
; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[TMP1]], -1
; CHECK-NEXT:    br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
; CHECK:       if.then:
; CHECK-NEXT:    br label [[L:%.*]]
; CHECK:       L:
; CHECK-NEXT:    [[E_0:%.*]] = phi i32 [ 0, [[IF_THEN]] ], [ [[E_1:%.*]], [[IF_THEN4:%.*]] ]
; CHECK-NEXT:    br label [[IF_END]]
; CHECK:       if.end:
; CHECK-NEXT:    [[E_1]] = phi i32 [ [[E_0]], [[L]] ], [ [[TMP]], [[ENTRY:%.*]] ]
; CHECK-NEXT:    store i32 [[E_1]], ptr @a, align 4
; CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr @b, align 4
; CHECK-NEXT:    store i32 0, ptr @b, align 4
; CHECK-NEXT:    [[SEXT:%.*]] = shl i32 [[TMP2]], 16
; CHECK-NEXT:    [[CONV1:%.*]] = ashr exact i32 [[SEXT]], 16
; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], [[TMP1]]
; CHECK-NEXT:    [[ADD2:%.*]] = add nsw i32 [[ADD]], [[E_1]]
; CHECK-NEXT:    store i32 [[ADD2]], ptr @a, align 4
; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[ADD2]], 0
; CHECK-NEXT:    br i1 [[TOBOOL3]], label [[IF_END5:%.*]], label [[IF_THEN4]]
; CHECK:       if.then4:
; CHECK-NEXT:    br label [[L]]
; CHECK:       if.end5:
; CHECK-NEXT:    ret i32 0
;
entry:
  %tmp = load i32, ptr @d, align 4
  %tmp1 = load i32, ptr @c, align 4
  %tobool = icmp eq i32 %tmp1, -1
  br i1 %tobool, label %if.end, label %if.then

if.then:                                          ; preds = %entry
  br label %L

L:                                                ; preds = %if.then4, %if.then
  %e.0 = phi i32 [ 0, %if.then ], [ %e.1, %if.then4 ]
  br label %if.end

if.end:                                           ; preds = %L, %entry
  %e.1 = phi i32 [ %e.0, %L ], [ %tmp, %entry ]
  store i32 %e.1, ptr @a, align 4
  %tmp2 = load i32, ptr @b, align 4
  store i32 0, ptr @b, align 4
  %sext = shl i32 %tmp2, 16
  %conv1 = ashr exact i32 %sext, 16
  %tmp3 = load i32, ptr @c, align 4
  %add = add nsw i32 %conv1, %tmp3
  %tmp4 = load i32, ptr @a, align 4
  %and = and i32 %tmp4, %e.1
  %add2 = add nsw i32 %add, %and
  store i32 %add2, ptr @a, align 4
  %tobool3 = icmp eq i32 %add2, 0
  br i1 %tobool3, label %if.end5, label %if.then4

if.then4:                                         ; preds = %if.end
  br label %L

if.end5:                                          ; preds = %if.end
  ret i32 0
}