| // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s |
| // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s |
| // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR,W32-ERR --implicit-check-not=error: %s |
| // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR,W64-ERR --implicit-check-not=error: %s |
| |
| v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_add3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_add3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x55,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[3,2,1,0] |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[0,1,2,3] |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_mirror |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, s2 row_mirror |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x00,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_half_mirror |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shl:1 |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shl:15 |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shr:1 |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_shr:15 |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s6, v1, v2 row_ror:1 |
| // W32: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s105, v1, v2 row_ror:15 |
| // W32: [0x05,0x69,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // W32: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W32: [0x05,0x6b,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W32: [0x05,0x7b,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0] |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3] |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, s2 row_half_mirror |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x00,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1 |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15 |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1 |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15 |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1 |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15 |
| // W64: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // W64: [0x05,0x68,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W64: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W64: [0x05,0x7a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_add_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0xfc,0x00,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_add_lshl_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_add_lshl_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x47,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_add_nc_i16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_add_nc_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_add_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_add_nc_u16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_alignbit_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_alignbit_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_alignbyte_b32_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_alignbyte_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x17,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_and_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_and_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_and_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_and_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_and_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x57,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_ashrrev_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_ashrrev_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x3a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_bcnt_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_bcnt_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_bfe_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_bfe_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x11,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_bfe_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_bfe_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x10,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_bfi_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_bfi_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x12,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_bfm_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_bfm_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 quad_perm:[3,2,1,0] |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 quad_perm:[0,1,2,3] |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_mirror |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, s2, s3 row_mirror |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0c,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, 10, s3 row_mirror |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x14,0x0d,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_half_mirror |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shl:1 |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shl:15 |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shr:1 |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_shr:15 |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s3 row_ror:1 |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s105 row_ror:15 |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, vcc_hi row_share:0 row_mask:0xf bank_mask:0xf |
| // W32: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, |v1|, -v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W32: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, -v1, |v2|, ttmp15 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W32: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xee,0x21,0x01,0x60,0x09,0x13] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] quad_perm:[3,2,1,0] |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] quad_perm:[0,1,2,3] |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_mirror |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_half_mirror |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, s2, s[6:7] row_half_mirror |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x18,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, 10, s[6:7] row_half_mirror |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x14,0x19,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shl:1 |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shl:15 |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shr:1 |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_shr:15 |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_ror:1 |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[6:7] row_ror:15 |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, v1, v2, s[104:105] row_share:0 row_mask:0xf bank_mask:0xf |
| // W64: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, |v1|, -v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W64: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v5, -v1, |v2|, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W64: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xea,0x21,0x01,0x60,0x09,0x13] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_cndmask_b16_e64_dpp v255, -|v255|, -|v255|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x5d,0xd6,0xfa,0xfe,0xf3,0x61,0xff,0x6f,0x05,0x30] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x0c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x0c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x0c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x0c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_cubeid_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x0c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_cubeid_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x0c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_cubeid_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x0c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x0f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x0f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x0f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x0f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_cubema_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x0f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_cubema_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x0f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_cubema_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x0f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x0d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x0d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x0d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x0d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_cubesc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x0d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_cubesc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x0d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_cubesc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x0d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x0e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x0e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x0e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x0e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_cubetc_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x0e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_cubetc_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x0e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_cubetc_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x0e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x06,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] |
| |
| v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 |
| // GFX12: encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x06,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] |
| |
| v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 |
| // GFX12: encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x06,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] |
| |
| v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 |
| // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] |
| |
| v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x06,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] |
| |
| v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 |
| // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] |
| |
| v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] |
| // GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x06,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x06,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x06,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_i16_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_i16_i32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x24,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x07,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x07,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x07,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_u16_u32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_u16_u32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x23,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x54,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x54,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x48,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x48,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x13,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x13,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x13,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x13,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_fma_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x13,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_fma_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x13,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_fma_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x13,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01] |
| |
| v_ldexp_f32_e64_dpp v5, v1, v2 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x10,0x01,0x60,0x09,0x13] |
| |
| v_ldexp_f32_e64_dpp v255, -|v255|, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x81,0x1c,0xd7,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x05,0x30] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_lerp_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_lerp_u8_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x15,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_lshl_add_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_lshl_add_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x46,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_lshl_or_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_lshl_or_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x56,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_lshlrev_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_lshlrev_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x38,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_lshrrev_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_lshrrev_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x39,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_mad_i16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_mad_i32_i24_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_mad_i32_i24_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x0a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_mad_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_mad_u32_u24_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_mad_u32_u24_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x0b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x2c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x2c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x2c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x2c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x2c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x2c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x2c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x2c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x2a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x2a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x2a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x2a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x2a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_max3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x2a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_max3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x2a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_max3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x2a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_max3_i16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_max3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_max3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_max3_u16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_max3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_max3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_max_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_max_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_max_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x0a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_max_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_max_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_max_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x09,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x6b,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x6b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x6b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x6b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_maxmin_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x6b,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_maxmin_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x6b,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_maxmin_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x6b,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x69,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x69,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x69,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x69,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x69,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_maxmin_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x69,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_maxmin_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x69,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_maxmin_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x69,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_maxmin_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_maxmin_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x64,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_maxmin_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_maxmin_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x62,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_mbcnt_hi_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x20,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_mbcnt_lo_u32_b32_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1f,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x32,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x32,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x32,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x32,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x32,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x32,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x32,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x32,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x31,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x31,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x31,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x31,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x31,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_med3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x31,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_med3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x31,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_med3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x31,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_med3_i16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_med3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_med3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x20,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_med3_u16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_med3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_med3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x21,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x2b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x2b,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x2b,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x2b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x2b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x2b,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x2b,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x2b,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x29,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x29,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x29,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x29,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x29,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_min3_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x29,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_min3_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x29,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_min3_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x29,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_min3_i16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_min3_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_min3_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, v3 row_half_mirror |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, v255 row_shl:1 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, s105 row_shl:15 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, vcc_hi row_shr:1 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:15 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, ttmp15 row_ror:1 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, exec_hi row_ror:15 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, exec_lo row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, null row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, -1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13] |
| |
| v_min3_u16_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_min3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_min3_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x1b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_min_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_min_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_min_i16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x0c,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_min_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_min_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_min_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x0b,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x6a,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x6a,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x6a,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x6a,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_minmax_num_f16_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x6a,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_minmax_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x6a,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_minmax_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x6a,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x68,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x68,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x68,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x68,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x68,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_minmax_num_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x68,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_minmax_num_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x68,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_minmax_num_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x68,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_minmax_i32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_minmax_i32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x65,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_minmax_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_minmax_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x63,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_msad_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_msad_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x39,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_mul_lo_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_mul_lo_u16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x05,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x18,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x18,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x18,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x18,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_mullit_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x18,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_mullit_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x18,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_mullit_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x18,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_or3_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_or3_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x58,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_or_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_or_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_or_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_pack_b32_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x11,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_pack_b32_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_perm_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_perm_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x44,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_sad_hi_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_sad_hi_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x23,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_sad_u16_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_sad_u16_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x24,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_sad_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_sad_u32_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x25,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_sad_u8_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_sad_u8_e64_dpp v255, v255, v255, src_scc clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x22,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[3,2,1,0] |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[0,1,2,3] |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_mirror |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, s2 row_mirror |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x00,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_half_mirror |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shl:1 |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shl:15 |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shr:1 |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_shr:15 |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s6, v1, v2 row_ror:1 |
| // W32: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s105, v1, v2 row_ror:15 |
| // W32: [0x05,0x69,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // W32: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W32: [0x05,0x6b,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W32: [0x05,0x7b,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0] |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3] |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, s2 row_half_mirror |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x00,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1 |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15 |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1 |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15 |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1 |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15 |
| // W64: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // W64: [0x05,0x68,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W64: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W64: [0x05,0x7a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_sub_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0xfc,0x01,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_sub_nc_i16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_sub_nc_i32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_sub_nc_i32_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x25,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_sub_nc_u16_e64_dpp v255, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x80,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[3,2,1,0] |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 quad_perm:[0,1,2,3] |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_mirror |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, s2 row_mirror |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x00,0x00,0x01,0x40,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_half_mirror |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shl:1 |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shl:15 |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shr:1 |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_shr:15 |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s6, v1, v2 row_ror:1 |
| // W32: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s105, v1, v2 row_ror:15 |
| // W32: [0x05,0x69,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, vcc_lo, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // W32: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, vcc_hi, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W32: [0x05,0x6b,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, ttmp15, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W32: [0x05,0x7b,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[3,2,1,0] |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 quad_perm:[0,1,2,3] |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_mirror |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_half_mirror |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, s2 row_half_mirror |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x00,0x00,0x01,0x41,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:1 |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shl:15 |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:1 |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_shr:15 |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:1 |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[12:13], v1, v2 row_ror:15 |
| // W64: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, s[104:105], v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // W64: [0x05,0x68,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, vcc, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // W64: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v5, ttmp[14:15], v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // W64: [0x05,0x7a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_subrev_co_u32_e64_dpp v255, null, v255, v255 clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0xfc,0x02,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_xad_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_xad_u32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x45,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, 10, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x14,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, ttmp15 row_shr:15 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, exec_hi row_ror:1 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, exec_lo row_ror:15 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, -1 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01] |
| |
| v_xor3_b32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13] |
| |
| v_xor3_b32_e64_dpp v255, v255, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x40,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_xor_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13] |
| |
| v_xor_b16_e64_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x00,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x58,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x08,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_add_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x10,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] |
| |
| v_add_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc0,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x58,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x08,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_add_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x10,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] |
| |
| v_add_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc0,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x0a,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] |
| |
| v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x13,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x0a,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] |
| |
| v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x13,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] |
| |
| v_div_fixup_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x7c,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x0b,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_div_fixup_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x15,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_div_fixup_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x26,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13] |
| |
| v_div_fixup_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc7,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] |
| |
| v_fma_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x7c,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x0b,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_fma_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x15,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_fma_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x26,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13] |
| |
| v_fma_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc7,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_mad_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_mad_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc0,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_mad_i32_i16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x08,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13] |
| |
| v_mad_i32_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x90,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_mad_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_mad_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc0,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_mad_u32_u16_e64_dpp v5, v1, v2, 0.5 op_sel:[1,0,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x08,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13] |
| |
| v_mad_u32_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,1,0,0] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x90,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_max3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x7c,0x2c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x0b,0x2c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_max3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x15,0x2c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_max3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x26,0x2c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13] |
| |
| v_max3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc7,0x2c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_max3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_max3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x40,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_max3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_max3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x40,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_med3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x7c,0x32,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x0b,0x32,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_med3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x15,0x32,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_med3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x26,0x32,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13] |
| |
| v_med3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc7,0x32,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_med3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_med3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x40,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_med3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_med3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x40,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_min3_num_f16_e64_dpp v5, -v1, v2, |exec_lo| op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x7c,0x2b,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, -|v1|, -|v2|, null op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x0b,0x2b,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_min3_num_f16_e64_dpp v5, -|v1|, v2, -|-1| op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x15,0x2b,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_min3_num_f16_e64_dpp v5, v1, -|v2|, -|0.5| op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x26,0x2b,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13] |
| |
| v_min3_num_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| op_sel:[0,0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc7,0x2b,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_min3_i16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_min3_i16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x40,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, exec_hi op_sel:[1,1,1,1] row_ror:15 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x78,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, exec_lo op_sel:[1,0,0,0] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x08,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, null op_sel:[0,1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x10,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01] |
| |
| v_min3_u16_e64_dpp v5, v1, v2, -1 op_sel:[0,0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x20,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13] |
| |
| v_min3_u16_e64_dpp v255, v255, v255, src_scc op_sel:[0,0,0,1] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x40,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30] |
| |
| v_pack_b32_f16_e64_dpp v5, -v1, |v2| op_sel:[1,0,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x0a,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13] |
| |
| v_pack_b32_f16_e64_dpp v255, -|v255|, -|v255| op_sel:[0,1,0] row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0x13,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x58,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x08,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_sub_nc_i16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x10,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] |
| |
| v_sub_nc_i16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc0,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x58,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[1,0,0] row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x08,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01] |
| |
| v_sub_nc_u16_e64_dpp v5, v1, v2 op_sel:[0,1,0] row_xmask:0 row_mask:0x1 bank_mask:0x3 |
| // GFX12: [0x05,0x10,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13] |
| |
| v_sub_nc_u16_e64_dpp v255, v255, v255 op_sel:[0,0,1] clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 |
| // GFX12: [0xff,0xc0,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30] |
| |
| v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x00,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[1,1,0,0] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand |
| |
| v_dot2_f16_f16_e64_dpp v0, s1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_dot2_f16_f16_e64_dpp v0, v1, s2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x00,0x66,0xd6,0xfa,0x04,0x0c,0x04,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_f16_f16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x60,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_f16_f16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x65,0x66,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_f16_f16_e64_dpp v5, v1, v2, 0.5 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x66,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x1b,0x00,0xff] |
| |
| v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x00,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[1,1,0,0] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand |
| |
| v_dot2_bf16_bf16_e64_dpp v0, s1, v2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 |
| // GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction |
| |
| v_dot2_bf16_bf16_e64_dpp v0, v1, s2, v3 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 |
| // GFX12: [0x00,0x00,0x67,0xd6,0xfa,0x04,0x0c,0x04,0x01,0xe4,0x00,0x00] |
| |
| v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x60,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 |
| // GFX12: [0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00] |
| |
| v_dot2_bf16_bf16_e64_dpp v5, v1, v2, 0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x67,0xd6,0xfa,0x04,0x02,0x02,0x01,0x1b,0x00,0xff] |
| |
| v_minimum_f32 v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_minimum_f32 v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_minimum_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_minimum_f32 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x65,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_minimum_f32 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x65,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_minimum_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x65,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_maximum_f32 v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_maximum_f32 v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_maximum_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_maximum_f32 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x66,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_maximum_f32 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x66,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_maximum_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x66,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_minimum_f16 v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_minimum_f16 v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_minimum_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_minimum_f16 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x67,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_minimum_f16 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x67,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_minimum_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x67,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_maximum_f16 v5, v1, v2 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] |
| |
| v_maximum_f16 v5, v1, v2 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_mirror |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_half_mirror |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_shl:1 |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_shl:15 |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_shr:1 |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_shr:15 |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_ror:1 |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_ror:15 |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] |
| |
| v_maximum_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] |
| |
| v_maximum_f16 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x01,0x68,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] |
| |
| v_maximum_f16 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x02,0x68,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] |
| |
| v_maximum_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x03,0x68,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] |
| |
| v_minimum3_f32 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimum3_f32 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimum3_f32 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimum3_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minimum3_f32 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minimum3_f32 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minimum3_f32 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minimum3_f32 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minimum3_f32 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minimum3_f32 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x2d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_minimum3_f32 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x2d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_minimum3_f32 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x2d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_minimum3_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x2d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_minimum3_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x2d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_minimum3_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x2d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_minimum3_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x2d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_maximum3_f32 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximum3_f32 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximum3_f32 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximum3_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maximum3_f32 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maximum3_f32 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maximum3_f32 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maximum3_f32 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maximum3_f32 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maximum3_f32 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x2e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_maximum3_f32 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x2e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_maximum3_f32 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x2e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_maximum3_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x2e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_maximum3_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x2e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_maximum3_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x2e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_maximum3_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x2e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_minimum3_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimum3_f16 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimum3_f16 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimum3_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minimum3_f16 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minimum3_f16 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minimum3_f16 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minimum3_f16 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minimum3_f16 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minimum3_f16 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x2f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_minimum3_f16 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x2f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_minimum3_f16 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x2f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_minimum3_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x2f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_minimum3_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x2f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_minimum3_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x2f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_minimum3_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x2f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_maximum3_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximum3_f16 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximum3_f16 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximum3_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maximum3_f16 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maximum3_f16 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maximum3_f16 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maximum3_f16 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maximum3_f16 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maximum3_f16 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x30,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_maximum3_f16 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x30,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_maximum3_f16 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x30,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_maximum3_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x30,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_maximum3_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x30,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_maximum3_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x30,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_maximum3_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x30,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_maximumminimum_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maximumminimum_f32 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x6d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x6d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x6d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x6d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_maximumminimum_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x6d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_maximumminimum_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x6d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_maximumminimum_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x6d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_minimummaximum_f32 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimummaximum_f32 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimummaximum_f32 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimummaximum_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minimummaximum_f32 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x6c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x6c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x6c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x6c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_minimummaximum_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x6c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] |
| |
| v_minimummaximum_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x6c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] |
| |
| v_minimummaximum_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x6c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] |
| |
| v_maximumminimum_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximumminimum_f16 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximumminimum_f16 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_maximumminimum_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_maximumminimum_f16 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x6f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x6f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x6f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x6f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_maximumminimum_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x6f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_maximumminimum_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x6f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_maximumminimum_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x6f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
| |
| v_minimummaximum_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimummaximum_f16 v5, v1, s2, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimummaximum_f16 v5, v1, 2.0, v3 quad_perm:[3,2,1,0] |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0xe8,0x0d,0x04,0x01,0x1b,0x00,0xff] |
| |
| v_minimummaximum_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] |
| |
| v_minimummaximum_f16 v5, v1, v2, v3 row_mirror |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, v1, v2, v255 row_half_mirror |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, v1, v2, s105 row_shl:1 |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, v1, v2, vcc_hi row_shl:15 |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, v1, v2, vcc_lo row_shr:1 |
| // GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, |v1|, v2, -ttmp15 row_shr:15 |
| // GFX12: [0x05,0x01,0x6e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, v1, -|v2|, exec_hi row_ror:1 |
| // GFX12: [0x05,0x02,0x6e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, -v1, v2, |exec_lo| row_ror:15 |
| // GFX12: [0x05,0x04,0x6e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf |
| // GFX12: [0x05,0x03,0x6e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] |
| |
| v_minimummaximum_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 |
| // GFX12: [0x05,0x05,0x6e,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] |
| |
| v_minimummaximum_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 |
| // GFX12: [0x05,0x06,0x6e,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] |
| |
| v_minimummaximum_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 |
| // GFX12: [0xff,0x87,0x6e,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] |
