llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck -check-prefix=RV64I %s

---
name:            zext_nxv1i16_nxv1i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv1i16_nxv1i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ZEXT [[COPY]](<vscale x 1 x s8>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s16>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv1i16_nxv1i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ZEXT [[COPY]](<vscale x 1 x s8>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s16>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 1 x s8>) = COPY $v8
    %1:_(<vscale x 1 x s16>) = G_ZEXT %0(<vscale x 1 x s8>)
    $v8 = COPY %1(<vscale x 1 x s16>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv1i32_nxv1i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv1i32_nxv1i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s8>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv1i32_nxv1i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s8>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 1 x s8>) = COPY $v8
    %1:_(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s8>)
    $v8 = COPY %1(<vscale x 1 x s32>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv1i64_nxv1i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv1i64_nxv1i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s8>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv1i64_nxv1i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s8>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 1 x s8>) = COPY $v8
    %1:_(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s8>)
    $v8 = COPY %1(<vscale x 1 x s64>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv2i16_nxv2i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv2i16_nxv2i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ZEXT [[COPY]](<vscale x 2 x s8>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s16>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv2i16_nxv2i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ZEXT [[COPY]](<vscale x 2 x s8>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s16>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 2 x s8>) = COPY $v8
    %1:_(<vscale x 2 x s16>) = G_ZEXT %0(<vscale x 2 x s8>)
    $v8 = COPY %1(<vscale x 2 x s16>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv2i32_nxv2i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv2i32_nxv2i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s8>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv2i32_nxv2i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s8>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 2 x s8>) = COPY $v8
    %1:_(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s8>)
    $v8 = COPY %1(<vscale x 2 x s32>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv2i64_nxv2i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv2i64_nxv2i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s8>)
    ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m2
    ;
    ; RV64I-LABEL: name: zext_nxv2i64_nxv2i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s8>)
    ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m2
    %0:_(<vscale x 2 x s8>) = COPY $v8
    %1:_(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s8>)
    $v8m2 = COPY %1(<vscale x 2 x s64>)
    PseudoRET implicit $v8m2

...
---
name:            zext_nxv4i16_nxv4i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv4i16_nxv4i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ZEXT [[COPY]](<vscale x 4 x s8>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 4 x s16>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv4i16_nxv4i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ZEXT [[COPY]](<vscale x 4 x s8>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 4 x s16>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 4 x s8>) = COPY $v8
    %1:_(<vscale x 4 x s16>) = G_ZEXT %0(<vscale x 4 x s8>)
    $v8 = COPY %1(<vscale x 4 x s16>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv4i32_nxv4i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv4i32_nxv4i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s8>)
    ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8m2
    ;
    ; RV64I-LABEL: name: zext_nxv4i32_nxv4i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s8>)
    ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8m2
    %0:_(<vscale x 4 x s8>) = COPY $v8
    %1:_(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s8>)
    $v8m2 = COPY %1(<vscale x 4 x s32>)
    PseudoRET implicit $v8m2

...
---
name:            zext_nxv4i64_nxv4i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv4i64_nxv4i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s8>)
    ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m4
    ;
    ; RV64I-LABEL: name: zext_nxv4i64_nxv4i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s8>)
    ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m4
    %0:_(<vscale x 4 x s8>) = COPY $v8
    %1:_(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s8>)
    $v8m4 = COPY %1(<vscale x 4 x s64>)
    PseudoRET implicit $v8m4

...
---
name:            zext_nxv8i16_nxv8i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv8i16_nxv8i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ZEXT [[COPY]](<vscale x 8 x s8>)
    ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 8 x s16>)
    ; RV32I-NEXT: PseudoRET implicit $v8m2
    ;
    ; RV64I-LABEL: name: zext_nxv8i16_nxv8i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ZEXT [[COPY]](<vscale x 8 x s8>)
    ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 8 x s16>)
    ; RV64I-NEXT: PseudoRET implicit $v8m2
    %0:_(<vscale x 8 x s8>) = COPY $v8
    %1:_(<vscale x 8 x s16>) = G_ZEXT %0(<vscale x 8 x s8>)
    $v8m2 = COPY %1(<vscale x 8 x s16>)
    PseudoRET implicit $v8m2

...
---
name:            zext_nxv8i32_nxv8i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv8i32_nxv8i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s8>)
    ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8m4
    ;
    ; RV64I-LABEL: name: zext_nxv8i32_nxv8i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s8>)
    ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8m4
    %0:_(<vscale x 8 x s8>) = COPY $v8
    %1:_(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s8>)
    $v8m4 = COPY %1(<vscale x 8 x s32>)
    PseudoRET implicit $v8m4

...
---
name:            zext_nxv8i64_nxv8i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv8i64_nxv8i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s8>)
    ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m8
    ;
    ; RV64I-LABEL: name: zext_nxv8i64_nxv8i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s8>)
    ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m8
    %0:_(<vscale x 8 x s8>) = COPY $v8
    %1:_(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s8>)
    $v8m8 = COPY %1(<vscale x 8 x s64>)
    PseudoRET implicit $v8m8

...
---
name:            zext_nxv16i16_nxv16i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv16i16_nxv16i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ZEXT [[COPY]](<vscale x 16 x s8>)
    ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 16 x s16>)
    ; RV32I-NEXT: PseudoRET implicit $v8m4
    ;
    ; RV64I-LABEL: name: zext_nxv16i16_nxv16i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ZEXT [[COPY]](<vscale x 16 x s8>)
    ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 16 x s16>)
    ; RV64I-NEXT: PseudoRET implicit $v8m4
    %0:_(<vscale x 16 x s8>) = COPY $v8m2
    %1:_(<vscale x 16 x s16>) = G_ZEXT %0(<vscale x 16 x s8>)
    $v8m4 = COPY %1(<vscale x 16 x s16>)
    PseudoRET implicit $v8m4

...
---
name:            zext_nxv16i32_nxv16i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv16i32_nxv16i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s8>)
    ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8m8
    ;
    ; RV64I-LABEL: name: zext_nxv16i32_nxv16i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s8>)
    ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8m8
    %0:_(<vscale x 16 x s8>) = COPY $v8m2
    %1:_(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s8>)
    $v8m8 = COPY %1(<vscale x 16 x s32>)
    PseudoRET implicit $v8m8

...
---
name:            zext_nxv32i16_nxv32i8
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv32i16_nxv32i8
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ZEXT [[COPY]](<vscale x 32 x s8>)
    ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 32 x s16>)
    ; RV32I-NEXT: PseudoRET implicit $v8m8
    ;
    ; RV64I-LABEL: name: zext_nxv32i16_nxv32i8
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ZEXT [[COPY]](<vscale x 32 x s8>)
    ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 32 x s16>)
    ; RV64I-NEXT: PseudoRET implicit $v8m8
    %0:_(<vscale x 32 x s8>) = COPY $v8m4
    %1:_(<vscale x 32 x s16>) = G_ZEXT %0(<vscale x 32 x s8>)
    $v8m8 = COPY %1(<vscale x 32 x s16>)
    PseudoRET implicit $v8m8

...
---
name:            zext_nxv1i32_nxv1i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv1i32_nxv1i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s16>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv1i32_nxv1i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s16>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 1 x s16>) = COPY $v8
    %1:_(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s16>)
    $v8 = COPY %1(<vscale x 1 x s32>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv1i64_nxv1i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv1i64_nxv1i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s16>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv1i64_nxv1i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s16>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 1 x s16>) = COPY $v8
    %1:_(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s16>)
    $v8 = COPY %1(<vscale x 1 x s64>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv2i32_nxv2i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv2i32_nxv2i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s16>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv2i32_nxv2i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s16>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 2 x s16>) = COPY $v8
    %1:_(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s16>)
    $v8 = COPY %1(<vscale x 2 x s32>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv2i64_nxv2i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv2i64_nxv2i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s16>)
    ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m2
    ;
    ; RV64I-LABEL: name: zext_nxv2i64_nxv2i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s16>)
    ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m2
    %0:_(<vscale x 2 x s16>) = COPY $v8
    %1:_(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s16>)
    $v8m2 = COPY %1(<vscale x 2 x s64>)
    PseudoRET implicit $v8m2

...
---
name:            zext_nxv4i32_nxv4i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv4i32_nxv4i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s16>)
    ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8m2
    ;
    ; RV64I-LABEL: name: zext_nxv4i32_nxv4i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s16>)
    ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8m2
    %0:_(<vscale x 4 x s16>) = COPY $v8
    %1:_(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s16>)
    $v8m2 = COPY %1(<vscale x 4 x s32>)
    PseudoRET implicit $v8m2

...
---
name:            zext_nxv4i64_nxv4i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv4i64_nxv4i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s16>)
    ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m4
    ;
    ; RV64I-LABEL: name: zext_nxv4i64_nxv4i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s16>)
    ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m4
    %0:_(<vscale x 4 x s16>) = COPY $v8
    %1:_(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s16>)
    $v8m4 = COPY %1(<vscale x 4 x s64>)
    PseudoRET implicit $v8m4

...
---
name:            zext_nxv8i32_nxv8i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv8i32_nxv8i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s16>)
    ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8m4
    ;
    ; RV64I-LABEL: name: zext_nxv8i32_nxv8i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s16>)
    ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8m4
    %0:_(<vscale x 8 x s16>) = COPY $v8m2
    %1:_(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s16>)
    $v8m4 = COPY %1(<vscale x 8 x s32>)
    PseudoRET implicit $v8m4

...
---
name:            zext_nxv8i64_nxv8i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv8i64_nxv8i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m4
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s16>)
    ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m8
    ;
    ; RV64I-LABEL: name: zext_nxv8i64_nxv8i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m4
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s16>)
    ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m8
    %0:_(<vscale x 8 x s16>) = COPY $v8m4
    %1:_(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s16>)
    $v8m8 = COPY %1(<vscale x 8 x s64>)
    PseudoRET implicit $v8m8

...
---
name:            zext_nxv16i32_nxv16i16
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv16i32_nxv16i16
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s16>)
    ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>)
    ; RV32I-NEXT: PseudoRET implicit $v8m8
    ;
    ; RV64I-LABEL: name: zext_nxv16i32_nxv16i16
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s16>)
    ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>)
    ; RV64I-NEXT: PseudoRET implicit $v8m8
    %0:_(<vscale x 16 x s16>) = COPY $v8m4
    %1:_(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s16>)
    $v8m8 = COPY %1(<vscale x 16 x s32>)
    PseudoRET implicit $v8m8

...
---
name:            zext_nxv1i64_nxv1i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv1i64_nxv1i32
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s32>)
    ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8
    ;
    ; RV64I-LABEL: name: zext_nxv1i64_nxv1i32
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s32>)
    ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8
    %0:_(<vscale x 1 x s32>) = COPY $v8
    %1:_(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s32>)
    $v8 = COPY %1(<vscale x 1 x s64>)
    PseudoRET implicit $v8

...
---
name:            zext_nxv2i64_nxv2i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv2i64_nxv2i32
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s32>)
    ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m2
    ;
    ; RV64I-LABEL: name: zext_nxv2i64_nxv2i32
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s32>)
    ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m2
    %0:_(<vscale x 2 x s32>) = COPY $v8
    %1:_(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s32>)
    $v8m2 = COPY %1(<vscale x 2 x s64>)
    PseudoRET implicit $v8m2

...
---
name:            zext_nxv4i64_nxv4i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv4i64_nxv4i32
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s32>)
    ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m4
    ;
    ; RV64I-LABEL: name: zext_nxv4i64_nxv4i32
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s32>)
    ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m4
    %0:_(<vscale x 4 x s32>) = COPY $v8m2
    %1:_(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s32>)
    $v8m4 = COPY %1(<vscale x 4 x s64>)
    PseudoRET implicit $v8m4

...
---
name:            zext_nxv8i64_nxv8i32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v8

    ; RV32I-LABEL: name: zext_nxv8i64_nxv8i32
    ; RV32I: liveins: $v8
    ; RV32I-NEXT: {{  $}}
    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4
    ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s32>)
    ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>)
    ; RV32I-NEXT: PseudoRET implicit $v8m8
    ;
    ; RV64I-LABEL: name: zext_nxv8i64_nxv8i32
    ; RV64I: liveins: $v8
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4
    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s32>)
    ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>)
    ; RV64I-NEXT: PseudoRET implicit $v8m8
    %0:_(<vscale x 8 x s32>) = COPY $v8m4
    %1:_(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s32>)
    $v8m8 = COPY %1(<vscale x 8 x s64>)
    PseudoRET implicit $v8m8

...