| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s |
| # RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s |
| |
| --- |
| name: icmp_nxv1i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv1i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 1 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv1i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 1 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 1 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv2i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv2i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 2 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv2i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 2 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 2 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv4i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv4i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 4 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv4i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 4 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 4 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv8i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv8i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 8 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv8i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 8 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 8 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv16i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv16i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 16 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv16i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 16 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 16 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv32i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv32i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 32 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv32i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 32 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 32 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv64i1 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv64i1 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32) |
| ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32) |
| ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C2]](s32) |
| ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C3]](s32) |
| ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 64 x s8>), [[SELECT1]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv64i1 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) |
| ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) |
| ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] |
| ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) |
| ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 |
| ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) |
| ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) |
| ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 64 x s8>), [[SELECT1]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 64 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv1i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv1i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv1i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 1 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv2i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv2i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv2i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 2 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv4i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv4i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv4i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 4 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv8i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv8i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv8i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 8 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv16i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv16i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv16i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 16 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv32i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv32i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv32i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 32 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv64i8 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv64i8 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s8>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv64i8 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s8>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 64 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv1i16 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv1i16 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s16>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv1i16 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s16>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 1 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv2i16 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv2i16 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s16>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv2i16 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s16>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 2 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv4i16 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv4i16 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s16>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv4i16 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s16>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 4 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv8i16 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv8i16 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s16>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv8i16 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s16>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 8 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv16i16 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv16i16 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s16>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv16i16 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s16>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 16 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv32i16 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv32i16 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s16>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv32i16 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s16>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 32 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv1i32 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv1i32 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s32>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv1i32 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s32>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 1 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv2i32 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv2i32 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s32>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv2i32 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s32>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 2 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv4i32 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv4i32 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s32>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv4i32 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s32>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 4 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv8i32 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv8i32 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s32>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv8i32 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s32>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 8 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv16i32 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv16i32 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s32>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv16i32 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s32>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 16 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv1i64 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv1i64 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s64>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv1i64 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s64>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 1 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv2i64 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv2i64 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s64>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv2i64 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s64>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 2 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv4i64 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv4i64 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s64>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv4i64 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s64>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 4 x s1>) |
| PseudoRET implicit $v8 |
| ... |
| --- |
| name: icmp_nxv8i64 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32-LABEL: name: icmp_nxv8i64 |
| ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF |
| ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s64>), [[DEF]] |
| ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV32-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64-LABEL: name: icmp_nxv8i64 |
| ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF |
| ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s64>), [[DEF]] |
| ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) |
| ; RV64-NEXT: PseudoRET implicit $v8 |
| %0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF |
| %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 |
| $v8 = COPY %1(<vscale x 8 x s1>) |
| PseudoRET implicit $v8 |
| ... |