| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s |
| # RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s |
| |
| --- |
| name: select_nxv1i8 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv1i8 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */ |
| ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64I-LABEL: name: select_nxv1i8 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */ |
| ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8 |
| %0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 2 x s8>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1 |
| $v8 = COPY %2(<vscale x 2 x s8>) |
| PseudoRET implicit $v8 |
| |
| ... |
| --- |
| name: select_nxv4i8 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv4i8 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */ |
| ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64I-LABEL: name: select_nxv4i8 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */ |
| ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8 |
| %0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 8 x s8>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1 |
| $v8 = COPY %2(<vscale x 8 x s8>) |
| PseudoRET implicit $v8 |
| |
| ... |
| --- |
| name: select_nxv16i8 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv16i8 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */ |
| ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8m4 |
| ; |
| ; RV64I-LABEL: name: select_nxv16i8 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */ |
| ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8m4 |
| %0:vrb(<vscale x 32 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 32 x s8>) = G_SELECT %0(<vscale x 32 x s1>), %1, %1 |
| $v8m4 = COPY %2(<vscale x 32 x s8>) |
| PseudoRET implicit $v8m4 |
| |
| ... |
| --- |
| name: select_nxv64i8 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv64i8 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */ |
| ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64I-LABEL: name: select_nxv64i8 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */ |
| ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8 |
| %0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 1 x s16>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1 |
| $v8 = COPY %2(<vscale x 1 x s16>) |
| PseudoRET implicit $v8 |
| |
| ... |
| --- |
| name: select_nxv2i16 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv2i16 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */ |
| ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64I-LABEL: name: select_nxv2i16 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */ |
| ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8 |
| %0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 4 x s16>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1 |
| $v8 = COPY %2(<vscale x 4 x s16>) |
| PseudoRET implicit $v8 |
| |
| ... |
| --- |
| name: select_nxv8i16 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv8i16 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */ |
| ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8m4 |
| ; |
| ; RV64I-LABEL: name: select_nxv8i16 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */ |
| ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8m4 |
| %0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 16 x s16>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1 |
| $v8m4 = COPY %2(<vscale x 16 x s16>) |
| PseudoRET implicit $v8m4 |
| |
| ... |
| --- |
| name: select_nxv32i16 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv32i16 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */ |
| ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8 |
| ; |
| ; RV64I-LABEL: name: select_nxv32i16 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */ |
| ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8 |
| %0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 1 x s32>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1 |
| $v8 = COPY %2(<vscale x 1 x s32>) |
| PseudoRET implicit $v8 |
| |
| ... |
| --- |
| name: select_nxv2i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv2i32 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */ |
| ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8m2 |
| ; |
| ; RV64I-LABEL: name: select_nxv2i32 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */ |
| ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8m2 |
| %0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 4 x s32>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1 |
| $v8m2 = COPY %2(<vscale x 4 x s32>) |
| PseudoRET implicit $v8m2 |
| |
| ... |
| --- |
| name: select_nxv8i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv8i32 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */ |
| ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8m8 |
| ; |
| ; RV64I-LABEL: name: select_nxv8i32 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */ |
| ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8m8 |
| %0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 16 x s32>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1 |
| $v8m8 = COPY %2(<vscale x 16 x s32>) |
| PseudoRET implicit $v8m8 |
| |
| ... |
| --- |
| name: select_nxv1i64 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv1i64 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */ |
| ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8m2 |
| ; |
| ; RV64I-LABEL: name: select_nxv1i64 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */ |
| ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8m2 |
| %0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 2 x s64>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1 |
| $v8m2 = COPY %2(<vscale x 2 x s64>) |
| PseudoRET implicit $v8m2 |
| |
| ... |
| --- |
| name: select_nxv4i64 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0.entry: |
| ; RV32I-LABEL: name: select_nxv4i64 |
| ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF |
| ; RV32I-NEXT: $v0 = COPY [[DEF]] |
| ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */ |
| ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] |
| ; RV32I-NEXT: PseudoRET implicit $v8m8 |
| ; |
| ; RV64I-LABEL: name: select_nxv4i64 |
| ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF |
| ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF |
| ; RV64I-NEXT: $v0 = COPY [[DEF]] |
| ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */ |
| ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] |
| ; RV64I-NEXT: PseudoRET implicit $v8m8 |
| %0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF |
| %1:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF |
| %2:vrb(<vscale x 8 x s64>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1 |
| $v8m8 = COPY %2(<vscale x 8 x s64>) |
| PseudoRET implicit $v8m8 |
| |
| ... |