llvm/test/CodeGen/AMDGPU/folding-of-i32-as-i64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s

# The constant is 0xffffffff80000000. It is 64-bit negative constant, but it passes the test
# isInt<32>(). Nonetheless it is not a legal literal for a binary or unsigned operand and
# cannot be used right in the shift as HW will zero extend it.

---
name:            imm64_shift_int32_const_0xffffffff80000000
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff80000000
    ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -2147483648
    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744071562067968
    %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_shift_int32_const_0xffffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffff
    ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
    %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_shift_int32_const_0x80000000
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_shift_int32_const_0x80000000
    ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483648
    %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_shift_int32_const_0x7fffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_shift_int32_const_0x7fffffff
    ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 2147483647, 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647
    %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_shift_int32_const_0x1ffffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_shift_int32_const_0x1ffffffff
    ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 8589934591
    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[S_MOV_B]], 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 8589934591
    %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_shift_int32_const_0xffffffffffffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_shift_int32_const_0xffffffffffffffff
    ; GCN: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 -1, 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
    %1:sreg_64 = S_LSHL_B64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_ashr_int32_const_0xffffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffff
    ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
    ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[S_MOV_B]], 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
    %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_ashr_int32_const_0x7fffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_ashr_int32_const_0x7fffffff
    ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 2147483647, 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 2147483647
    %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...

---
name:            imm64_ashr_int32_const_0xffffffffffffffff
body: |
  bb.0:
    ; GCN-LABEL: name: imm64_ashr_int32_const_0xffffffffffffffff
    ; GCN: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 -1, 1, implicit-def $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
    %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
    S_ENDPGM 0, implicit %1

...