| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfmin \ |
| ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s |
| ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfmin \ |
| ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s |
| |
| declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32( |
| <vscale x 1 x bfloat>, |
| <vscale x 1 x float>, |
| iXLen, iXLen); |
| |
| define <vscale x 1 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv1bf16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv1bf16_nxv1f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8 |
| ; CHECK-NEXT: vmv1r.v v8, v9 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32( |
| <vscale x 1 x bfloat> undef, |
| <vscale x 1 x float> %0, |
| iXLen 7, iXLen %1) |
| |
| ret <vscale x 1 x bfloat> %a |
| } |
| |
| declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32( |
| <vscale x 1 x bfloat>, |
| <vscale x 1 x float>, |
| <vscale x 1 x i1>, |
| iXLen, iXLen, iXLen); |
| |
| define <vscale x 1 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv1bf16_nxv1f32(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv1bf16_nxv1f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32( |
| <vscale x 1 x bfloat> %0, |
| <vscale x 1 x float> %1, |
| <vscale x 1 x i1> %2, |
| iXLen 7, iXLen %3, iXLen 1) |
| |
| ret <vscale x 1 x bfloat> %a |
| } |
| |
| declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32( |
| <vscale x 2 x bfloat>, |
| <vscale x 2 x float>, |
| iXLen, iXLen); |
| |
| define <vscale x 2 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv2bf16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv2bf16_nxv2f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8 |
| ; CHECK-NEXT: vmv1r.v v8, v9 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32( |
| <vscale x 2 x bfloat> undef, |
| <vscale x 2 x float> %0, |
| iXLen 7, iXLen %1) |
| |
| ret <vscale x 2 x bfloat> %a |
| } |
| |
| declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32( |
| <vscale x 2 x bfloat>, |
| <vscale x 2 x float>, |
| <vscale x 2 x i1>, |
| iXLen, iXLen, iXLen); |
| |
| define <vscale x 2 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv2bf16_nxv2f32(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv2bf16_nxv2f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32( |
| <vscale x 2 x bfloat> %0, |
| <vscale x 2 x float> %1, |
| <vscale x 2 x i1> %2, |
| iXLen 7, iXLen %3, iXLen 1) |
| |
| ret <vscale x 2 x bfloat> %a |
| } |
| |
| declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32( |
| <vscale x 4 x bfloat>, |
| <vscale x 4 x float>, |
| iXLen, iXLen); |
| |
| define <vscale x 4 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv4bf16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv4bf16_nxv4f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8 |
| ; CHECK-NEXT: vmv.v.v v8, v10 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32( |
| <vscale x 4 x bfloat> undef, |
| <vscale x 4 x float> %0, |
| iXLen 7, iXLen %1) |
| |
| ret <vscale x 4 x bfloat> %a |
| } |
| |
| declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32( |
| <vscale x 4 x bfloat>, |
| <vscale x 4 x float>, |
| <vscale x 4 x i1>, |
| iXLen, iXLen, iXLen); |
| |
| define <vscale x 4 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv4bf16_nxv4f32(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv4bf16_nxv4f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32( |
| <vscale x 4 x bfloat> %0, |
| <vscale x 4 x float> %1, |
| <vscale x 4 x i1> %2, |
| iXLen 7, iXLen %3, iXLen 1) |
| |
| ret <vscale x 4 x bfloat> %a |
| } |
| |
| declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32( |
| <vscale x 8 x bfloat>, |
| <vscale x 8 x float>, |
| iXLen, iXLen); |
| |
| define <vscale x 8 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv8bf16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv8bf16_nxv8f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8 |
| ; CHECK-NEXT: vmv.v.v v8, v12 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32( |
| <vscale x 8 x bfloat> undef, |
| <vscale x 8 x float> %0, |
| iXLen 7, iXLen %1) |
| |
| ret <vscale x 8 x bfloat> %a |
| } |
| |
| declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32( |
| <vscale x 8 x bfloat>, |
| <vscale x 8 x float>, |
| <vscale x 8 x i1>, |
| iXLen, iXLen, iXLen); |
| |
| define <vscale x 8 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv8bf16_nxv8f32(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv8bf16_nxv8f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32( |
| <vscale x 8 x bfloat> %0, |
| <vscale x 8 x float> %1, |
| <vscale x 8 x i1> %2, |
| iXLen 7, iXLen %3, iXLen 1) |
| |
| ret <vscale x 8 x bfloat> %a |
| } |
| |
| declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32( |
| <vscale x 16 x bfloat>, |
| <vscale x 16 x float>, |
| iXLen, iXLen); |
| |
| define <vscale x 16 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv16bf16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv16bf16_nxv16f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v16, v8 |
| ; CHECK-NEXT: vmv.v.v v8, v16 |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32( |
| <vscale x 16 x bfloat> undef, |
| <vscale x 16 x float> %0, |
| iXLen 7, iXLen %1) |
| |
| ret <vscale x 16 x bfloat> %a |
| } |
| |
| declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32( |
| <vscale x 16 x bfloat>, |
| <vscale x 16 x float>, |
| <vscale x 16 x i1>, |
| iXLen, iXLen, iXLen); |
| |
| define <vscale x 16 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv16bf16_nxv16f32(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { |
| ; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv16bf16_nxv16f32: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu |
| ; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t |
| ; CHECK-NEXT: ret |
| entry: |
| %a = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32( |
| <vscale x 16 x bfloat> %0, |
| <vscale x 16 x float> %1, |
| <vscale x 16 x i1> %2, |
| iXLen 7, iXLen %3, iXLen 1) |
| |
| ret <vscale x 16 x bfloat> %a |
| } |