llvm/test/CodeGen/AArch64/pr58350.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s

; This used to hit an assertion caused by dagcombine merge store.
; When the store memVT is v1f32 and the other store to be merged
; is f32, we need to build vector for the f32 store.

define void @f(<1 x float> %a, i64 %b) {
; CHECK-LABEL: f:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    adrp x8, .LCPI0_0
; CHECK-NEXT:    mov x9, sp
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT:    bfi x9, x0, #2, #1
; CHECK-NEXT:    str d1, [sp]
; CHECK-NEXT:    ldr s1, [x9]
; CHECK-NEXT:    mov v1.s[1], v0.s[0]
; CHECK-NEXT:    str d1, [sp, #8]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
  %P = alloca i64
  %E = extractelement <2 x float> <float 0.5, float 1.0>, i64 %b
  %G = getelementptr <1 x float>, ptr %P, i64 1
  store float %E, ptr %P
  store <1 x float> %a, ptr %G
  ret void
}