| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s |
| |
| --- |
| name: ballot_sgpr_src |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| ; CHECK-LABEL: name: ballot_sgpr_src |
| ; CHECK: liveins: $sgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[COPY1]](s1) |
| ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s64) |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s1) = G_TRUNC %0 |
| %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: ballot_vgpr_src |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: ballot_vgpr_src |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[COPY1]](s1) |
| ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s64) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s1) = G_TRUNC %0 |
| %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: ballot_vcc_src |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| ; CHECK-LABEL: name: ballot_vcc_src |
| ; CHECK: liveins: $vgpr0, $vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1) |
| ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s64) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s1) = G_ICMP intpred(eq), %0, %1 |
| %3:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ballot), %2 |
| S_ENDPGM 0, implicit %3 |
| ... |