| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX9 %s |
| # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9PLUS,GFX11 %s |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_s32_s_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32 |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_pack_lh |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %1, %2 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| # s_pack_hl_b32 was introduced in GFX11 |
| --- |
| name: test_build_vector_trunc_s_pack_hl |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hl |
| ; GFX9: liveins: $sgpr0, $sgpr1 |
| ; GFX9-NEXT: {{ $}} |
| ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]] |
| ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| ; |
| ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hl |
| ; GFX11: liveins: $sgpr0, $sgpr1 |
| ; GFX11-NEXT: {{ $}} |
| ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY1]], [[COPY]] |
| ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %1, %2 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_pack_hh |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %0, %2 |
| %4:sgpr(s32) = G_LSHR %1, %2 |
| %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 |
| S_ENDPGM 0, implicit %5 |
| ... |
| |
| # TODO: Should this use an and instead? |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32 |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_CONSTANT i32 0 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32 |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_CONSTANT i32 0 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32 |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_IMPLICIT_DEF |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32 |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_IMPLICIT_DEF |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_undef_s_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32 |
| ; GFX9PLUS: liveins: $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = G_IMPLICIT_DEF |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_s32_undef |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[COPY]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_IMPLICIT_DEF |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_zero_s_s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32 |
| ; GFX9PLUS: liveins: $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = G_CONSTANT i32 0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_s_s32_zero |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_CONSTANT i32 0 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_lshr16_zero |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_lshr16_zero |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def dead $scc |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]] |
| %0:sgpr(s32) = G_CONSTANT i32 0 |
| %1:sgpr(s32) = COPY $sgpr0 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %1, %2 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| # Don't use pack since it would duplicate the shift use |
| --- |
| name: test_build_vector_trunc_s_pack_lh_multi_use |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %1, %2 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 |
| S_ENDPGM 0, implicit %4, implicit %3 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_pack_hh_multi_use_lhs |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %0, %2 |
| %4:sgpr(s32) = G_LSHR %1, %2 |
| %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 |
| S_ENDPGM 0, implicit %5, implicit %3 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_pack_hh_multi_use_rhs |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs |
| ; GFX9: liveins: $sgpr0, $sgpr1 |
| ; GFX9-NEXT: {{ $}} |
| ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]] |
| ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]] |
| ; |
| ; GFX11-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs |
| ; GFX11: liveins: $sgpr0, $sgpr1 |
| ; GFX11-NEXT: {{ $}} |
| ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; GFX11-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX11-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY]], [[S_LSHR_B32_]] |
| ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_PACK_HL_B32_B16_]], implicit [[S_LSHR_B32_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 16 |
| %3:sgpr(s32) = G_LSHR %0, %2 |
| %4:sgpr(s32) = G_LSHR %1, %2 |
| %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 |
| S_ENDPGM 0, implicit %5, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15 |
| ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 15 |
| %3:sgpr(s32) = G_LSHR %1, %2 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt |
| ; GFX9PLUS: liveins: $sgpr0, $sgpr1 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15 |
| ; GFX9PLUS-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:sgpr(s32) = G_CONSTANT i32 15 |
| %3:sgpr(s32) = G_LSHR %0, %2 |
| %4:sgpr(s32) = G_LSHR %1, %2 |
| %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 |
| S_ENDPGM 0, implicit %5 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_constant_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant |
| ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] |
| %0:sgpr(s32) = G_CONSTANT i32 123 |
| %1:sgpr(s32) = G_CONSTANT i32 456 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_constant_impdef |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef |
| ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] |
| %0:sgpr(s32) = G_CONSTANT i32 123 |
| %1:sgpr(s32) = G_IMPLICIT_DEF |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_impdef_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant |
| ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = G_IMPLICIT_DEF |
| %1:sgpr(s32) = G_CONSTANT i32 123 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_impdef_impdef |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef |
| ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[DEF]] |
| %0:sgpr(s32) = G_IMPLICIT_DEF |
| %1:sgpr(s32) = G_IMPLICIT_DEF |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant |
| ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] |
| %0:sgpr(s16) = G_CONSTANT i16 123 |
| %1:sgpr(s16) = G_CONSTANT i16 456 |
| %2:sgpr(s32) = G_ZEXT %0 |
| %3:sgpr(s32) = G_ZEXT %1 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant |
| ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 |
| ; GFX9PLUS-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_1]], [[DEF]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 |
| ; GFX9PLUS-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_MOV_B32_]], implicit-def dead $scc |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_AND_B32_]], [[S_AND_B32_1]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s16) = G_IMPLICIT_DEF |
| %1:sgpr(s16) = G_CONSTANT i16 123 |
| %2:sgpr(s32) = G_ZEXT %0 |
| %3:sgpr(s32) = G_ZEXT %1 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant |
| ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] |
| %0:sgpr(s16) = G_CONSTANT i16 -16 |
| %1:sgpr(s16) = G_CONSTANT i16 -3 |
| %2:sgpr(s32) = G_SEXT %0 |
| %3:sgpr(s32) = G_SEXT %1 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant |
| ; GFX9PLUS: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]] |
| %0:sgpr(s16) = G_CONSTANT i16 123 |
| %1:sgpr(s16) = G_CONSTANT i16 456 |
| %2:sgpr(s32) = G_ANYEXT %0 |
| %3:sgpr(s32) = G_ANYEXT %1 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant |
| ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s16) = G_IMPLICIT_DEF |
| %1:sgpr(s16) = G_CONSTANT i16 123 |
| %2:sgpr(s32) = G_ANYEXT %0 |
| %3:sgpr(s32) = G_ANYEXT %1 |
| %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 |
| S_ENDPGM 0, implicit %4 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_var_constant |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_CONSTANT i32 456 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_constant_var |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456 |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = G_CONSTANT i32 456 |
| %1:sgpr(s32) = COPY $sgpr0 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_var_0 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_var_0 |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = G_CONSTANT i32 0 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |
| |
| --- |
| name: test_build_vector_trunc_s_v2s16_0_var |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0 |
| |
| ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_0_var |
| ; GFX9PLUS: liveins: $sgpr0 |
| ; GFX9PLUS-NEXT: {{ $}} |
| ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 |
| ; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] |
| ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] |
| %0:sgpr(s32) = G_CONSTANT i32 0 |
| %1:sgpr(s32) = COPY $sgpr0 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 |
| S_ENDPGM 0, implicit %2 |
| ... |