| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s |
| |
| --- |
| name: uitofp_char_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: uitofp_char_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 255 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s32) = G_UITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: uitofp_too_many_bits_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: uitofp_too_many_bits_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[UITOFP]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 256 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s32) = G_UITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: sitofp_char_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: sitofp_char_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 255 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s32) = G_SITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: sitofp_bits127_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: sitofp_bits127_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 127 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s32) = G_SITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: sitofp_bits128_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: sitofp_bits128_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 128 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s32) = G_SITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| --- |
| name: sitofp_too_many_bits_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: sitofp_too_many_bits_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[AND]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[SITOFP]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 256 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s32) = G_SITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: uitofp_char_to_f16 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: uitofp_char_to_f16 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]] |
| ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) |
| ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 255 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s16) = G_UITOFP %2 |
| %4:_(s32) = G_ANYEXT %3 |
| $vgpr0 = COPY %4 |
| ... |
| |
| --- |
| name: sitofp_char_to_f16 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: sitofp_char_to_f16 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]] |
| ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) |
| ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_CONSTANT i32 255 |
| %2:_(s32) = G_AND %0, %1 |
| %3:_(s16) = G_SITOFP %2 |
| %4:_(s32) = G_ANYEXT %3 |
| $vgpr0 = COPY %4 |
| ... |
| |
| --- |
| name: uitofp_s64_char_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1 |
| |
| ; CHECK-LABEL: name: uitofp_s64_char_to_f32 |
| ; CHECK: liveins: $vgpr0_vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[TRUNC]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s64) = G_CONSTANT i64 255 |
| %2:_(s64) = G_AND %0, %1 |
| %3:_(s32) = G_UITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: sitofp_s64_char_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1 |
| |
| ; CHECK-LABEL: name: sitofp_s64_char_to_f32 |
| ; CHECK: liveins: $vgpr0_vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[TRUNC]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s64) = G_CONSTANT i64 255 |
| %2:_(s64) = G_AND %0, %1 |
| %3:_(s32) = G_SITOFP %2 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: uitofp_s16_char_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: uitofp_s16_char_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]] |
| ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16) |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[ANYEXT]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s16) = G_TRUNC %0 |
| %2:_(s16) = G_CONSTANT i16 255 |
| %3:_(s16) = G_AND %1, %2 |
| %4:_(s32) = G_UITOFP %3 |
| $vgpr0 = COPY %4 |
| ... |
| |
| --- |
| name: sitofp_s16_char_to_f32 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: sitofp_s16_char_to_f32 |
| ; CHECK: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 |
| ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]] |
| ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16) |
| ; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[ANYEXT]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s16) = G_TRUNC %0 |
| %2:_(s16) = G_CONSTANT i16 255 |
| %3:_(s16) = G_AND %1, %2 |
| %4:_(s32) = G_SITOFP %3 |
| $vgpr0 = COPY %4 |
| ... |