[VectorCombine] add safety check for 0-width register
Based on post-commit discussion in D81766, Hexagon sets this to "0".
I'll see if I can come up with a test, but making the obvious
code fix first to unblock that target.
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 688ea8f..7faba73 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -107,7 +107,7 @@
unsigned VectorSize = TTI.getMinVectorRegisterBitWidth();
uint64_t ScalarSize = ScalarTy->getPrimitiveSizeInBits();
- if (!ScalarSize || VectorSize % ScalarSize != 0)
+ if (!ScalarSize || !VectorSize || VectorSize % ScalarSize != 0)
return false;
// Check safety of replacing the scalar load with a larger vector load.
