| # RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s |
| |
| # CHECK: while.body: |
| # CHECK-NOT: t2DLS |
| # CHECK-NOT: t2LEUpdate |
| |
| --- | |
| target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" |
| target triple = "thumbv8.1m.main" |
| |
| define i32 @skip_spill(i32 %n) #0 { |
| entry: |
| %cmp6 = icmp eq i32 %n, 0 |
| br i1 %cmp6, label %while.end, label %while.body.preheader |
| |
| while.body.preheader: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %n) |
| br label %while.body |
| |
| while.body: ; preds = %while.body, %while.body.preheader |
| %res.07 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ] |
| %0 = phi i32 [ %n, %while.body.preheader ], [ %1, %while.body ] |
| %call = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() |
| %add = add nsw i32 %call, %res.07 |
| %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) |
| %2 = icmp ne i32 %1, 0 |
| br i1 %2, label %while.body, label %while.end |
| |
| while.end: ; preds = %while.body, %entry |
| %res.0.lcssa = phi i32 [ 0, %entry ], [ %add, %while.body ] |
| ret i32 %res.0.lcssa |
| } |
| |
| declare i32 @bar(...) local_unnamed_addr #0 |
| |
| declare void @llvm.set.loop.iterations.i32(i32) #1 |
| declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 |
| |
| attributes #0 = { "target-features"="+mve.fp" } |
| attributes #1 = { noduplicate nounwind } |
| attributes #2 = { nounwind } |
| |
| ... |
| --- |
| name: skip_spill |
| alignment: 2 |
| exposesReturnsTwice: false |
| legalized: false |
| regBankSelected: false |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| hasWinCFI: false |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| frameInfo: |
| isFrameAddressTaken: false |
| isReturnAddressTaken: false |
| hasStackMap: false |
| hasPatchPoint: false |
| stackSize: 16 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| adjustsStack: true |
| hasCalls: true |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| hasOpaqueSPAdjustment: false |
| hasVAStart: false |
| hasMustTailInVarArgFunc: false |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r4, $r5, $r7, $lr |
| |
| frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 16 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| frame-setup CFI_INSTRUCTION offset $r5, -12 |
| frame-setup CFI_INSTRUCTION offset $r4, -16 |
| tCBZ $r0, %bb.4 |
| |
| bb.1.while.body.preheader: |
| successors: %bb.2(0x80000000) |
| liveins: $r0 |
| |
| $lr = tMOVr $r0, 14, $noreg |
| renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg |
| t2DoLoopStart killed $r0 |
| |
| bb.2.while.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $lr, $r4 |
| |
| $r5 = tMOVr killed $lr, 14, $noreg |
| tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 |
| $lr = tMOVr killed $r5, 14, $noreg |
| renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14, $noreg |
| |
| bb.3.while.end: |
| liveins: $r4 |
| |
| $r0 = tMOVr killed $r4, 14, $noreg |
| tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg |
| $r0 = tMOVr killed $r4, 14, $noreg |
| tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
