llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.

...
---
name:            DUPv4i32gpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv4i32gpr
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %dup:fpr128 = DUPv4i32gpr %copy
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:gpr(s32) = COPY $w0
    %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
    $q0 = COPY %dup(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i64gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: DUPv2i64gpr
    ; CHECK: liveins: $x0
    ; CHECK: %copy:gpr64 = COPY $x0
    ; CHECK: %dup:fpr128 = DUPv2i64gpr %copy
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:gpr(s64) = COPY $x0
    %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
    $q0 = COPY %dup(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i32gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv2i32gpr
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %dup:fpr64 = DUPv2i32gpr %copy
    ; CHECK: $d0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $d0
    %copy:gpr(s32) = COPY $w0
    %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
    $d0 = COPY %dup(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv4i32lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $s0

    ; CHECK-LABEL: name: DUPv4i32lane
    ; CHECK: liveins: $s0
    ; CHECK: %copy:fpr32 = COPY $s0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
    ; CHECK: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:fpr(s32) = COPY $s0
    %dup:fpr(<4 x s32>) = G_DUP %copy(s32)
    $q0 = COPY %dup(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i64lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $d0
    ; CHECK-LABEL: name: DUPv2i64lane
    ; CHECK: liveins: $d0
    ; CHECK: %copy:fpr64 = COPY $d0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub
    ; CHECK: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:fpr(s64) = COPY $d0
    %dup:fpr(<2 x s64>) = G_DUP %copy(s64)
    $q0 = COPY %dup(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv2i32lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $s0
    ; CHECK-LABEL: name: DUPv2i32lane
    ; CHECK: liveins: $s0
    ; CHECK: %copy:fpr32 = COPY $s0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
    ; CHECK: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
    ; CHECK: $d0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $d0
    %copy:fpr(s32) = COPY $s0
    %dup:fpr(<2 x s32>) = G_DUP %copy(s32)
    $d0 = COPY %dup(<2 x s32>)
    RET_ReallyLR implicit $d0


...
---
name:            DUPv4i16lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $h0
    ; CHECK-LABEL: name: DUPv4i16lane
    ; CHECK: liveins: $h0
    ; CHECK: %copy:fpr16 = COPY $h0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
    ; CHECK: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
    ; CHECK: $d0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $d0
    %copy:fpr(s16) = COPY $h0
    %dup:fpr(<4 x s16>) = G_DUP %copy(s16)
    $d0 = COPY %dup(<4 x s16>)
    RET_ReallyLR implicit $d0
...
---
name:            DUPv4i16gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv4i16gpr
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %dup:fpr64 = DUPv4i16gpr %copy
    ; CHECK: $d0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $d0
    %copy:gpr(s32) = COPY $w0
    %dup:fpr(<4 x s16>) = G_DUP %copy(s32)
    $d0 = COPY %dup(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv8i16lane
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $h0
    ; CHECK-LABEL: name: DUPv8i16lane
    ; CHECK: liveins: $h0
    ; CHECK: %copy:fpr16 = COPY $h0
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
    ; CHECK: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:fpr(s16) = COPY $h0
    %dup:fpr(<8 x s16>) = G_DUP %copy(s16)
    $q0 = COPY %dup(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv8i16gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv8i16gpr
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %dup:fpr128 = DUPv8i16gpr %copy
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:gpr(s32) = COPY $w0
    %dup:fpr(<8 x s16>) = G_DUP %copy(s32)
    $q0 = COPY %dup(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            DUPv8i8gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv8i8gpr
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %dup:fpr64 = DUPv8i8gpr %copy
    ; CHECK: $d0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $d0
    %copy:gpr(s32) = COPY $w0
    %dup:fpr(<8 x s8>) = G_DUP %copy(s32)
    $d0 = COPY %dup(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            DUPv16i8gpr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $w0
    ; CHECK-LABEL: name: DUPv16i8gpr
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %dup:fpr128 = DUPv16i8gpr %copy
    ; CHECK: $q0 = COPY %dup
    ; CHECK: RET_ReallyLR implicit $q0
    %copy:gpr(s32) = COPY $w0
    %dup:fpr(<16 x s8>) = G_DUP %copy(s32)
    $q0 = COPY %dup(<16 x s8>)
    RET_ReallyLR implicit $q0