i965_drv_video/shaders/mpeg2/vld/null.g4a

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Author:
 *    Zou Nan hai <nanhai.zou@intel.com>
 *
 */
mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1};
mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1};
define(`UV_red',`0xffffffffUD')
define(`UV_white',`0x7f7f7f7fUD')
define(`UV_green',`0x00000000UD')

mov(2) g6.0<1>UD g82.12<2,2,1>UW {align1};
mov(1) g6.8<1>UD 0x000f000fUD  { align1 };
mov(16) m1<1>UD 0xFFFFFFFFUD {align1 compr};
mov(16) m3<1>UD 0xFFFFFFFFUD {align1 compr};
mov(16) m5<1>UD 0xFFFFFFFFUD {align1 compr};
mov(16) m7<1>UD 0xFFFFFFFFUD {align1 compr};
send (16) 0 acc0<1>UW g6<8,8,1>UW write(0, 0, 2, 0) mlen 9 rlen 0 { align1 };

/*Fill U buffer & V buffer with 0x7F*/
shr (2) g6.0<1>UD g82.12<2,2,1>UW  1UW {align1};

mov(1) g6.8<1>UD 0x00070007UD  { align1 };
mov (16) m1<1>UD UV_white {align1 compr};
//mov (16) m1<1>UD g1.0<16,8,1>UD {align1 compr};
send (16) 0 acc0<1>UW g6<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 };
send (16) 0 acc0<1>UW g6<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 };

send (16) 0 acc0<1>UW g0<8,8,1>UW 
	thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT};