commit f6c91364b0911a7513e9543fd874360ec8901742
author John Machado <john.machado@intel.com> Sun Sep 06 08:42:01 2020 +0530
committer gbsbuild <gbsbuild@intel.com> Mon Sep 07 03:17:11 2020 -0700
tree de39826f3c54f6d174b26c14e02f7e6cc61b97fa
parent db62cba9532b1b7d8f57b884b986bb9c10e65416

Do not use memset for clearing an object of non-trivial type.

Change-Id: I1d5cd613ae8df9ea195245997036a988a4a692ef

Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h

diff --git a/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h b/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
index 87d2061..c774778 100644
--- a/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
+++ b/Source/GmmLib/TranslationTable/GmmUmdTranslationTable.h
@@ -429,7 +429,7 @@
         const int NodesPerTable;                   //Aux L2/L3 has 32KB size, Aux L1 has 4KB -can't use as selector for PageTable is AuxTT
                                                    // 1 node for TR-table, 8 nodes for Aux-Table L2, 2 nodes for Aux-table L1
         //Root Table structure
-        struct
+        struct RootTable
         {
             GMM_RESOURCE_INFO* pGmmResInfo;
             HANDLE         L3Handle;
@@ -437,6 +437,7 @@
             GMM_GFX_ADDRESS  CPUAddress;              //LMEM-cpuvisible adr
             bool        NeedRegisterUpdate;        //True @ L3 allocation, False when L3AdrRegWrite done
             SyncInfo        BBInfo;
+            RootTable() : pGmmResInfo(NULL), L3Handle(NULL), GfxAddress(0), CPUAddress(0), NeedRegisterUpdate(false), BBInfo() {}
         } TTL3;
 
         MidLevelTable*   pTTL2;                      //array of L2-Tables
@@ -455,8 +456,6 @@
             NodesPerTable(Size / PAGE_SIZE),
             TTType(flag)
         {
-            memset(&TTL3, 0, sizeof(TTL3));
-
             InitializeCriticalSection(&TTLock);
 
             pTTL2 = new MidLevelTable[NumL3e];