opcodes/xc16x-desc.c

/* CPU data for xc16x.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996-2016 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

   This file is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License along
   with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.

*/

#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "xc16x-desc.h"
#include "xc16x-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"

/* Attributes.  */

static const CGEN_ATTR_ENTRY bool_attr[] =
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
{
  { "base", MACH_BASE },
  { "xc16x", MACH_XC16X },
  { "max", MACH_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
{
  { "xc16x", ISA_XC16X },
  { "max", ISA_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
{
  { "NONE", PIPE_NONE },
  { "OS", PIPE_OS },
  { 0, 0 }
};

const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "RELOC", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { "RELOC", &bool_attr[0], &bool_attr[0] },
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

/* Instruction set variants.  */

static const CGEN_ISA xc16x_cgen_isa_table[] = {
  { "xc16x", 16, 32, 16, 32 },
  { 0, 0, 0, 0, 0 }
};

/* Machine variants.  */

static const CGEN_MACH xc16x_cgen_mach_table[] = {
  { "xc16x", "xc16x", MACH_XC16X, 32 },
  { 0, 0, 0, 0 }
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_gr_names =
{
  & xc16x_cgen_opval_gr_names_entries[0],
  16,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
{
  { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_ext_names =
{
  & xc16x_cgen_opval_ext_names_entries[0],
  8,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
{
  { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
  { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
  { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
  { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
  { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
  { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
  { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
  { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
  { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
  { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_psw_names =
{
  & xc16x_cgen_opval_psw_names_entries[0],
  17,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
{
  { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_grb_names =
{
  & xc16x_cgen_opval_grb_names_entries[0],
  16,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
{
  { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
{
  & xc16x_cgen_opval_conditioncode_names_entries[0],
  20,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
{
  { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
{
  & xc16x_cgen_opval_extconditioncode_names_entries[0],
  24,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
{
  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
  { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
  { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
  { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
  { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
  { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
  { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
  { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
  { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
  { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
  { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
{
  & xc16x_cgen_opval_grb8_names_entries[0],
  36,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
{
  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
  { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
  { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
  { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
  { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
  { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
  { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_r8_names =
{
  & xc16x_cgen_opval_r8_names_entries[0],
  36,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
{
  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
  { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
  { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
  { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
  { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
  { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
  { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
{
  & xc16x_cgen_opval_regmem8_names_entries[0],
  36,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
  { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
  { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
  { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
  { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
  { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
  { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
  { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
  { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
  { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
  { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
{
  & xc16x_cgen_opval_regdiv8_names_entries[0],
  16,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
{
  { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
  { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
{
  & xc16x_cgen_opval_reg0_name_entries[0],
  30,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
{
  { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
{
  & xc16x_cgen_opval_reg0_name1_entries[0],
  14,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
{
  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
  { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
  { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
  { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
  { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
  { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
  { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
  { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
  { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
  { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
  { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
{
  & xc16x_cgen_opval_regbmem8_names_entries[0],
  36,
  0, 0, 0, 0, ""
};

static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
{
  { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
  { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
  { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
  { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
  { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
  { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
  { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
  { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
  { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
  { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
  { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
  { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
  { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
  { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
};

CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
{
  & xc16x_cgen_opval_memgr8_names_entries[0],
  20,
  0, 0, 0, 0, ""
};


/* The hardware table.  */

#define A(a) (1 << CGEN_HW_##a)

const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
{
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};

#undef A


/* The instruction field table.  */

#define A(a) (1 << CGEN_IFLD_##a)

const CGEN_IFLD xc16x_cgen_ifld_table[] =
{
  { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};

#undef A



/* multi ifield declarations */



/* multi ifield definitions */


/* The operand table.  */

#define A(a) (1 << CGEN_OPERAND_##a)
#define OPERAND(op) XC16X_OPERAND_##op

const CGEN_OPERAND xc16x_cgen_operand_table[] =
{
/* pc: program counter */
  { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
/* sr: source register */
  { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* dr: destination register */
  { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* dri: destination register */
  { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* srb: source register */
  { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* drb: destination register */
  { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* sr2: 2 bit source register */
  { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* src1: source register 1 */
  { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* src2: source register 2 */
  { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* srdiv: source register 2 */
  { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* RegNam: PSW bits */
  { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* uimm2: 2 bit unsigned number */
  { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* uimm3: 3 bit unsigned number */
  { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* uimm4: 4 bit unsigned number */
  { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* uimm7: 7 bit trap number */
  { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
    { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
/* uimm8: 8 bit unsigned immediate */
  { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* uimm16: 16 bit unsigned immediate */
  { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* upof16: 16 bit unsigned immediate */
  { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
    { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* reg8: 8 bit word register number */
  { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* regmem8: 8 bit word register number */
  { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* regbmem8: 8 bit byte register number */
  { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* regoff8: 8 bit word register number */
  { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* reghi8: 8 bit word register number */
  { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* regb8: 8 bit byte register number */
  { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* genreg: 8 bit word register number */
  { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* seg: 8 bit segment number */
  { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* seghi8: 8 bit hi segment number */
  { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* caddr: 16 bit address offset */
  { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
    { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
/* rel: 8 bit signed relative offset */
  { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
/* relhi: hi 8 bit signed relative offset */
  { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
/* condbit: condition bit */
  { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
/* bit1: gap of 1 bit */
  { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* bit2: gap of 2 bits */
  { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* bit4: gap of 4 bits */
  { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* lbit4: gap of 4 bits */
  { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* lbit2: gap of 2 bits */
  { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* bit8: gap of 8 bits */
  { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* u4: gap of 4 bits */
  { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* bitone: field of 1 bit */
  { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* bit01: field of 1 bit */
  { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* cond: condition code */
  { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* icond: indirect condition code */
  { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* extcond: extended condition code */
  { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* memory: 16 bit memory */
  { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* memgr8: 16 bit memory */
  { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* cbit: carry bit */
  { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
/* qbit: bit addr */
  { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
    { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* qlobit: bit addr */
  { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
    { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* qhibit: bit addr */
  { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
    { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* mask8: 8 bit mask */
  { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* masklo8: 8 bit mask */
  { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* pagenum: 10 bit page number */
  { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* data8: 8 bit data */
  { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* datahi8: 8 bit data */
  { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* sgtdisbit: segmentation enable bit */
  { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
/* upag16: 16 bit unsigned immediate */
  { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
    { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* useg8: 8 bit segment  */
  { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
    { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
/* useg16: 16 bit address offset */
  { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
    { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
/* usof16: 16 bit address offset */
  { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
    { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
/* hash: # prefix */
  { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* dot: . prefix */
  { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* pof: pof: prefix */
  { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* pag: pag: prefix */
  { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* sof: sof: prefix */
  { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* segm: seg: prefix */
  { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
/* sentinel */
  { 0, 0, 0, 0, 0,
    { 0, { (const PTR) 0 } },
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
};

#undef A


/* The instruction table.  */

#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#define A(a) (1 << CGEN_INSN_##a)

static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
{
  /* Special null first entry.
     A `num' value of zero is thus invalid.
     Also, the special `invalid' insn resides here.  */
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
/* add $reg8,$pof$upof16 */
  {
    XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $reg8,$pof$upof16 */
  {
    XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regb8,$pof$upof16 */
  {
    XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regb8,$pof$upof16 */
  {
    XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $reg8,$pag$upag16 */
  {
    XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $reg8,$pag$upag16 */
  {
    XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regb8,$pag$upag16 */
  {
    XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regb8,$pag$upag16 */
  {
    XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $reg8,$pof$upof16 */
  {
    XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $reg8,$pof$upof16 */
  {
    XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regb8,$pof$upof16 */
  {
    XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regb8,$pof$upof16 */
  {
    XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $reg8,$pag$upag16 */
  {
    XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $reg8,$pag$upag16 */
  {
    XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regb8,$pag$upag16 */
  {
    XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regb8,$pag$upag16 */
  {
    XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $pof$upof16,$reg8 */
  {
    XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $pof$upof16,$reg8 */
  {
    XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $pof$upof16,$regb8 */
  {
    XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $pof$upof16,$regb8 */
  {
    XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $pof$upof16,$reg8 */
  {
    XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $pof$upof16,$reg8 */
  {
    XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $pof$upof16,$regb8 */
  {
    XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $pof$upof16,$regb8 */
  {
    XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $reg8,$hash$pof$uimm16 */
  {
    XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $reg8,$hash$pof$uimm16 */
  {
    XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $reg8,$hash$pag$uimm16 */
  {
    XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $reg8,$hash$pag$uimm16 */
  {
    XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $dr,$hash$pof$uimm3 */
  {
    XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $dr,$hash$pof$uimm3 */
  {
    XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $drb,$hash$pag$uimm3 */
  {
    XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $drb,$hash$pag$uimm3 */
  {
    XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $dr,$hash$pag$uimm3 */
  {
    XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $dr,$hash$pag$uimm3 */
  {
    XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $drb,$hash$pof$uimm3 */
  {
    XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $drb,$hash$pof$uimm3 */
  {
    XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regb8,$hash$pof$uimm8 */
  {
    XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regb8,$hash$pof$uimm8 */
  {
    XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regb8,$hash$pag$uimm8 */
  {
    XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regb8,$hash$pag$uimm8 */
  {
    XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $reg8,$hash$pof$uimm16 */
  {
    XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $reg8,$hash$pof$uimm16 */
  {
    XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $reg8,$hash$pag$uimm16 */
  {
    XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $reg8,$hash$pag$uimm16 */
  {
    XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $dr,$hash$pof$uimm3 */
  {
    XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $dr,$hash$pof$uimm3 */
  {
    XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $drb,$hash$pag$uimm3 */
  {
    XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $drb,$hash$pag$uimm3 */
  {
    XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $dr,$hash$pag$uimm3 */
  {
    XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $dr,$hash$pag$uimm3 */
  {
    XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $drb,$hash$pof$uimm3 */
  {
    XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $drb,$hash$pof$uimm3 */
  {
    XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regb8,$hash$pof$uimm8 */
  {
    XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regb8,$hash$pof$uimm8 */
  {
    XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regb8,$hash$pag$uimm8 */
  {
    XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regb8,$hash$pag$uimm8 */
  {
    XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $dr,$hash$uimm3 */
  {
    XC16X_INSN_ADDRI, "addri", "add", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $dr,$hash$uimm3 */
  {
    XC16X_INSN_SUBRI, "subri", "sub", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $drb,$hash$uimm3 */
  {
    XC16X_INSN_ADDBRI, "addbri", "addb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $drb,$hash$uimm3 */
  {
    XC16X_INSN_SUBBRI, "subbri", "subb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $reg8,$hash$uimm16 */
  {
    XC16X_INSN_ADDRIM, "addrim", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $reg8,$hash$uimm16 */
  {
    XC16X_INSN_SUBRIM, "subrim", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regb8,$hash$uimm8 */
  {
    XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regb8,$hash$uimm8 */
  {
    XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $dr,$hash$uimm3 */
  {
    XC16X_INSN_ADDCRI, "addcri", "addc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $dr,$hash$uimm3 */
  {
    XC16X_INSN_SUBCRI, "subcri", "subc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $drb,$hash$uimm3 */
  {
    XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $drb,$hash$uimm3 */
  {
    XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $reg8,$hash$uimm16 */
  {
    XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $reg8,$hash$uimm16 */
  {
    XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regb8,$hash$uimm8 */
  {
    XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regb8,$hash$uimm8 */
  {
    XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $dr,$sr */
  {
    XC16X_INSN_ADDR, "addr", "add", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $dr,$sr */
  {
    XC16X_INSN_SUBR, "subr", "sub", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $drb,$srb */
  {
    XC16X_INSN_ADDBR, "addbr", "addb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $drb,$srb */
  {
    XC16X_INSN_SUBBR, "subbr", "subb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $dr,[$sr2] */
  {
    XC16X_INSN_ADD2, "add2", "add", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $dr,[$sr2] */
  {
    XC16X_INSN_SUB2, "sub2", "sub", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $drb,[$sr2] */
  {
    XC16X_INSN_ADDB2, "addb2", "addb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $drb,[$sr2] */
  {
    XC16X_INSN_SUBB2, "subb2", "subb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $dr,[$sr2+] */
  {
    XC16X_INSN_ADD2I, "add2i", "add", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $dr,[$sr2+] */
  {
    XC16X_INSN_SUB2I, "sub2i", "sub", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $drb,[$sr2+] */
  {
    XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $drb,[$sr2+] */
  {
    XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $dr,$sr */
  {
    XC16X_INSN_ADDCR, "addcr", "addc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $dr,$sr */
  {
    XC16X_INSN_SUBCR, "subcr", "subc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $drb,$srb */
  {
    XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $drb,$srb */
  {
    XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $dr,[$sr2] */
  {
    XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $dr,[$sr2] */
  {
    XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $drb,[$sr2] */
  {
    XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $drb,[$sr2] */
  {
    XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $dr,[$sr2+] */
  {
    XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $dr,[$sr2+] */
  {
    XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $drb,[$sr2+] */
  {
    XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $drb,[$sr2+] */
  {
    XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $regmem8,$memgr8 */
  {
    XC16X_INSN_ADDRM2, "addrm2", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $memgr8,$regmem8 */
  {
    XC16X_INSN_ADDRM3, "addrm3", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $reg8,$memory */
  {
    XC16X_INSN_ADDRM, "addrm", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* add $memory,$reg8 */
  {
    XC16X_INSN_ADDRM1, "addrm1", "add", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $regmem8,$memgr8 */
  {
    XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $memgr8,$regmem8 */
  {
    XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $reg8,$memory */
  {
    XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* sub $memory,$reg8 */
  {
    XC16X_INSN_SUBRM, "subrm", "sub", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regbmem8,$memgr8 */
  {
    XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $memgr8,$regbmem8 */
  {
    XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $regb8,$memory */
  {
    XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addb $memory,$regb8 */
  {
    XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regbmem8,$memgr8 */
  {
    XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $memgr8,$regbmem8 */
  {
    XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $regb8,$memory */
  {
    XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subb $memory,$regb8 */
  {
    XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $regmem8,$memgr8 */
  {
    XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $memgr8,$regmem8 */
  {
    XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $reg8,$memory */
  {
    XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addc $memory,$reg8 */
  {
    XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $regmem8,$memgr8 */
  {
    XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $memgr8,$regmem8 */
  {
    XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $reg8,$memory */
  {
    XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subc $memory,$reg8 */
  {
    XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regbmem8,$memgr8 */
  {
    XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $memgr8,$regbmem8 */
  {
    XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $regb8,$memory */
  {
    XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* addcb $memory,$regb8 */
  {
    XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regbmem8,$memgr8 */
  {
    XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $memgr8,$regbmem8 */
  {
    XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $regb8,$memory */
  {
    XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* subcb $memory,$regb8 */
  {
    XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* mul $src1,$src2 */
  {
    XC16X_INSN_MULS, "muls", "mul", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* mulu $src1,$src2 */
  {
    XC16X_INSN_MULU, "mulu", "mulu", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* div $srdiv */
  {
    XC16X_INSN_DIV, "div", "div", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* divl $srdiv */
  {
    XC16X_INSN_DIVL, "divl", "divl", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* divlu $srdiv */
  {
    XC16X_INSN_DIVLU, "divlu", "divlu", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* divu $srdiv */
  {
    XC16X_INSN_DIVU, "divu", "divu", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* cpl $dr */
  {
    XC16X_INSN_CPL, "cpl", "cpl", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* cplb $drb */
  {
    XC16X_INSN_CPLB, "cplb", "cplb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* neg $dr */
  {
    XC16X_INSN_NEG, "neg", "neg", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* negb $drb */
  {
    XC16X_INSN_NEGB, "negb", "negb", 16,
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
  },
/* and $dr,$sr */
  {
    XC16X_INSN_ANDR, "andr", "and", 16,
    {