| /* Print i386 instructions for GDB, the GNU debugger. |
| Copyright (C) 1988-2016 Free Software Foundation, Inc. |
| |
| This file is part of the GNU opcodes library. |
| |
| This library is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| |
| It is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with this program; if not, write to the Free Software |
| Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| |
| |
| /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) |
| July 1988 |
| modified by John Hassey (hassey@dg-rtp.dg.com) |
| x86-64 support added by Jan Hubicka (jh@suse.cz) |
| VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ |
| |
| /* The main tables describing the instructions is essentially a copy |
| of the "Opcode Map" chapter (Appendix A) of the Intel 80386 |
| Programmers Manual. Usually, there is a capital letter, followed |
| by a small letter. The capital letter tell the addressing mode, |
| and the small letter tells about the operand size. Refer to |
| the Intel manual for details. */ |
| |
| #include "sysdep.h" |
| #include "dis-asm.h" |
| #include "opintl.h" |
| #include "opcode/i386.h" |
| #include "libiberty.h" |
| |
| #include <setjmp.h> |
| |
| static int print_insn (bfd_vma, disassemble_info *); |
| static void dofloat (int); |
| static void OP_ST (int, int); |
| static void OP_STi (int, int); |
| static int putop (const char *, int); |
| static void oappend (const char *); |
| static void append_seg (void); |
| static void OP_indirE (int, int); |
| static void print_operand_value (char *, int, bfd_vma); |
| static void OP_E_register (int, int); |
| static void OP_E_memory (int, int); |
| static void print_displacement (char *, bfd_vma); |
| static void OP_E (int, int); |
| static void OP_G (int, int); |
| static bfd_vma get64 (void); |
| static bfd_signed_vma get32 (void); |
| static bfd_signed_vma get32s (void); |
| static int get16 (void); |
| static void set_op (bfd_vma, int); |
| static void OP_Skip_MODRM (int, int); |
| static void OP_REG (int, int); |
| static void OP_IMREG (int, int); |
| static void OP_I (int, int); |
| static void OP_I64 (int, int); |
| static void OP_sI (int, int); |
| static void OP_J (int, int); |
| static void OP_SEG (int, int); |
| static void OP_DIR (int, int); |
| static void OP_OFF (int, int); |
| static void OP_OFF64 (int, int); |
| static void ptr_reg (int, int); |
| static void OP_ESreg (int, int); |
| static void OP_DSreg (int, int); |
| static void OP_C (int, int); |
| static void OP_D (int, int); |
| static void OP_T (int, int); |
| static void OP_R (int, int); |
| static void OP_MMX (int, int); |
| static void OP_XMM (int, int); |
| static void OP_EM (int, int); |
| static void OP_EX (int, int); |
| static void OP_EMC (int,int); |
| static void OP_MXC (int,int); |
| static void OP_MS (int, int); |
| static void OP_XS (int, int); |
| static void OP_M (int, int); |
| static void OP_VEX (int, int); |
| static void OP_EX_Vex (int, int); |
| static void OP_EX_VexW (int, int); |
| static void OP_EX_VexImmW (int, int); |
| static void OP_XMM_Vex (int, int); |
| static void OP_XMM_VexW (int, int); |
| static void OP_Rounding (int, int); |
| static void OP_REG_VexI4 (int, int); |
| static void PCLMUL_Fixup (int, int); |
| static void VEXI4_Fixup (int, int); |
| static void VZERO_Fixup (int, int); |
| static void VCMP_Fixup (int, int); |
| static void VPCMP_Fixup (int, int); |
| static void OP_0f07 (int, int); |
| static void OP_Monitor (int, int); |
| static void OP_Mwait (int, int); |
| static void OP_Mwaitx (int, int); |
| static void NOP_Fixup1 (int, int); |
| static void NOP_Fixup2 (int, int); |
| static void OP_3DNowSuffix (int, int); |
| static void CMP_Fixup (int, int); |
| static void BadOp (void); |
| static void REP_Fixup (int, int); |
| static void BND_Fixup (int, int); |
| static void HLE_Fixup1 (int, int); |
| static void HLE_Fixup2 (int, int); |
| static void HLE_Fixup3 (int, int); |
| static void CMPXCHG8B_Fixup (int, int); |
| static void XMM_Fixup (int, int); |
| static void CRC32_Fixup (int, int); |
| static void FXSAVE_Fixup (int, int); |
| static void OP_LWPCB_E (int, int); |
| static void OP_LWP_E (int, int); |
| static void OP_Vex_2src_1 (int, int); |
| static void OP_Vex_2src_2 (int, int); |
| |
| static void MOVBE_Fixup (int, int); |
| |
| static void OP_Mask (int, int); |
| |
| struct dis_private { |
| /* Points to first byte not fetched. */ |
| bfd_byte *max_fetched; |
| bfd_byte the_buffer[MAX_MNEM_SIZE]; |
| bfd_vma insn_start; |
| int orig_sizeflag; |
| OPCODES_SIGJMP_BUF bailout; |
| }; |
| |
| enum address_mode |
| { |
| mode_16bit, |
| mode_32bit, |
| mode_64bit |
| }; |
| |
| enum address_mode address_mode; |
| |
| /* Flags for the prefixes for the current instruction. See below. */ |
| static int prefixes; |
| |
| /* REX prefix the current instruction. See below. */ |
| static int rex; |
| /* Bits of REX we've already used. */ |
| static int rex_used; |
| /* REX bits in original REX prefix ignored. */ |
| static int rex_ignored; |
| /* Mark parts used in the REX prefix. When we are testing for |
| empty prefix (for 8bit register REX extension), just mask it |
| out. Otherwise test for REX bit is excuse for existence of REX |
| only in case value is nonzero. */ |
| #define USED_REX(value) \ |
| { \ |
| if (value) \ |
| { \ |
| if ((rex & value)) \ |
| rex_used |= (value) | REX_OPCODE; \ |
| } \ |
| else \ |
| rex_used |= REX_OPCODE; \ |
| } |
| |
| /* Flags for prefixes which we somehow handled when printing the |
| current instruction. */ |
| static int used_prefixes; |
| |
| /* Flags stored in PREFIXES. */ |
| #define PREFIX_REPZ 1 |
| #define PREFIX_REPNZ 2 |
| #define PREFIX_LOCK 4 |
| #define PREFIX_CS 8 |
| #define PREFIX_SS 0x10 |
| #define PREFIX_DS 0x20 |
| #define PREFIX_ES 0x40 |
| #define PREFIX_FS 0x80 |
| #define PREFIX_GS 0x100 |
| #define PREFIX_DATA 0x200 |
| #define PREFIX_ADDR 0x400 |
| #define PREFIX_FWAIT 0x800 |
| |
| /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
| to ADDR (exclusive) are valid. Returns 1 for success, longjmps |
| on error. */ |
| #define FETCH_DATA(info, addr) \ |
| ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
| ? 1 : fetch_data ((info), (addr))) |
| |
| static int |
| fetch_data (struct disassemble_info *info, bfd_byte *addr) |
| { |
| int status; |
| struct dis_private *priv = (struct dis_private *) info->private_data; |
| bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
| |
| if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
| status = (*info->read_memory_func) (start, |
| priv->max_fetched, |
| addr - priv->max_fetched, |
| info); |
| else |
| status = -1; |
| if (status != 0) |
| { |
| /* If we did manage to read at least one byte, then |
| print_insn_i386 will do something sensible. Otherwise, print |
| an error. We do that here because this is where we know |
| STATUS. */ |
| if (priv->max_fetched == priv->the_buffer) |
| (*info->memory_error_func) (status, start, info); |
| OPCODES_SIGLONGJMP (priv->bailout, 1); |
| } |
| else |
| priv->max_fetched = addr; |
| return 1; |
| } |
| |
| /* Possible values for prefix requirement. */ |
| #define PREFIX_IGNORED_SHIFT 16 |
| #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) |
| #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) |
| #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) |
| #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) |
| #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) |
| |
| /* Opcode prefixes. */ |
| #define PREFIX_OPCODE (PREFIX_REPZ \ |
| | PREFIX_REPNZ \ |
| | PREFIX_DATA) |
| |
| /* Prefixes ignored. */ |
| #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ |
| | PREFIX_IGNORED_REPNZ \ |
| | PREFIX_IGNORED_DATA) |
| |
| #define XX { NULL, 0 } |
| #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
| |
| #define Eb { OP_E, b_mode } |
| #define Ebnd { OP_E, bnd_mode } |
| #define EbS { OP_E, b_swap_mode } |
| #define Ev { OP_E, v_mode } |
| #define Ev_bnd { OP_E, v_bnd_mode } |
| #define EvS { OP_E, v_swap_mode } |
| #define Ed { OP_E, d_mode } |
| #define Edq { OP_E, dq_mode } |
| #define Edqw { OP_E, dqw_mode } |
| #define Edqb { OP_E, dqb_mode } |
| #define Edb { OP_E, db_mode } |
| #define Edw { OP_E, dw_mode } |
| #define Edqd { OP_E, dqd_mode } |
| #define Eq { OP_E, q_mode } |
| #define indirEv { OP_indirE, indir_v_mode } |
| #define indirEp { OP_indirE, f_mode } |
| #define stackEv { OP_E, stack_v_mode } |
| #define Em { OP_E, m_mode } |
| #define Ew { OP_E, w_mode } |
| #define M { OP_M, 0 } /* lea, lgdt, etc. */ |
| #define Ma { OP_M, a_mode } |
| #define Mb { OP_M, b_mode } |
| #define Md { OP_M, d_mode } |
| #define Mo { OP_M, o_mode } |
| #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
| #define Mq { OP_M, q_mode } |
| #define Mx { OP_M, x_mode } |
| #define Mxmm { OP_M, xmm_mode } |
| #define Gb { OP_G, b_mode } |
| #define Gbnd { OP_G, bnd_mode } |
| #define Gv { OP_G, v_mode } |
| #define Gd { OP_G, d_mode } |
| #define Gdq { OP_G, dq_mode } |
| #define Gm { OP_G, m_mode } |
| #define Gw { OP_G, w_mode } |
| #define Rd { OP_R, d_mode } |
| #define Rdq { OP_R, dq_mode } |
| #define Rm { OP_R, m_mode } |
| #define Ib { OP_I, b_mode } |
| #define sIb { OP_sI, b_mode } /* sign extened byte */ |
| #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
| #define Iv { OP_I, v_mode } |
| #define sIv { OP_sI, v_mode } |
| #define Iq { OP_I, q_mode } |
| #define Iv64 { OP_I64, v_mode } |
| #define Iw { OP_I, w_mode } |
| #define I1 { OP_I, const_1_mode } |
| #define Jb { OP_J, b_mode } |
| #define Jv { OP_J, v_mode } |
| #define Cm { OP_C, m_mode } |
| #define Dm { OP_D, m_mode } |
| #define Td { OP_T, d_mode } |
| #define Skip_MODRM { OP_Skip_MODRM, 0 } |
| |
| #define RMeAX { OP_REG, eAX_reg } |
| #define RMeBX { OP_REG, eBX_reg } |
| #define RMeCX { OP_REG, eCX_reg } |
| #define RMeDX { OP_REG, eDX_reg } |
| #define RMeSP { OP_REG, eSP_reg } |
| #define RMeBP { OP_REG, eBP_reg } |
| #define RMeSI { OP_REG, eSI_reg } |
| #define RMeDI { OP_REG, eDI_reg } |
| #define RMrAX { OP_REG, rAX_reg } |
| #define RMrBX { OP_REG, rBX_reg } |
| #define RMrCX { OP_REG, rCX_reg } |
| #define RMrDX { OP_REG, rDX_reg } |
| #define RMrSP { OP_REG, rSP_reg } |
| #define RMrBP { OP_REG, rBP_reg } |
| #define RMrSI { OP_REG, rSI_reg } |
| #define RMrDI { OP_REG, rDI_reg } |
| #define RMAL { OP_REG, al_reg } |
| #define RMCL { OP_REG, cl_reg } |
| #define RMDL { OP_REG, dl_reg } |
| #define RMBL { OP_REG, bl_reg } |
| #define RMAH { OP_REG, ah_reg } |
| #define RMCH { OP_REG, ch_reg } |
| #define RMDH { OP_REG, dh_reg } |
| #define RMBH { OP_REG, bh_reg } |
| #define RMAX { OP_REG, ax_reg } |
| #define RMDX { OP_REG, dx_reg } |
| |
| #define eAX { OP_IMREG, eAX_reg } |
| #define eBX { OP_IMREG, eBX_reg } |
| #define eCX { OP_IMREG, eCX_reg } |
| #define eDX { OP_IMREG, eDX_reg } |
| #define eSP { OP_IMREG, eSP_reg } |
| #define eBP { OP_IMREG, eBP_reg } |
| #define eSI { OP_IMREG, eSI_reg } |
| #define eDI { OP_IMREG, eDI_reg } |
| #define AL { OP_IMREG, al_reg } |
| #define CL { OP_IMREG, cl_reg } |
| #define DL { OP_IMREG, dl_reg } |
| #define BL { OP_IMREG, bl_reg } |
| #define AH { OP_IMREG, ah_reg } |
| #define CH { OP_IMREG, ch_reg } |
| #define DH { OP_IMREG, dh_reg } |
| #define BH { OP_IMREG, bh_reg } |
| #define AX { OP_IMREG, ax_reg } |
| #define DX { OP_IMREG, dx_reg } |
| #define zAX { OP_IMREG, z_mode_ax_reg } |
| #define indirDX { OP_IMREG, indir_dx_reg } |
| |
| #define Sw { OP_SEG, w_mode } |
| #define Sv { OP_SEG, v_mode } |
| #define Ap { OP_DIR, 0 } |
| #define Ob { OP_OFF64, b_mode } |
| #define Ov { OP_OFF64, v_mode } |
| #define Xb { OP_DSreg, eSI_reg } |
| #define Xv { OP_DSreg, eSI_reg } |
| #define Xz { OP_DSreg, eSI_reg } |
| #define Yb { OP_ESreg, eDI_reg } |
| #define Yv { OP_ESreg, eDI_reg } |
| #define DSBX { OP_DSreg, eBX_reg } |
| |
| #define es { OP_REG, es_reg } |
| #define ss { OP_REG, ss_reg } |
| #define cs { OP_REG, cs_reg } |
| #define ds { OP_REG, ds_reg } |
| #define fs { OP_REG, fs_reg } |
| #define gs { OP_REG, gs_reg } |
| |
| #define MX { OP_MMX, 0 } |
| #define XM { OP_XMM, 0 } |
| #define XMScalar { OP_XMM, scalar_mode } |
| #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
| #define XMM { OP_XMM, xmm_mode } |
| #define XMxmmq { OP_XMM, xmmq_mode } |
| #define EM { OP_EM, v_mode } |
| #define EMS { OP_EM, v_swap_mode } |
| #define EMd { OP_EM, d_mode } |
| #define EMx { OP_EM, x_mode } |
| #define EXw { OP_EX, w_mode } |
| #define EXd { OP_EX, d_mode } |
| #define EXdScalar { OP_EX, d_scalar_mode } |
| #define EXdS { OP_EX, d_swap_mode } |
| #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
| #define EXq { OP_EX, q_mode } |
| #define EXqScalar { OP_EX, q_scalar_mode } |
| #define EXqScalarS { OP_EX, q_scalar_swap_mode } |
| #define EXqS { OP_EX, q_swap_mode } |
| #define EXx { OP_EX, x_mode } |
| #define EXxS { OP_EX, x_swap_mode } |
| #define EXxmm { OP_EX, xmm_mode } |
| #define EXymm { OP_EX, ymm_mode } |
| #define EXxmmq { OP_EX, xmmq_mode } |
| #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
| #define EXxmm_mb { OP_EX, xmm_mb_mode } |
| #define EXxmm_mw { OP_EX, xmm_mw_mode } |
| #define EXxmm_md { OP_EX, xmm_md_mode } |
| #define EXxmm_mq { OP_EX, xmm_mq_mode } |
| #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
| #define EXxmmdw { OP_EX, xmmdw_mode } |
| #define EXxmmqd { OP_EX, xmmqd_mode } |
| #define EXymmq { OP_EX, ymmq_mode } |
| #define EXVexWdq { OP_EX, vex_w_dq_mode } |
| #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
| #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
| #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } |
| #define MS { OP_MS, v_mode } |
| #define XS { OP_XS, v_mode } |
| #define EMCq { OP_EMC, q_mode } |
| #define MXC { OP_MXC, 0 } |
| #define OPSUF { OP_3DNowSuffix, 0 } |
| #define CMP { CMP_Fixup, 0 } |
| #define XMM0 { XMM_Fixup, 0 } |
| #define FXSAVE { FXSAVE_Fixup, 0 } |
| #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
| #define Vex_2src_2 { OP_Vex_2src_2, 0 } |
| |
| #define Vex { OP_VEX, vex_mode } |
| #define VexScalar { OP_VEX, vex_scalar_mode } |
| #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
| #define Vex128 { OP_VEX, vex128_mode } |
| #define Vex256 { OP_VEX, vex256_mode } |
| #define VexGdq { OP_VEX, dq_mode } |
| #define VexI4 { VEXI4_Fixup, 0} |
| #define EXdVex { OP_EX_Vex, d_mode } |
| #define EXdVexS { OP_EX_Vex, d_swap_mode } |
| #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
| #define EXqVex { OP_EX_Vex, q_mode } |
| #define EXqVexS { OP_EX_Vex, q_swap_mode } |
| #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
| #define EXVexW { OP_EX_VexW, x_mode } |
| #define EXdVexW { OP_EX_VexW, d_mode } |
| #define EXqVexW { OP_EX_VexW, q_mode } |
| #define EXVexImmW { OP_EX_VexImmW, x_mode } |
| #define XMVex { OP_XMM_Vex, 0 } |
| #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
| #define XMVexW { OP_XMM_VexW, 0 } |
| #define XMVexI4 { OP_REG_VexI4, x_mode } |
| #define PCLMUL { PCLMUL_Fixup, 0 } |
| #define VZERO { VZERO_Fixup, 0 } |
| #define VCMP { VCMP_Fixup, 0 } |
| #define VPCMP { VPCMP_Fixup, 0 } |
| |
| #define EXxEVexR { OP_Rounding, evex_rounding_mode } |
| #define EXxEVexS { OP_Rounding, evex_sae_mode } |
| |
| #define XMask { OP_Mask, mask_mode } |
| #define MaskG { OP_G, mask_mode } |
| #define MaskE { OP_E, mask_mode } |
| #define MaskBDE { OP_E, mask_bd_mode } |
| #define MaskR { OP_R, mask_mode } |
| #define MaskVex { OP_VEX, mask_mode } |
| |
| #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
| #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
| #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
| #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
| |
| /* Used handle "rep" prefix for string instructions. */ |
| #define Xbr { REP_Fixup, eSI_reg } |
| #define Xvr { REP_Fixup, eSI_reg } |
| #define Ybr { REP_Fixup, eDI_reg } |
| #define Yvr { REP_Fixup, eDI_reg } |
| #define Yzr { REP_Fixup, eDI_reg } |
| #define indirDXr { REP_Fixup, indir_dx_reg } |
| #define ALr { REP_Fixup, al_reg } |
| #define eAXr { REP_Fixup, eAX_reg } |
| |
| /* Used handle HLE prefix for lockable instructions. */ |
| #define Ebh1 { HLE_Fixup1, b_mode } |
| #define Evh1 { HLE_Fixup1, v_mode } |
| #define Ebh2 { HLE_Fixup2, b_mode } |
| #define Evh2 { HLE_Fixup2, v_mode } |
| #define Ebh3 { HLE_Fixup3, b_mode } |
| #define Evh3 { HLE_Fixup3, v_mode } |
| |
| #define BND { BND_Fixup, 0 } |
| |
| #define cond_jump_flag { NULL, cond_jump_mode } |
| #define loop_jcxz_flag { NULL, loop_jcxz_mode } |
| |
| /* bits in sizeflag */ |
| #define SUFFIX_ALWAYS 4 |
| #define AFLAG 2 |
| #define DFLAG 1 |
| |
| enum |
| { |
| /* byte operand */ |
| b_mode = 1, |
| /* byte operand with operand swapped */ |
| b_swap_mode, |
| /* byte operand, sign extend like 'T' suffix */ |
| b_T_mode, |
| /* operand size depends on prefixes */ |
| v_mode, |
| /* operand size depends on prefixes with operand swapped */ |
| v_swap_mode, |
| /* word operand */ |
| w_mode, |
| /* double word operand */ |
| d_mode, |
| /* double word operand with operand swapped */ |
| d_swap_mode, |
| /* quad word operand */ |
| q_mode, |
| /* quad word operand with operand swapped */ |
| q_swap_mode, |
| /* ten-byte operand */ |
| t_mode, |
| /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
| broadcast enabled. */ |
| x_mode, |
| /* Similar to x_mode, but with different EVEX mem shifts. */ |
| evex_x_gscat_mode, |
| /* Similar to x_mode, but with disabled broadcast. */ |
| evex_x_nobcst_mode, |
| /* Similar to x_mode, but with operands swapped and disabled broadcast |
| in EVEX. */ |
| x_swap_mode, |
| /* 16-byte XMM operand */ |
| xmm_mode, |
| /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
| memory operand (depending on vector length). Broadcast isn't |
| allowed. */ |
| xmmq_mode, |
| /* Same as xmmq_mode, but broadcast is allowed. */ |
| evex_half_bcst_xmmq_mode, |
| /* XMM register or byte memory operand */ |
| xmm_mb_mode, |
| /* XMM register or word memory operand */ |
| xmm_mw_mode, |
| /* XMM register or double word memory operand */ |
| xmm_md_mode, |
| /* XMM register or quad word memory operand */ |
| xmm_mq_mode, |
| /* XMM register or double/quad word memory operand, depending on |
| VEX.W. */ |
| xmm_mdq_mode, |
| /* 16-byte XMM, word, double word or quad word operand. */ |
| xmmdw_mode, |
| /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
| xmmqd_mode, |
| /* 32-byte YMM operand */ |
| ymm_mode, |
| /* quad word, ymmword or zmmword memory operand. */ |
| ymmq_mode, |
| /* 32-byte YMM or 16-byte word operand */ |
| ymmxmm_mode, |
| /* d_mode in 32bit, q_mode in 64bit mode. */ |
| m_mode, |
| /* pair of v_mode operands */ |
| a_mode, |
| cond_jump_mode, |
| loop_jcxz_mode, |
| v_bnd_mode, |
| /* operand size depends on REX prefixes. */ |
| dq_mode, |
| /* registers like dq_mode, memory like w_mode. */ |
| dqw_mode, |
| bnd_mode, |
| /* 4- or 6-byte pointer operand */ |
| f_mode, |
| const_1_mode, |
| /* v_mode for indirect branch opcodes. */ |
| indir_v_mode, |
| /* v_mode for stack-related opcodes. */ |
| stack_v_mode, |
| /* non-quad operand size depends on prefixes */ |
| z_mode, |
| /* 16-byte operand */ |
| o_mode, |
| /* registers like dq_mode, memory like b_mode. */ |
| dqb_mode, |
| /* registers like d_mode, memory like b_mode. */ |
| db_mode, |
| /* registers like d_mode, memory like w_mode. */ |
| dw_mode, |
| /* registers like dq_mode, memory like d_mode. */ |
| dqd_mode, |
| /* normal vex mode */ |
| vex_mode, |
| /* 128bit vex mode */ |
| vex128_mode, |
| /* 256bit vex mode */ |
| vex256_mode, |
| /* operand size depends on the VEX.W bit. */ |
| vex_w_dq_mode, |
| |
| /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
| vex_vsib_d_w_dq_mode, |
| /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
| vex_vsib_d_w_d_mode, |
| /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
| vex_vsib_q_w_dq_mode, |
| /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
| vex_vsib_q_w_d_mode, |
| |
| /* scalar, ignore vector length. */ |
| scalar_mode, |
| /* like d_mode, ignore vector length. */ |
| d_scalar_mode, |
| /* like d_swap_mode, ignore vector length. */ |
| d_scalar_swap_mode, |
| /* like q_mode, ignore vector length. */ |
| q_scalar_mode, |
| /* like q_swap_mode, ignore vector length. */ |
| q_scalar_swap_mode, |
| /* like vex_mode, ignore vector length. */ |
| vex_scalar_mode, |
| /* like vex_w_dq_mode, ignore vector length. */ |
| vex_scalar_w_dq_mode, |
| |
| /* Static rounding. */ |
| evex_rounding_mode, |
| /* Supress all exceptions. */ |
| evex_sae_mode, |
| |
| /* Mask register operand. */ |
| mask_mode, |
| /* Mask register operand. */ |
| mask_bd_mode, |
| |
| es_reg, |
| cs_reg, |
| ss_reg, |
| ds_reg, |
| fs_reg, |
| gs_reg, |
| |
| eAX_reg, |
| eCX_reg, |
| eDX_reg, |
| eBX_reg, |
| eSP_reg, |
| eBP_reg, |
| eSI_reg, |
| eDI_reg, |
| |
| al_reg, |
| cl_reg, |
| dl_reg, |
| bl_reg, |
| ah_reg, |
| ch_reg, |
| dh_reg, |
| bh_reg, |
| |
| ax_reg, |
| cx_reg, |
| dx_reg, |
| bx_reg, |
| sp_reg, |
| bp_reg, |
| si_reg, |
| di_reg, |
| |
| rAX_reg, |
| rCX_reg, |
| rDX_reg, |
| rBX_reg, |
| rSP_reg, |
| rBP_reg, |
| rSI_reg, |
| rDI_reg, |
| |
| z_mode_ax_reg, |
| indir_dx_reg |
| }; |
| |
| enum |
| { |
| FLOATCODE = 1, |
| USE_REG_TABLE, |
| USE_MOD_TABLE, |
| USE_RM_TABLE, |
| USE_PREFIX_TABLE, |
| USE_X86_64_TABLE, |
| USE_3BYTE_TABLE, |
| USE_XOP_8F_TABLE, |
| USE_VEX_C4_TABLE, |
| USE_VEX_C5_TABLE, |
| USE_VEX_LEN_TABLE, |
| USE_VEX_W_TABLE, |
| USE_EVEX_TABLE |
| }; |
| |
| #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
| |
| #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
| #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P |
| #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
| #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) |
| #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) |
| #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) |
| #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
| #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) |
| #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
| #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
| #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
| #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) |
| #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) |
| #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
| #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
| |
| enum |
| { |
| REG_80 = 0, |
| REG_81, |
| REG_83, |
| REG_8F, |
| REG_C0, |
| REG_C1, |
| REG_C6, |
| REG_C7, |
| REG_D0, |
| REG_D1, |
| REG_D2, |
| REG_D3, |
| REG_F6, |
| REG_F7, |
| REG_FE, |
| REG_FF, |
| REG_0F00, |
| REG_0F01, |
| REG_0F0D, |
| REG_0F18, |
| REG_0F71, |
| REG_0F72, |
| REG_0F73, |
| REG_0FA6, |
| REG_0FA7, |
| REG_0FAE, |
| REG_0FBA, |
| REG_0FC7, |
| REG_VEX_0F71, |
| REG_VEX_0F72, |
| REG_VEX_0F73, |
| REG_VEX_0FAE, |
| REG_VEX_0F38F3, |
| REG_XOP_LWPCB, |
| REG_XOP_LWP, |
| REG_XOP_TBM_01, |
| REG_XOP_TBM_02, |
| |
| REG_EVEX_0F71, |
| REG_EVEX_0F72, |
| REG_EVEX_0F73, |
| REG_EVEX_0F38C6, |
| REG_EVEX_0F38C7 |
| }; |
| |
| enum |
| { |
| MOD_8D = 0, |
| MOD_C6_REG_7, |
| MOD_C7_REG_7, |
| MOD_FF_REG_3, |
| MOD_FF_REG_5, |
| MOD_0F01_REG_0, |
| MOD_0F01_REG_1, |
| MOD_0F01_REG_2, |
| MOD_0F01_REG_3, |
| MOD_0F01_REG_5, |
| MOD_0F01_REG_7, |
| MOD_0F12_PREFIX_0, |
| MOD_0F13, |
| MOD_0F16_PREFIX_0, |
| MOD_0F17, |
| MOD_0F18_REG_0, |
| MOD_0F18_REG_1, |
| MOD_0F18_REG_2, |
| MOD_0F18_REG_3, |
| MOD_0F18_REG_4, |
| MOD_0F18_REG_5, |
| MOD_0F18_REG_6, |
| MOD_0F18_REG_7, |
| MOD_0F1A_PREFIX_0, |
| MOD_0F1B_PREFIX_0, |
| MOD_0F1B_PREFIX_1, |
| MOD_0F24, |
| MOD_0F26, |
| MOD_0F2B_PREFIX_0, |
| MOD_0F2B_PREFIX_1, |
| MOD_0F2B_PREFIX_2, |
| MOD_0F2B_PREFIX_3, |
| MOD_0F51, |
| MOD_0F71_REG_2, |
| MOD_0F71_REG_4, |
| MOD_0F71_REG_6, |
| MOD_0F72_REG_2, |
| MOD_0F72_REG_4, |
| MOD_0F72_REG_6, |
| MOD_0F73_REG_2, |
| MOD_0F73_REG_3, |
| MOD_0F73_REG_6, |
| MOD_0F73_REG_7, |
| MOD_0FAE_REG_0, |
| MOD_0FAE_REG_1, |
| MOD_0FAE_REG_2, |
| MOD_0FAE_REG_3, |
| MOD_0FAE_REG_4, |
| MOD_0FAE_REG_5, |
| MOD_0FAE_REG_6, |
| MOD_0FAE_REG_7, |
| MOD_0FB2, |
| MOD_0FB4, |
| MOD_0FB5, |
| MOD_0FC3, |
| MOD_0FC7_REG_3, |
| MOD_0FC7_REG_4, |
| MOD_0FC7_REG_5, |
| MOD_0FC7_REG_6, |
| MOD_0FC7_REG_7, |
| MOD_0FD7, |
| MOD_0FE7_PREFIX_2, |
| MOD_0FF0_PREFIX_3, |
| MOD_0F382A_PREFIX_2, |
| MOD_62_32BIT, |
| MOD_C4_32BIT, |
| MOD_C5_32BIT, |
| MOD_VEX_0F12_PREFIX_0, |
| MOD_VEX_0F13, |
| MOD_VEX_0F16_PREFIX_0, |
| MOD_VEX_0F17, |
| MOD_VEX_0F2B, |
| MOD_VEX_W_0_0F41_P_0_LEN_1, |
| MOD_VEX_W_1_0F41_P_0_LEN_1, |
| MOD_VEX_W_0_0F41_P_2_LEN_1, |
| MOD_VEX_W_1_0F41_P_2_LEN_1, |
| MOD_VEX_W_0_0F42_P_0_LEN_1, |
| MOD_VEX_W_1_0F42_P_0_LEN_1, |
| MOD_VEX_W_0_0F42_P_2_LEN_1, |
| MOD_VEX_W_1_0F42_P_2_LEN_1, |
| MOD_VEX_W_0_0F44_P_0_LEN_1, |
| MOD_VEX_W_1_0F44_P_0_LEN_1, |
| MOD_VEX_W_0_0F44_P_2_LEN_1, |
| MOD_VEX_W_1_0F44_P_2_LEN_1, |
| MOD_VEX_W_0_0F45_P_0_LEN_1, |
| MOD_VEX_W_1_0F45_P_0_LEN_1, |
| MOD_VEX_W_0_0F45_P_2_LEN_1, |
| MOD_VEX_W_1_0F45_P_2_LEN_1, |
| MOD_VEX_W_0_0F46_P_0_LEN_1, |
| MOD_VEX_W_1_0F46_P_0_LEN_1, |
| MOD_VEX_W_0_0F46_P_2_LEN_1, |
| MOD_VEX_W_1_0F46_P_2_LEN_1, |
| MOD_VEX_W_0_0F47_P_0_LEN_1, |
| MOD_VEX_W_1_0F47_P_0_LEN_1, |
| MOD_VEX_W_0_0F47_P_2_LEN_1, |
| MOD_VEX_W_1_0F47_P_2_LEN_1, |
| MOD_VEX_W_0_0F4A_P_0_LEN_1, |
| MOD_VEX_W_1_0F4A_P_0_LEN_1, |
| MOD_VEX_W_0_0F4A_P_2_LEN_1, |
| MOD_VEX_W_1_0F4A_P_2_LEN_1, |
| MOD_VEX_W_0_0F4B_P_0_LEN_1, |
| MOD_VEX_W_1_0F4B_P_0_LEN_1, |
| MOD_VEX_W_0_0F4B_P_2_LEN_1, |
| MOD_VEX_0F50, |
| MOD_VEX_0F71_REG_2, |
| MOD_VEX_0F71_REG_4, |
| MOD_VEX_0F71_REG_6, |
| MOD_VEX_0F72_REG_2, |
| MOD_VEX_0F72_REG_4, |
| MOD_VEX_0F72_REG_6, |
| MOD_VEX_0F73_REG_2, |
| MOD_VEX_0F73_REG_3, |
| MOD_VEX_0F73_REG_6, |
| MOD_VEX_0F73_REG_7, |
| MOD_VEX_W_0_0F91_P_0_LEN_0, |
| MOD_VEX_W_1_0F91_P_0_LEN_0, |
| MOD_VEX_W_0_0F91_P_2_LEN_0, |
| MOD_VEX_W_1_0F91_P_2_LEN_0, |
| MOD_VEX_W_0_0F92_P_0_LEN_0, |
| MOD_VEX_W_0_0F92_P_2_LEN_0, |
| MOD_VEX_W_0_0F92_P_3_LEN_0, |
| MOD_VEX_W_1_0F92_P_3_LEN_0, |
| MOD_VEX_W_0_0F93_P_0_LEN_0, |
| MOD_VEX_W_0_0F93_P_2_LEN_0, |
| MOD_VEX_W_0_0F93_P_3_LEN_0, |
| MOD_VEX_W_1_0F93_P_3_LEN_0, |
| MOD_VEX_W_0_0F98_P_0_LEN_0, |
| MOD_VEX_W_1_0F98_P_0_LEN_0, |
| MOD_VEX_W_0_0F98_P_2_LEN_0, |
| MOD_VEX_W_1_0F98_P_2_LEN_0, |
| MOD_VEX_W_0_0F99_P_0_LEN_0, |
| MOD_VEX_W_1_0F99_P_0_LEN_0, |
| MOD_VEX_W_0_0F99_P_2_LEN_0, |
| MOD_VEX_W_1_0F99_P_2_LEN_0, |
| MOD_VEX_0FAE_REG_2, |
| MOD_VEX_0FAE_REG_3, |
| MOD_VEX_0FD7_PREFIX_2, |
| MOD_VEX_0FE7_PREFIX_2, |
| MOD_VEX_0FF0_PREFIX_3, |
| MOD_VEX_0F381A_PREFIX_2, |
| MOD_VEX_0F382A_PREFIX_2, |
| MOD_VEX_0F382C_PREFIX_2, |
| MOD_VEX_0F382D_PREFIX_2, |
| MOD_VEX_0F382E_PREFIX_2, |
| MOD_VEX_0F382F_PREFIX_2, |
| MOD_VEX_0F385A_PREFIX_2, |
| MOD_VEX_0F388C_PREFIX_2, |
| MOD_VEX_0F388E_PREFIX_2, |
| MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
| MOD_VEX_W_1_0F3A30_P_2_LEN_0, |
| MOD_VEX_W_0_0F3A31_P_2_LEN_0, |
| MOD_VEX_W_1_0F3A31_P_2_LEN_0, |
| MOD_VEX_W_0_0F3A32_P_2_LEN_0, |
| MOD_VEX_W_1_0F3A32_P_2_LEN_0, |
| MOD_VEX_W_0_0F3A33_P_2_LEN_0, |
| MOD_VEX_W_1_0F3A33_P_2_LEN_0, |
| |
| MOD_EVEX_0F10_PREFIX_1, |
| MOD_EVEX_0F10_PREFIX_3, |
| MOD_EVEX_0F11_PREFIX_1, |
| MOD_EVEX_0F11_PREFIX_3, |
| MOD_EVEX_0F12_PREFIX_0, |
| MOD_EVEX_0F16_PREFIX_0, |
| MOD_EVEX_0F38C6_REG_1, |
| MOD_EVEX_0F38C6_REG_2, |
| MOD_EVEX_0F38C6_REG_5, |
| MOD_EVEX_0F38C6_REG_6, |
| MOD_EVEX_0F38C7_REG_1, |
| MOD_EVEX_0F38C7_REG_2, |
| MOD_EVEX_0F38C7_REG_5, |
| MOD_EVEX_0F38C7_REG_6 |
| }; |
| |
| enum |
| { |
| RM_C6_REG_7 = 0, |
| RM_C7_REG_7, |
| RM_0F01_REG_0, |
| RM_0F01_REG_1, |
| RM_0F01_REG_2, |
| RM_0F01_REG_3, |
| RM_0F01_REG_5, |
| RM_0F01_REG_7, |
| RM_0FAE_REG_5, |
| RM_0FAE_REG_6, |
| RM_0FAE_REG_7 |
| }; |
| |
| enum |
| { |
| PREFIX_90 = 0, |
| PREFIX_0F10, |
| PREFIX_0F11, |
| PREFIX_0F12, |
| PREFIX_0F16, |
| PREFIX_0F1A, |
| PREFIX_0F1B, |
| PREFIX_0F2A, |
| PREFIX_0F2B, |
| PREFIX_0F2C, |
| PREFIX_0F2D, |
| PREFIX_0F2E, |
| PREFIX_0F2F, |
| PREFIX_0F51, |
| PREFIX_0F52, |
| PREFIX_0F53, |
| PREFIX_0F58, |
| PREFIX_0F59, |
| PREFIX_0F5A, |
| PREFIX_0F5B, |
| PREFIX_0F5C, |
| PREFIX_0F5D, |
| PREFIX_0F5E, |
| PREFIX_0F5F, |
| PREFIX_0F60, |
| PREFIX_0F61, |
| PREFIX_0F62, |
| PREFIX_0F6C, |
| PREFIX_0F6D, |
| PREFIX_0F6F, |
| PREFIX_0F70, |
| PREFIX_0F73_REG_3, |
| PREFIX_0F73_REG_7, |
| PREFIX_0F78, |
| PREFIX_0F79, |
| PREFIX_0F7C, |
| PREFIX_0F7D, |
| PREFIX_0F7E, |
| PREFIX_0F7F, |
| PREFIX_0FAE_REG_0, |
| PREFIX_0FAE_REG_1, |
| PREFIX_0FAE_REG_2, |
| PREFIX_0FAE_REG_3, |
| PREFIX_MOD_0_0FAE_REG_4, |
| PREFIX_MOD_3_0FAE_REG_4, |
| PREFIX_0FAE_REG_6, |
| PREFIX_0FAE_REG_7, |
| PREFIX_0FB8, |
| PREFIX_0FBC, |
| PREFIX_0FBD, |
| PREFIX_0FC2, |
| PREFIX_MOD_0_0FC3, |
| PREFIX_MOD_0_0FC7_REG_6, |
| PREFIX_MOD_3_0FC7_REG_6, |
| PREFIX_MOD_3_0FC7_REG_7, |
| PREFIX_0FD0, |
| PREFIX_0FD6, |
| PREFIX_0FE6, |
| PREFIX_0FE7, |
| PREFIX_0FF0, |
| PREFIX_0FF7, |
| PREFIX_0F3810, |
| PREFIX_0F3814, |
| PREFIX_0F3815, |
| PREFIX_0F3817, |
| PREFIX_0F3820, |
| PREFIX_0F3821, |
| PREFIX_0F3822, |
| PREFIX_0F3823, |
| PREFIX_0F3824, |
| PREFIX_0F3825, |
| PREFIX_0F3828, |
| PREFIX_0F3829, |
| PREFIX_0F382A, |
| PREFIX_0F382B, |
| PREFIX_0F3830, |
| PREFIX_0F3831, |
| PREFIX_0F3832, |
| PREFIX_0F3833, |
| PREFIX_0F3834, |
| PREFIX_0F3835, |
| PREFIX_0F3837, |
| PREFIX_0F3838, |
| PREFIX_0F3839, |
| PREFIX_0F383A, |
| PREFIX_0F383B, |
| PREFIX_0F383C, |
| PREFIX_0F383D, |
| PREFIX_0F383E, |
| PREFIX_0F383F, |
| PREFIX_0F3840, |
| PREFIX_0F3841, |
| PREFIX_0F3880, |
| PREFIX_0F3881, |
| PREFIX_0F3882, |
| PREFIX_0F38C8, |
| PREFIX_0F38C9, |
| PREFIX_0F38CA, |
| PREFIX_0F38CB, |
| PREFIX_0F38CC, |
| PREFIX_0F38CD, |
| PREFIX_0F38DB, |
| PREFIX_0F38DC, |
| PREFIX_0F38DD, |
| PREFIX_0F38DE, |
| PREFIX_0F38DF, |
| PREFIX_0F38F0, |
| PREFIX_0F38F1, |
| PREFIX_0F38F6, |
| PREFIX_0F3A08, |
| PREFIX_0F3A09, |
| PREFIX_0F3A0A, |
| PREFIX_0F3A0B, |
| PREFIX_0F3A0C, |
| PREFIX_0F3A0D, |
| PREFIX_0F3A0E, |
| PREFIX_0F3A14, |
| PREFIX_0F3A15, |
| PREFIX_0F3A16, |
| PREFIX_0F3A17, |
| PREFIX_0F3A20, |
| PREFIX_0F3A21, |
| PREFIX_0F3A22, |
| PREFIX_0F3A40, |
| PREFIX_0F3A41, |
| PREFIX_0F3A42, |
| PREFIX_0F3A44, |
| PREFIX_0F3A60, |
| PREFIX_0F3A61, |
| PREFIX_0F3A62, |
| PREFIX_0F3A63, |
| PREFIX_0F3ACC, |
| PREFIX_0F3ADF, |
| PREFIX_VEX_0F10, |
| PREFIX_VEX_0F11, |
| PREFIX_VEX_0F12, |
| PREFIX_VEX_0F16, |
| PREFIX_VEX_0F2A, |
| PREFIX_VEX_0F2C, |
| PREFIX_VEX_0F2D, |
| PREFIX_VEX_0F2E, |
| PREFIX_VEX_0F2F, |
| PREFIX_VEX_0F41, |
| PREFIX_VEX_0F42, |
| PREFIX_VEX_0F44, |
| PREFIX_VEX_0F45, |
| PREFIX_VEX_0F46, |
| PREFIX_VEX_0F47, |
| PREFIX_VEX_0F4A, |
| PREFIX_VEX_0F4B, |
| PREFIX_VEX_0F51, |
| PREFIX_VEX_0F52, |
| PREFIX_VEX_0F53, |
| PREFIX_VEX_0F58, |
| PREFIX_VEX_0F59, |
| PREFIX_VEX_0F5A, |
| PREFIX_VEX_0F5B, |
| PREFIX_VEX_0F5C, |
| PREFIX_VEX_0F5D, |
| PREFIX_VEX_0F5E, |
| PREFIX_VEX_0F5F, |
| PREFIX_VEX_0F60, |
| PREFIX_VEX_0F61, |
| PREFIX_VEX_0F62, |
| PREFIX_VEX_0F63, |
| PREFIX_VEX_0F64, |
| PREFIX_VEX_0F65, |
| PREFIX_VEX_0F66, |
| PREFIX_VEX_0F67, |
| PREFIX_VEX_0F68, |
| PREFIX_VEX_0F69, |
| PREFIX_VEX_0F6A, |
| PREFIX_VEX_0F6B, |
| PREFIX_VEX_0F6C, |
| PREFIX_VEX_0F6D, |
| PREFIX_VEX_0F6E, |
| PREFIX_VEX_0F6F, |
| PREFIX_VEX_0F70, |
| PREFIX_VEX_0F71_REG_2, |
| PREFIX_VEX_0F71_REG_4, |
| PREFIX_VEX_0F71_REG_6, |
| PREFIX_VEX_0F72_REG_2, |
| PREFIX_VEX_0F72_REG_4, |
| PREFIX_VEX_0F72_REG_6, |
| PREFIX_VEX_0F73_REG_2, |
| PREFIX_VEX_0F73_REG_3, |
| PREFIX_VEX_0F73_REG_6, |
| PREFIX_VEX_0F73_REG_7, |
| PREFIX_VEX_0F74, |
| PREFIX_VEX_0F75, |
| PREFIX_VEX_0F76, |
| PREFIX_VEX_0F77, |
| PREFIX_VEX_0F7C, |
| PREFIX_VEX_0F7D, |
| PREFIX_VEX_0F7E, |
| PREFIX_VEX_0F7F, |
| PREFIX_VEX_0F90, |
| PREFIX_VEX_0F91, |
| PREFIX_VEX_0F92, |
| PREFIX_VEX_0F93, |
| PREFIX_VEX_0F98, |
| PREFIX_VEX_0F99, |
| PREFIX_VEX_0FC2, |
| PREFIX_VEX_0FC4, |
| PREFIX_VEX_0FC5, |
| PREFIX_VEX_0FD0, |
| PREFIX_VEX_0FD1, |
| PREFIX_VEX_0FD2, |
| PREFIX_VEX_0FD3, |
| PREFIX_VEX_0FD4, |
| PREFIX_VEX_0FD5, |
| PREFIX_VEX_0FD6, |
| PREFIX_VEX_0FD7, |
| PREFIX_VEX_0FD8, |
| PREFIX_VEX_0FD9, |
| PREFIX_VEX_0FDA, |
| PREFIX_VEX_0FDB, |
| PREFIX_VEX_0FDC, |
| PREFIX_VEX_0FDD, |
| PREFIX_VEX_0FDE, |
| PREFIX_VEX_0FDF, |
| PREFIX_VEX_0FE0, |
| PREFIX_VEX_0FE1, |
| PREFIX_VEX_0FE2, |
| PREFIX_VEX_0FE3, |
| PREFIX_VEX_0FE4, |
| PREFIX_VEX_0FE5, |
| PREFIX_VEX_0FE6, |
| PREFIX_VEX_0FE7, |
| PREFIX_VEX_0FE8, |
| PREFIX_VEX_0FE9, |
| PREFIX_VEX_0FEA, |
| PREFIX_VEX_0FEB, |
| PREFIX_VEX_0FEC, |
| PREFIX_VEX_0FED, |
| PREFIX_VEX_0FEE, |
| PREFIX_VEX_0FEF, |
| PREFIX_VEX_0FF0, |
| PREFIX_VEX_0FF1, |
| PREFIX_VEX_0FF2, |
| PREFIX_VEX_0FF3, |
| PREFIX_VEX_0FF4, |
| PREFIX_VEX_0FF5, |
| PREFIX_VEX_0FF6, |
| PREFIX_VEX_0FF7, |
| PREFIX_VEX_0FF8, |
| PREFIX_VEX_0FF9, |
| PREFIX_VEX_0FFA, |
| PREFIX_VEX_0FFB, |
| PREFIX_VEX_0FFC, |
| PREFIX_VEX_0FFD, |
| PREFIX_VEX_0FFE, |
| PREFIX_VEX_0F3800, |
| PREFIX_VEX_0F3801, |
| PREFIX_VEX_0F3802, |
| PREFIX_VEX_0F3803, |
| PREFIX_VEX_0F3804, |
| PREFIX_VEX_0F3805, |
| PREFIX_VEX_0F3806, |
| PREFIX_VEX_0F3807, |
| PREFIX_VEX_0F3808, |
| PREFIX_VEX_0F3809, |
| PREFIX_VEX_0F380A, |
| PREFIX_VEX_0F380B, |
| PREFIX_VEX_0F380C, |
| PREFIX_VEX_0F380D, |
| PREFIX_VEX_0F380E, |
| PREFIX_VEX_0F380F, |
| PREFIX_VEX_0F3813, |
| PREFIX_VEX_0F3816, |
| PREFIX_VEX_0F3817, |
| PREFIX_VEX_0F3818, |
| PREFIX_VEX_0F3819, |
| PREFIX_VEX_0F381A, |
| PREFIX_VEX_0F381C, |
| PREFIX_VEX_0F381D, |
| PREFIX_VEX_0F381E, |
| PREFIX_VEX_0F3820, |
| PREFIX_VEX_0F3821, |
| PREFIX_VEX_0F3822, |
| PREFIX_VEX_0F3823, |
| PREFIX_VEX_0F3824, |
| PREFIX_VEX_0F3825, |
| PREFIX_VEX_0F3828, |
| PREFIX_VEX_0F3829, |
| PREFIX_VEX_0F382A, |
| PREFIX_VEX_0F382B, |
| PREFIX_VEX_0F382C, |
| PREFIX_VEX_0F382D, |
| PREFIX_VEX_0F382E, |
| PREFIX_VEX_0F382F, |
| PREFIX_VEX_0F3830, |
| PREFIX_VEX_0F3831, |
| PREFIX_VEX_0F3832, |
| PREFIX_VEX_0F3833, |
| PREFIX_VEX_0F3834, |
| PREFIX_VEX_0F3835, |
| PREFIX_VEX_0F3836, |
| PREFIX_VEX_0F3837, |
| PREFIX_VEX_0F3838, |
| PREFIX_VEX_0F3839, |
| PREFIX_VEX_0F383A, |
| PREFIX_VEX_0F383B, |
| PREFIX_VEX_0F383C, |
| PREFIX_VEX_0F383D, |
| PREFIX_VEX_0F383E, |
| PREFIX_VEX_0F383F, |
| PREFIX_VEX_0F3840, |
| PREFIX_VEX_0F3841, |
| PREFIX_VEX_0F3845, |
| PREFIX_VEX_0F3846, |
| PREFIX_VEX_0F3847, |
| PREFIX_VEX_0F3858, |
| PREFIX_VEX_0F3859, |
| PREFIX_VEX_0F385A, |
| PREFIX_VEX_0F3878, |
| PREFIX_VEX_0F3879, |
| PREFIX_VEX_0F388C, |
| PREFIX_VEX_0F388E, |
| PREFIX_VEX_0F3890, |
| PREFIX_VEX_0F3891, |
| PREFIX_VEX_0F3892, |
| PREFIX_VEX_0F3893, |
| PREFIX_VEX_0F3896, |
| PREFIX_VEX_0F3897, |
| PREFIX_VEX_0F3898, |
| PREFIX_VEX_0F3899, |
| PREFIX_VEX_0F389A, |
| PREFIX_VEX_0F389B, |
| PREFIX_VEX_0F389C, |
| PREFIX_VEX_0F389D, |
| PREFIX_VEX_0F389E, |
| PREFIX_VEX_0F389F, |
| PREFIX_VEX_0F38A6, |
| PREFIX_VEX_0F38A7, |
| PREFIX_VEX_0F38A8, |
| PREFIX_VEX_0F38A9, |
| PREFIX_VEX_0F38AA, |
| PREFIX_VEX_0F38AB, |
| PREFIX_VEX_0F38AC, |
| PREFIX_VEX_0F38AD, |
| PREFIX_VEX_0F38AE, |
| PREFIX_VEX_0F38AF, |
| PREFIX_VEX_0F38B6, |
| PREFIX_VEX_0F38B7, |
| PREFIX_VEX_0F38B8, |
| PREFIX_VEX_0F38B9, |
| PREFIX_VEX_0F38BA, |
| PREFIX_VEX_0F38BB, |
| PREFIX_VEX_0F38BC, |
| PREFIX_VEX_0F38BD, |
| PREFIX_VEX_0F38BE, |
| PREFIX_VEX_0F38BF, |
| PREFIX_VEX_0F38DB, |
| PREFIX_VEX_0F38DC, |
| PREFIX_VEX_0F38DD, |
| PREFIX_VEX_0F38DE, |
| PREFIX_VEX_0F38DF, |
| PREFIX_VEX_0F38F2, |
| PREFIX_VEX_0F38F3_REG_1, |
| PREFIX_VEX_0F38F3_REG_2, |
| PREFIX_VEX_0F38F3_REG_3, |
| PREFIX_VEX_0F38F5, |
| PREFIX_VEX_0F38F6, |
| PREFIX_VEX_0F38F7, |
| PREFIX_VEX_0F3A00, |
| PREFIX_VEX_0F3A01, |
| PREFIX_VEX_0F3A02, |
| PREFIX_VEX_0F3A04, |
| PREFIX_VEX_0F3A05, |
| PREFIX_VEX_0F3A06, |
| PREFIX_VEX_0F3A08, |
| PREFIX_VEX_0F3A09, |
| PREFIX_VEX_0F3A0A, |
| PREFIX_VEX_0F3A0B, |
| PREFIX_VEX_0F3A0C, |
| PREFIX_VEX_0F3A0D, |
| PREFIX_VEX_0F3A0E, |
| PREFIX_VEX_0F3A0F, |
| PREFIX_VEX_0F3A14, |
| PREFIX_VEX_0F3A15, |
| PREFIX_VEX_0F3A16, |
| PREFIX_VEX_0F3A17, |
| PREFIX_VEX_0F3A18, |
| PREFIX_VEX_0F3A19, |
| PREFIX_VEX_0F3A1D, |
| PREFIX_VEX_0F3A20, |
| PREFIX_VEX_0F3A21, |
| PREFIX_VEX_0F3A22, |
| PREFIX_VEX_0F3A30, |
| PREFIX_VEX_0F3A31, |
| PREFIX_VEX_0F3A32, |
| PREFIX_VEX_0F3A33, |
| PREFIX_VEX_0F3A38, |
| PREFIX_VEX_0F3A39, |
| PREFIX_VEX_0F3A40, |
| PREFIX_VEX_0F3A41, |
| PREFIX_VEX_0F3A42, |
| PREFIX_VEX_0F3A44, |
| PREFIX_VEX_0F3A46, |
| PREFIX_VEX_0F3A48, |
| PREFIX_VEX_0F3A49, |
| PREFIX_VEX_0F3A4A, |
| PREFIX_VEX_0F3A4B, |
| PREFIX_VEX_0F3A4C, |
| PREFIX_VEX_0F3A5C, |
| PREFIX_VEX_0F3A5D, |
| PREFIX_VEX_0F3A5E, |
| PREFIX_VEX_0F3A5F, |
| PREFIX_VEX_0F3A60, |
| PREFIX_VEX_0F3A61, |
| PREFIX_VEX_0F3A62, |
| PREFIX_VEX_0F3A63, |
| PREFIX_VEX_0F3A68, |
| PREFIX_VEX_0F3A69, |
| PREFIX_VEX_0F3A6A, |
| PREFIX_VEX_0F3A6B, |
| PREFIX_VEX_0F3A6C, |
| PREFIX_VEX_0F3A6D, |
| PREFIX_VEX_0F3A6E, |
| PREFIX_VEX_0F3A6F, |
| PREFIX_VEX_0F3A78, |
| PREFIX_VEX_0F3A79, |
| PREFIX_VEX_0F3A7A, |
| PREFIX_VEX_0F3A7B, |
| PREFIX_VEX_0F3A7C, |
| PREFIX_VEX_0F3A7D, |
| PREFIX_VEX_0F3A7E, |
| PREFIX_VEX_0F3A7F, |
| PREFIX_VEX_0F3ADF, |
| PREFIX_VEX_0F3AF0, |
| |
| PREFIX_EVEX_0F10, |
| PREFIX_EVEX_0F11, |
| PREFIX_EVEX_0F12, |
| PREFIX_EVEX_0F13, |
| PREFIX_EVEX_0F14, |
| PREFIX_EVEX_0F15, |
| PREFIX_EVEX_0F16, |
| PREFIX_EVEX_0F17, |
| PREFIX_EVEX_0F28, |
| PREFIX_EVEX_0F29, |
| PREFIX_EVEX_0F2A, |
| PREFIX_EVEX_0F2B, |
| PREFIX_EVEX_0F2C, |
| PREFIX_EVEX_0F2D, |
| PREFIX_EVEX_0F2E, |
| PREFIX_EVEX_0F2F, |
| PREFIX_EVEX_0F51, |
| PREFIX_EVEX_0F54, |
| PREFIX_EVEX_0F55, |
| PREFIX_EVEX_0F56, |
| PREFIX_EVEX_0F57, |
| PREFIX_EVEX_0F58, |
| PREFIX_EVEX_0F59, |
| PREFIX_EVEX_0F5A, |
| PREFIX_EVEX_0F5B, |
| PREFIX_EVEX_0F5C, |
| PREFIX_EVEX_0F5D, |
| PREFIX_EVEX_0F5E, |
| PREFIX_EVEX_0F5F, |
| PREFIX_EVEX_0F60, |
| PREFIX_EVEX_0F61, |
| PREFIX_EVEX_0F62, |
| PREFIX_EVEX_0F63, |
| PREFIX_EVEX_0F64, |
| PREFIX_EVEX_0F65, |
| PREFIX_EVEX_0F66, |
| PREFIX_EVEX_0F67, |
| PREFIX_EVEX_0F68, |
| PREFIX_EVEX_0F69, |
| PREFIX_EVEX_0F6A, |
| PREFIX_EVEX_0F6B, |
| PREFIX_EVEX_0F6C, |
| PREFIX_EVEX_0F6D, |
| PREFIX_EVEX_0F6E, |
| PREFIX_EVEX_0F6F, |
| PREFIX_EVEX_0F70, |
| PREFIX_EVEX_0F71_REG_2, |
| PREFIX_EVEX_0F71_REG_4, |
| PREFIX_EVEX_0F71_REG_6, |
| PREFIX_EVEX_0F72_REG_0, |
| PREFIX_EVEX_0F72_REG_1, |
| PREFIX_EVEX_0F72_REG_2, |
| PREFIX_EVEX_0F72_REG_4, |
| PREFIX_EVEX_0F72_REG_6, |
| PREFIX_EVEX_0F73_REG_2, |
| PREFIX_EVEX_0F73_REG_3, |
| PREFIX_EVEX_0F73_REG_6, |
| PREFIX_EVEX_0F73_REG_7, |
| PREFIX_EVEX_0F74, |
| PREFIX_EVEX_0F75, |
| PREFIX_EVEX_0F76, |
| PREFIX_EVEX_0F78, |
| PREFIX_EVEX_0F79, |
| PREFIX_EVEX_0F7A, |
| PREFIX_EVEX_0F7B, |
| PREFIX_EVEX_0F7E, |
| PREFIX_EVEX_0F7F, |
| PREFIX_EVEX_0FC2, |
| PREFIX_EVEX_0FC4, |
| PREFIX_EVEX_0FC5, |
| PREFIX_EVEX_0FC6, |
| PREFIX_EVEX_0FD1, |
| PREFIX_EVEX_0FD2, |
| PREFIX_EVEX_0FD3, |
| PREFIX_EVEX_0FD4, |
| PREFIX_EVEX_0FD5, |
| PREFIX_EVEX_0FD6, |
| PREFIX_EVEX_0FD8, |
| PREFIX_EVEX_0FD9, |
| PREFIX_EVEX_0FDA, |
| PREFIX_EVEX_0FDB, |
| PREFIX_EVEX_0FDC, |
| PREFIX_EVEX_0FDD, |
| PREFIX_EVEX_0FDE, |
| PREFIX_EVEX_0FDF, |
| PREFIX_EVEX_0FE0, |
| PREFIX_EVEX_0FE1, |
| PREFIX_EVEX_0FE2, |
| PREFIX_EVEX_0FE3, |
| PREFIX_EVEX_0FE4, |
| PREFIX_EVEX_0FE5, |
| PREFIX_EVEX_0FE6, |
| PREFIX_EVEX_0FE7, |
| PREFIX_EVEX_0FE8, |
| PREFIX_EVEX_0FE9, |
| PREFIX_EVEX_0FEA, |
| PREFIX_EVEX_0FEB, |
| PREFIX_EVEX_0FEC, |
| PREFIX_EVEX_0FED, |
| PREFIX_EVEX_0FEE, |
| PREFIX_EVEX_0FEF, |
| PREFIX_EVEX_0FF1, |
| PREFIX_EVEX_0FF2, |
| PREFIX_EVEX_0FF3, |
| PREFIX_EVEX_0FF4, |
| PREFIX_EVEX_0FF5, |
| PREFIX_EVEX_0FF6, |
| PREFIX_EVEX_0FF8, |
| PREFIX_EVEX_0FF9, |
| PREFIX_EVEX_0FFA, |
| PREFIX_EVEX_0FFB, |
| PREFIX_EVEX_0FFC, |
| PREFIX_EVEX_0FFD, |
| PREFIX_EVEX_0FFE, |
| PREFIX_EVEX_0F3800, |
| PREFIX_EVEX_0F3804, |
| PREFIX_EVEX_0F380B, |
| PREFIX_EVEX_0F380C, |
| PREFIX_EVEX_0F380D, |
| PREFIX_EVEX_0F3810, |
| PREFIX_EVEX_0F3811, |
| PREFIX_EVEX_0F3812, |
| PREFIX_EVEX_0F3813, |
| PREFIX_EVEX_0F3814, |
| PREFIX_EVEX_0F3815, |
| PREFIX_EVEX_0F3816, |
| PREFIX_EVEX_0F3818, |
| PREFIX_EVEX_0F3819, |
| PREFIX_EVEX_0F381A, |
| PREFIX_EVEX_0F381B, |
| PREFIX_EVEX_0F381C, |
| PREFIX_EVEX_0F381D, |
| PREFIX_EVEX_0F381E, |
| PREFIX_EVEX_0F381F, |
| PREFIX_EVEX_0F3820, |
| PREFIX_EVEX_0F3821, |
| PREFIX_EVEX_0F3822, |
| PREFIX_EVEX_0F3823, |
| PREFIX_EVEX_0F3824, |
| PREFIX_EVEX_0F3825, |
| PREFIX_EVEX_0F3826, |
| PREFIX_EVEX_0F3827, |
| PREFIX_EVEX_0F3828, |
| PREFIX_EVEX_0F3829, |
| PREFIX_EVEX_0F382A, |
| PREFIX_EVEX_0F382B, |
| PREFIX_EVEX_0F382C, |
| PREFIX_EVEX_0F382D, |
| PREFIX_EVEX_0F3830, |
| PREFIX_EVEX_0F3831, |
| PREFIX_EVEX_0F3832, |
| PREFIX_EVEX_0F3833, |
| PREFIX_EVEX_0F3834, |
| PREFIX_EVEX_0F3835, |
| PREFIX_EVEX_0F3836, |
| PREFIX_EVEX_0F3837, |
| PREFIX_EVEX_0F3838, |
| PREFIX_EVEX_0F3839, |
| PREFIX_EVEX_0F383A, |
| PREFIX_EVEX_0F383B, |
| PREFIX_EVEX_0F383C, |
| PREFIX_EVEX_0F383D, |
| PREFIX_EVEX_0F383E, |
| PREFIX_EVEX_0F383F, |
| PREFIX_EVEX_0F3840, |
| PREFIX_EVEX_0F3842, |
| PREFIX_EVEX_0F3843, |
| PREFIX_EVEX_0F3844, |
| PREFIX_EVEX_0F3845, |
| PREFIX_EVEX_0F3846, |
| PREFIX_EVEX_0F3847, |
| PREFIX_EVEX_0F384C, |
| PREFIX_EVEX_0F384D, |
| PREFIX_EVEX_0F384E, |
| PREFIX_EVEX_0F384F, |
| PREFIX_EVEX_0F3852, |
| PREFIX_EVEX_0F3853, |
| PREFIX_EVEX_0F3858, |
| PREFIX_EVEX_0F3859, |
| PREFIX_EVEX_0F385A, |
| PREFIX_EVEX_0F385B, |
| PREFIX_EVEX_0F3864, |
| PREFIX_EVEX_0F3865, |
| PREFIX_EVEX_0F3866, |
| PREFIX_EVEX_0F3875, |
| PREFIX_EVEX_0F3876, |
| PREFIX_EVEX_0F3877, |
| PREFIX_EVEX_0F3878, |
| PREFIX_EVEX_0F3879, |
| PREFIX_EVEX_0F387A, |
| PREFIX_EVEX_0F387B, |
| PREFIX_EVEX_0F387C, |
| PREFIX_EVEX_0F387D, |
| PREFIX_EVEX_0F387E, |
| PREFIX_EVEX_0F387F, |
| PREFIX_EVEX_0F3883, |
| PREFIX_EVEX_0F3888, |
| PREFIX_EVEX_0F3889, |
| PREFIX_EVEX_0F388A, |
| PREFIX_EVEX_0F388B, |
| PREFIX_EVEX_0F388D, |
| PREFIX_EVEX_0F3890, |
| PREFIX_EVEX_0F3891, |
| PREFIX_EVEX_0F3892, |
| PREFIX_EVEX_0F3893, |
| PREFIX_EVEX_0F3896, |
| PREFIX_EVEX_0F3897, |
| PREFIX_EVEX_0F3898, |
| PREFIX_EVEX_0F3899, |
| PREFIX_EVEX_0F389A, |
| PREFIX_EVEX_0F389B, |
| PREFIX_EVEX_0F389C, |
| PREFIX_EVEX_0F389D, |
| PREFIX_EVEX_0F389E, |
| PREFIX_EVEX_0F389F, |
| PREFIX_EVEX_0F38A0, |
| PREFIX_EVEX_0F38A1, |
| PREFIX_EVEX_0F38A2, |
| PREFIX_EVEX_0F38A3, |
| PREFIX_EVEX_0F38A6, |
| PREFIX_EVEX_0F38A7, |
| PREFIX_EVEX_0F38A8, |
| PREFIX_EVEX_0F38A9, |
| PREFIX_EVEX_0F38AA, |
| PREFIX_EVEX_0F38AB, |
| PREFIX_EVEX_0F38AC, |
| PREFIX_EVEX_0F38AD, |
| PREFIX_EVEX_0F38AE, |
| PREFIX_EVEX_0F38AF, |
| PREFIX_EVEX_0F38B4, |
| PREFIX_EVEX_0F38B5, |
| PREFIX_EVEX_0F38B6, |
| PREFIX_EVEX_0F38B7, |
| PREFIX_EVEX_0F38B8, |
| PREFIX_EVEX_0F38B9, |
| PREFIX_EVEX_0F38BA, |
| PREFIX_EVEX_0F38BB, |
| PREFIX_EVEX_0F38BC, |
| PREFIX_EVEX_0F38BD, |
| PREFIX_EVEX_0F38BE, |
| PREFIX_EVEX_0F38BF, |
| PREFIX_EVEX_0F38C4, |
| PREFIX_EVEX_0F38C6_REG_1, |
| PREFIX_EVEX_0F38C6_REG_2, |
| PREFIX_EVEX_0F38C6_REG_5, |
| PREFIX_EVEX_0F38C6_REG_6, |
| PREFIX_EVEX_0F38C7_REG_1, |
| PREFIX_EVEX_0F38C7_REG_2, |
| PREFIX_EVEX_0F38C7_REG_5, |
| PREFIX_EVEX_0F38C7_REG_6, |
| PREFIX_EVEX_0F38C8, |
| PREFIX_EVEX_0F38CA, |
| PREFIX_EVEX_0F38CB, |
| PREFIX_EVEX_0F38CC, |
| PREFIX_EVEX_0F38CD, |
| |
| PREFIX_EVEX_0F3A00, |
| PREFIX_EVEX_0F3A01, |
| PREFIX_EVEX_0F3A03, |
| PREFIX_EVEX_0F3A04, |
| PREFIX_EVEX_0F3A05, |
| PREFIX_EVEX_0F3A08, |
| PREFIX_EVEX_0F3A09, |
| PREFIX_EVEX_0F3A0A, |
| PREFIX_EVEX_0F3A0B, |
| PREFIX_EVEX_0F3A0F, |
| PREFIX_EVEX_0F3A14, |
| PREFIX_EVEX_0F3A15, |
| PREFIX_EVEX_0F3A16, |
| PREFIX_EVEX_0F3A17, |
| PREFIX_EVEX_0F3A18, |
| PREFIX_EVEX_0F3A19, |
| PREFIX_EVEX_0F3A1A, |
| PREFIX_EVEX_0F3A1B, |
| PREFIX_EVEX_0F3A1D, |
| PREFIX_EVEX_0F3A1E, |
| PREFIX_EVEX_0F3A1F, |
| PREFIX_EVEX_0F3A20, |
| PREFIX_EVEX_0F3A21, |
| PREFIX_EVEX_0F3A22, |
| PREFIX_EVEX_0F3A23, |
| PREFIX_EVEX_0F3A25, |
| PREFIX_EVEX_0F3A26, |
| PREFIX_EVEX_0F3A27, |
| PREFIX_EVEX_0F3A38, |
| PREFIX_EVEX_0F3A39, |
| PREFIX_EVEX_0F3A3A, |
| PREFIX_EVEX_0F3A3B, |
| PREFIX_EVEX_0F3A3E, |
| PREFIX_EVEX_0F3A3F, |
| PREFIX_EVEX_0F3A42, |
| PREFIX_EVEX_0F3A43, |
| PREFIX_EVEX_0F3A50, |
| PREFIX_EVEX_0F3A51, |
| PREFIX_EVEX_0F3A54, |
| PREFIX_EVEX_0F3A55, |
| PREFIX_EVEX_0F3A56, |
| PREFIX_EVEX_0F3A57, |
| PREFIX_EVEX_0F3A66, |
| PREFIX_EVEX_0F3A67 |
| }; |
| |
| enum |
| { |
| X86_64_06 = 0, |
| X86_64_07, |
| X86_64_0D, |
| X86_64_16, |
| X86_64_17, |
| X86_64_1E, |
| X86_64_1F, |
| X86_64_27, |
| X86_64_2F, |
| X86_64_37, |
| X86_64_3F, |
| X86_64_60, |
| X86_64_61, |
| X86_64_62, |
| X86_64_63, |
| X86_64_6D, |
| X86_64_6F, |
| X86_64_82, |
| X86_64_9A, |
| X86_64_C4, |
| X86_64_C5, |
| X86_64_CE, |
| X86_64_D4, |
| X86_64_D5, |
| X86_64_E8, |
| X86_64_E9, |
| X86_64_EA, |
| X86_64_0F01_REG_0, |
| X86_64_0F01_REG_1, |
| X86_64_0F01_REG_2, |
| X86_64_0F01_REG_3 |
| }; |
| |
| enum |
| { |
| THREE_BYTE_0F38 = 0, |
| THREE_BYTE_0F3A |
| }; |
| |
| enum |
| { |
| XOP_08 = 0, |
| XOP_09, |
| XOP_0A |
| }; |
| |
| enum |
| { |
| VEX_0F = 0, |
| VEX_0F38, |
| VEX_0F3A |
| }; |
| |
| enum |
| { |
| EVEX_0F = 0, |
| EVEX_0F38, |
| EVEX_0F3A |
| }; |
| |
| enum |
| { |
| VEX_LEN_0F10_P_1 = 0, |
| VEX_LEN_0F10_P_3, |
| VEX_LEN_0F11_P_1, |
| VEX_LEN_0F11_P_3, |
| VEX_LEN_0F12_P_0_M_0, |
| VEX_LEN_0F12_P_0_M_1, |
| VEX_LEN_0F12_P_2, |
| VEX_LEN_0F13_M_0, |
| VEX_LEN_0F16_P_0_M_0, |
| VEX_LEN_0F16_P_0_M_1, |
| VEX_LEN_0F16_P_2, |
| VEX_LEN_0F17_M_0, |
| VEX_LEN_0F2A_P_1, |
| VEX_LEN_0F2A_P_3, |
| VEX_LEN_0F2C_P_1, |
| VEX_LEN_0F2C_P_3, |
| VEX_LEN_0F2D_P_1, |
| VEX_LEN_0F2D_P_3, |
| VEX_LEN_0F2E_P_0, |
| VEX_LEN_0F2E_P_2, |
| VEX_LEN_0F2F_P_0, |
| VEX_LEN_0F2F_P_2, |
| VEX_LEN_0F41_P_0, |
| VEX_LEN_0F41_P_2, |
| VEX_LEN_0F42_P_0, |
| VEX_LEN_0F42_P_2, |
| VEX_LEN_0F44_P_0, |
| VEX_LEN_0F44_P_2, |
| VEX_LEN_0F45_P_0, |
| VEX_LEN_0F45_P_2, |
| VEX_LEN_0F46_P_0, |
| VEX_LEN_0F46_P_2, |
| VEX_LEN_0F47_P_0, |
| VEX_LEN_0F47_P_2, |
| VEX_LEN_0F4A_P_0, |
| VEX_LEN_0F4A_P_2, |
| VEX_LEN_0F4B_P_0, |
| VEX_LEN_0F4B_P_2, |
| VEX_LEN_0F51_P_1, |
| VEX_LEN_0F51_P_3, |
| VEX_LEN_0F52_P_1, |
| VEX_LEN_0F53_P_1, |
| VEX_LEN_0F58_P_1, |
| VEX_LEN_0F58_P_3, |
| VEX_LEN_0F59_P_1, |
| VEX_LEN_0F59_P_3, |
| VEX_LEN_0F5A_P_1, |
| VEX_LEN_0F5A_P_3, |
| VEX_LEN_0F5C_P_1, |
| VEX_LEN_0F5C_P_3, |
| VEX_LEN_0F5D_P_1, |
| VEX_LEN_0F5D_P_3, |
| VEX_LEN_0F5E_P_1, |
| VEX_LEN_0F5E_P_3, |
| VEX_LEN_0F5F_P_1, |
| VEX_LEN_0F5F_P_3, |
| VEX_LEN_0F6E_P_2, |
| VEX_LEN_0F7E_P_1, |
| VEX_LEN_0F7E_P_2, |
| VEX_LEN_0F90_P_0, |
| VEX_LEN_0F90_P_2, |
| VEX_LEN_0F91_P_0, |
| VEX_LEN_0F91_P_2, |
| VEX_LEN_0F92_P_0, |
| VEX_LEN_0F92_P_2, |
| VEX_LEN_0F92_P_3, |
| VEX_LEN_0F93_P_0, |
| VEX_LEN_0F93_P_2, |
| VEX_LEN_0F93_P_3, |
| VEX_LEN_0F98_P_0, |
| VEX_LEN_0F98_P_2, |
| VEX_LEN_0F99_P_0, |
| VEX_LEN_0F99_P_2, |
| VEX_LEN_0FAE_R_2_M_0, |
| VEX_LEN_0FAE_R_3_M_0, |
| VEX_LEN_0FC2_P_1, |
| VEX_LEN_0FC2_P_3, |
| VEX_LEN_0FC4_P_2, |
| VEX_LEN_0FC5_P_2, |
| VEX_LEN_0FD6_P_2, |
| VEX_LEN_0FF7_P_2, |
| VEX_LEN_0F3816_P_2, |
| VEX_LEN_0F3819_P_2, |
| VEX_LEN_0F381A_P_2_M_0, |
| VEX_LEN_0F3836_P_2, |
| VEX_LEN_0F3841_P_2, |
| VEX_LEN_0F385A_P_2_M_0, |
| VEX_LEN_0F38DB_P_2, |
| VEX_LEN_0F38DC_P_2, |
| VEX_LEN_0F38DD_P_2, |
| VEX_LEN_0F38DE_P_2, |
| VEX_LEN_0F38DF_P_2, |
| VEX_LEN_0F38F2_P_0, |
| VEX_LEN_0F38F3_R_1_P_0, |
| VEX_LEN_0F38F3_R_2_P_0, |
| VEX_LEN_0F38F3_R_3_P_0, |
| VEX_LEN_0F38F5_P_0, |
| VEX_LEN_0F38F5_P_1, |
| VEX_LEN_0F38F5_P_3, |
| VEX_LEN_0F38F6_P_3, |
| VEX_LEN_0F38F7_P_0, |
| VEX_LEN_0F38F7_P_1, |
| VEX_LEN_0F38F7_P_2, |
| VEX_LEN_0F38F7_P_3, |
| VEX_LEN_0F3A00_P_2, |
| VEX_LEN_0F3A01_P_2, |
| VEX_LEN_0F3A06_P_2, |
| VEX_LEN_0F3A0A_P_2, |
| VEX_LEN_0F3A0B_P_2, |
| VEX_LEN_0F3A14_P_2, |
| VEX_LEN_0F3A15_P_2, |
| VEX_LEN_0F3A16_P_2, |
| VEX_LEN_0F3A17_P_2, |
| VEX_LEN_0F3A18_P_2, |
| VEX_LEN_0F3A19_P_2, |
| VEX_LEN_0F3A20_P_2, |
| VEX_LEN_0F3A21_P_2, |
| VEX_LEN_0F3A22_P_2, |
| VEX_LEN_0F3A30_P_2, |
| VEX_LEN_0F3A31_P_2, |
| VEX_LEN_0F3A32_P_2, |
| VEX_LEN_0F3A33_P_2, |
| VEX_LEN_0F3A38_P_2, |
| VEX_LEN_0F3A39_P_2, |
| VEX_LEN_0F3A41_P_2, |
| VEX_LEN_0F3A44_P_2, |
| VEX_LEN_0F3A46_P_2, |
| VEX_LEN_0F3A60_P_2, |
| VEX_LEN_0F3A61_P_2, |
| VEX_LEN_0F3A62_P_2, |
| VEX_LEN_0F3A63_P_2, |
| VEX_LEN_0F3A6A_P_2, |
| VEX_LEN_0F3A6B_P_2, |
| VEX_LEN_0F3A6E_P_2, |
| VEX_LEN_0F3A6F_P_2, |
| VEX_LEN_0F3A7A_P_2, |
| VEX_LEN_0F3A7B_P_2, |
| VEX_LEN_0F3A7E_P_2, |
| VEX_LEN_0F3A7F_P_2, |
| VEX_LEN_0F3ADF_P_2, |
| VEX_LEN_0F3AF0_P_3, |
| VEX_LEN_0FXOP_08_CC, |
| VEX_LEN_0FXOP_08_CD, |
| VEX_LEN_0FXOP_08_CE, |
| VEX_LEN_0FXOP_08_CF, |
| VEX_LEN_0FXOP_08_EC, |
| VEX_LEN_0FXOP_08_ED, |
| VEX_LEN_0FXOP_08_EE, |
| VEX_LEN_0FXOP_08_EF, |
| VEX_LEN_0FXOP_09_80, |
| VEX_LEN_0FXOP_09_81 |
| }; |
| |
| enum |
| { |
| VEX_W_0F10_P_0 = 0, |
| VEX_W_0F10_P_1, |
| VEX_W_0F10_P_2, |
| VEX_W_0F10_P_3, |
| VEX_W_0F11_P_0, |
| VEX_W_0F11_P_1, |
| VEX_W_0F11_P_2, |
| VEX_W_0F11_P_3, |
| VEX_W_0F12_P_0_M_0, |
| VEX_W_0F12_P_0_M_1, |
| VEX_W_0F12_P_1, |
| VEX_W_0F12_P_2, |
| VEX_W_0F12_P_3, |
| VEX_W_0F13_M_0, |
| VEX_W_0F14, |
| VEX_W_0F15, |
| VEX_W_0F16_P_0_M_0, |
| VEX_W_0F16_P_0_M_1, |
| VEX_W_0F16_P_1, |
| VEX_W_0F16_P_2, |
| VEX_W_0F17_M_0, |
| VEX_W_0F28, |
| VEX_W_0F29, |
| VEX_W_0F2B_M_0, |
| VEX_W_0F2E_P_0, |
| VEX_W_0F2E_P_2, |
| VEX_W_0F2F_P_0, |
| VEX_W_0F2F_P_2, |
| VEX_W_0F41_P_0_LEN_1, |
| VEX_W_0F41_P_2_LEN_1, |
| VEX_W_0F42_P_0_LEN_1, |
| VEX_W_0F42_P_2_LEN_1, |
| VEX_W_0F44_P_0_LEN_0, |
| VEX_W_0F44_P_2_LEN_0, |
| VEX_W_0F45_P_0_LEN_1, |
| VEX_W_0F45_P_2_LEN_1, |
| VEX_W_0F46_P_0_LEN_1, |
| VEX_W_0F46_P_2_LEN_1, |
| VEX_W_0F47_P_0_LEN_1, |
| VEX_W_0F47_P_2_LEN_1, |
| VEX_W_0F4A_P_0_LEN_1, |
| VEX_W_0F4A_P_2_LEN_1, |
| VEX_W_0F4B_P_0_LEN_1, |
| VEX_W_0F4B_P_2_LEN_1, |
| VEX_W_0F50_M_0, |
| VEX_W_0F51_P_0, |
| VEX_W_0F51_P_1, |
| VEX_W_0F51_P_2, |
| VEX_W_0F51_P_3, |
| VEX_W_0F52_P_0, |
| VEX_W_0F52_P_1, |
| VEX_W_0F53_P_0, |
| VEX_W_0F53_P_1, |
| VEX_W_0F58_P_0, |
| VEX_W_0F58_P_1, |
| VEX_W_0F58_P_2, |
| VEX_W_0F58_P_3, |
| VEX_W_0F59_P_0, |
| VEX_W_0F59_P_1, |
| VEX_W_0F59_P_2, |
| VEX_W_0F59_P_3, |
| VEX_W_0F5A_P_0, |
| VEX_W_0F5A_P_1, |
| VEX_W_0F5A_P_3, |
| VEX_W_0F5B_P_0, |
| VEX_W_0F5B_P_1, |
| VEX_W_0F5B_P_2, |
| VEX_W_0F5C_P_0, |
| VEX_W_0F5C_P_1, |
| VEX_W_0F5C_P_2, |
| VEX_W_0F5C_P_3, |
| VEX_W_0F5D_P_0, |
| VEX_W_0F5D_P_1, |
| VEX_W_0F5D_P_2, |
| VEX_W_0F5D_P_3, |
| VEX_W_0F5E_P_0, |
| VEX_W_0F5E_P_1, |
| VEX_W_0F5E_P_2, |
| VEX_W_0F5E_P_3, |
| VEX_W_0F5F_P_0, |
| VEX_W_0F5F_P_1, |
| VEX_W_0F5F_P_2, |
| VEX_W_0F5F_P_3, |
| VEX_W_0F60_P_2, |
| VEX_W_0F61_P_2, |
| VEX_W_0F62_P_2, |
| VEX_W_0F63_P_2, |
| VEX_W_0F64_P_2, |
| VEX_W_0F65_P_2, |
| VEX_W_0F66_P_2, |
| VEX_W_0F67_P_2, |
| VEX_W_0F68_P_2, |
| VEX_W_0F69_P_2, |
| VEX_W_0F6A_P_2, |
| VEX_W_0F6B_P_2, |
| VEX_W_0F6C_P_2, |
| VEX_W_0F6D_P_2, |
| VEX_W_0F6F_P_1, |
| VEX_W_0F6F_P_2, |
| VEX_W_0F70_P_1, |
| VEX_W_0F70_P_2, |
| VEX_W_0F70_P_3, |
| VEX_W_0F71_R_2_P_2, |
| VEX_W_0F71_R_4_P_2, |
| VEX_W_0F71_R_6_P_2, |
| VEX_W_0F72_R_2_P_2, |
| VEX_W_0F72_R_4_P_2, |
| VEX_W_0F72_R_6_P_2, |
| VEX_W_0F73_R_2_P_2, |
| VEX_W_0F73_R_3_P_2, |
| VEX_W_0F73_R_6_P_2, |
| VEX_W_0F73_R_7_P_2, |
| VEX_W_0F74_P_2, |
| VEX_W_0F75_P_2, |
| VEX_W_0F76_P_2, |
| VEX_W_0F77_P_0, |
| VEX_W_0F7C_P_2, |
| VEX_W_0F7C_P_3, |
| VEX_W_0F7D_P_2, |
| VEX_W_0F7D_P_3, |
| VEX_W_0F7E_P_1, |
| VEX_W_0F7F_P_1, |
| VEX_W_0F7F_P_2, |
| VEX_W_0F90_P_0_LEN_0, |
| VEX_W_0F90_P_2_LEN_0, |
| VEX_W_0F91_P_0_LEN_0, |
| VEX_W_0F91_P_2_LEN_0, |
| VEX_W_0F92_P_0_LEN_0, |
| VEX_W_0F92_P_2_LEN_0, |
| VEX_W_0F92_P_3_LEN_0, |
| VEX_W_0F93_P_0_LEN_0, |
| VEX_W_0F93_P_2_LEN_0, |
| VEX_W_0F93_P_3_LEN_0, |
| VEX_W_0F98_P_0_LEN_0, |
| VEX_W_0F98_P_2_LEN_0, |
| VEX_W_0F99_P_0_LEN_0, |
| VEX_W_0F99_P_2_LEN_0, |
| VEX_W_0FAE_R_2_M_0, |
| VEX_W_0FAE_R_3_M_0, |
| VEX_W_0FC2_P_0, |
| VEX_W_0FC2_P_1, |
| VEX_W_0FC2_P_2, |
| VEX_W_0FC2_P_3, |
| VEX_W_0FC4_P_2, |
| VEX_W_0FC5_P_2, |
| VEX_W_0FD0_P_2, |
| VEX_W_0FD0_P_3, |
| VEX_W_0FD1_P_2, |
| VEX_W_0FD2_P_2, |
| VEX_W_0FD3_P_2, |
| VEX_W_0FD4_P_2, |
| VEX_W_0FD5_P_2, |
| VEX_W_0FD6_P_2, |
| VEX_W_0FD7_P_2_M_1, |
| VEX_W_0FD8_P_2, |
| VEX_W_0FD9_P_2, |
| VEX_W_0FDA_P_2, |
| VEX_W_0FDB_P_2, |
| VEX_W_0FDC_P_2, |
| VEX_W_0FDD_P_2, |
| VEX_W_0FDE_P_2, |
| VEX_W_0FDF_P_2, |
| VEX_W_0FE0_P_2, |
| VEX_W_0FE1_P_2, |
| VEX_W_0FE2_P_2, |
| VEX_W_0FE3_P_2, |
| VEX_W_0FE4_P_2, |
| VEX_W_0FE5_P_2, |
| VEX_W_0FE6_P_1, |
| VEX_W_0FE6_P_2, |
| VEX_W_0FE6_P_3, |
| VEX_W_0FE7_P_2_M_0, |
| VEX_W_0FE8_P_2, |
| VEX_W_0FE9_P_2, |
| VEX_W_0FEA_P_2, |
| VEX_W_0FEB_P_2, |
| VEX_W_0FEC_P_2, |
| VEX_W_0FED_P_2, |
| VEX_W_0FEE_P_2, |
| VEX_W_0FEF_P_2, |
| VEX_W_0FF0_P_3_M_0, |
| VEX_W_0FF1_P_2, |
| VEX_W_0FF2_P_2, |
| VEX_W_0FF3_P_2, |
| VEX_W_0FF4_P_2, |
| VEX_W_0FF5_P_2, |
| VEX_W_0FF6_P_2, |
| VEX_W_0FF7_P_2, |
| VEX_W_0FF8_P_2, |
| VEX_W_0FF9_P_2, |
| VEX_W_0FFA_P_2, |
| VEX_W_0FFB_P_2, |
| VEX_W_0FFC_P_2, |
| VEX_W_0FFD_P_2, |
| VEX_W_0FFE_P_2, |
| VEX_W_0F3800_P_2, |
| VEX_W_0F3801_P_2, |
| VEX_W_0F3802_P_2, |
| VEX_W_0F3803_P_2, |
| VEX_W_0F3804_P_2, |
| VEX_W_0F3805_P_2, |
| VEX_W_0F3806_P_2, |
| VEX_W_0F3807_P_2, |
| VEX_W_0F3808_P_2, |
| VEX_W_0F3809_P_2, |
| VEX_W_0F380A_P_2, |
| VEX_W_0F380B_P_2, |
| VEX_W_0F380C_P_2, |
| VEX_W_0F380D_P_2, |
| VEX_W_0F380E_P_2, |
| VEX_W_0F380F_P_2, |
| VEX_W_0F3816_P_2, |
| VEX_W_0F3817_P_2, |
| VEX_W_0F3818_P_2, |
| VEX_W_0F3819_P_2, |
| VEX_W_0F381A_P_2_M_0, |
| VEX_W_0F381C_P_2, |
| VEX_W_0F381D_P_2, |
| VEX_W_0F381E_P_2, |
| VEX_W_0F3820_P_2, |
| VEX_W_0F3821_P_2, |
| VEX_W_0F3822_P_2, |
| VEX_W_0F3823_P_2, |
| VEX_W_0F3824_P_2, |
| VEX_W_0F3825_P_2, |
| VEX_W_0F3828_P_2, |
| VEX_W_0F3829_P_2, |
| VEX_W_0F382A_P_2_M_0, |
| VEX_W_0F382B_P_2, |
| VEX_W_0F382C_P_2_M_0, |
| VEX_W_0F382D_P_2_M_0, |
| VEX_W_0F382E_P_2_M_0, |
| VEX_W_0F382F_P_2_M_0, |
| VEX_W_0F3830_P_2, |
| VEX_W_0F3831_P_2, |
| VEX_W_0F3832_P_2, |
| VEX_W_0F3833_P_2, |
| VEX_W_0F3834_P_2, |
| VEX_W_0F3835_P_2, |
| VEX_W_0F3836_P_2, |
| VEX_W_0F3837_P_2, |
| VEX_W_0F3838_P_2, |
| VEX_W_0F3839_P_2, |
| VEX_W_0F383A_P_2, |
| VEX_W_0F383B_P_2, |
| VEX_W_0F383C_P_2, |
| VEX_W_0F383D_P_2, |
| VEX_W_0F383E_P_2, |
| VEX_W_0F383F_P_2, |
| VEX_W_0F3840_P_2, |
| VEX_W_0F3841_P_2, |
| VEX_W_0F3846_P_2, |
| VEX_W_0F3858_P_2, |
| VEX_W_0F3859_P_2, |
| VEX_W_0F385A_P_2_M_0, |
| VEX_W_0F3878_P_2, |
| VEX_W_0F3879_P_2, |
| VEX_W_0F38DB_P_2, |
| VEX_W_0F38DC_P_2, |
| VEX_W_0F38DD_P_2, |
| VEX_W_0F38DE_P_2, |
| VEX_W_0F38DF_P_2, |
| VEX_W_0F3A00_P_2, |
| VEX_W_0F3A01_P_2, |
| VEX_W_0F3A02_P_2, |
| VEX_W_0F3A04_P_2, |
| VEX_W_0F3A05_P_2, |
| VEX_W_0F3A06_P_2, |
| VEX_W_0F3A08_P_2, |
| VEX_W_0F3A09_P_2, |
| VEX_W_0F3A0A_P_2, |
| VEX_W_0F3A0B_P_2, |
| VEX_W_0F3A0C_P_2, |
| VEX_W_0F3A0D_P_2, |
| VEX_W_0F3A0E_P_2, |
| VEX_W_0F3A0F_P_2, |
| VEX_W_0F3A14_P_2, |
| VEX_W_0F3A15_P_2, |
| VEX_W_0F3A18_P_2, |
| VEX_W_0F3A19_P_2, |
| VEX_W_0F3A20_P_2, |
| VEX_W_0F3A21_P_2, |
| VEX_W_0F3A30_P_2_LEN_0, |
| VEX_W_0F3A31_P_2_LEN_0, |
| VEX_W_0F3A32_P_2_LEN_0, |
| VEX_W_0F3A33_P_2_LEN_0, |
| VEX_W_0F3A38_P_2, |
| VEX_W_0F3A39_P_2, |
| VEX_W_0F3A40_P_2, |
| VEX_W_0F3A41_P_2, |
| VEX_W_0F3A42_P_2, |
| VEX_W_0F3A44_P_2, |
| VEX_W_0F3A46_P_2, |
| VEX_W_0F3A48_P_2, |
| VEX_W_0F3A49_P_2, |
| VEX_W_0F3A4A_P_2, |
| VEX_W_0F3A4B_P_2, |
| VEX_W_0F3A4C_P_2, |
| VEX_W_0F3A60_P_2, |
| VEX_W_0F3A61_P_2, |
| VEX_W_0F3A62_P_2, |
| VEX_W_0F3A63_P_2, |
| VEX_W_0F3ADF_P_2, |
| |
| EVEX_W_0F10_P_0, |
| EVEX_W_0F10_P_1_M_0, |
| EVEX_W_0F10_P_1_M_1, |
| EVEX_W_0F10_P_2, |
| EVEX_W_0F10_P_3_M_0, |
| EVEX_W_0F10_P_3_M_1, |
| EVEX_W_0F11_P_0, |
| EVEX_W_0F11_P_1_M_0, |
| EVEX_W_0F11_P_1_M_1, |
| EVEX_W_0F11_P_2, |
| EVEX_W_0F11_P_3_M_0, |
| EVEX_W_0F11_P_3_M_1, |
| EVEX_W_0F12_P_0_M_0, |
| EVEX_W_0F12_P_0_M_1, |
| EVEX_W_0F12_P_1, |
| EVEX_W_0F12_P_2, |
| EVEX_W_0F12_P_3, |
| EVEX_W_0F13_P_0, |
| EVEX_W_0F13_P_2, |
| EVEX_W_0F14_P_0, |
| EVEX_W_0F14_P_2, |
| EVEX_W_0F15_P_0, |
| EVEX_W_0F15_P_2, |
| EVEX_W_0F16_P_0_M_0, |
| EVEX_W_0F16_P_0_M_1, |
| EVEX_W_0F16_P_1, |
| EVEX_W_0F16_P_2, |
| EVEX_W_0F17_P_0, |
| EVEX_W_0F17_P_2, |
| EVEX_W_0F28_P_0, |
| EVEX_W_0F28_P_2, |
| EVEX_W_0F29_P_0, |
| EVEX_W_0F29_P_2, |
| EVEX_W_0F2A_P_1, |
| EVEX_W_0F2A_P_3, |
| EVEX_W_0F2B_P_0, |
| EVEX_W_0F2B_P_2, |
| EVEX_W_0F2E_P_0, |
| EVEX_W_0F2E_P_2, |
| EVEX_W_0F2F_P_0, |
| EVEX_W_0F2F_P_2, |
| EVEX_W_0F51_P_0, |
| EVEX_W_0F51_P_1, |
| EVEX_W_0F51_P_2, |
| EVEX_W_0F51_P_3, |
| EVEX_W_0F54_P_0, |
| EVEX_W_0F54_P_2, |
| EVEX_W_0F55_P_0, |
| EVEX_W_0F55_P_2, |
| EVEX_W_0F56_P_0, |
| EVEX_W_0F56_P_2, |
| EVEX_W_0F57_P_0, |
| EVEX_W_0F57_P_2, |
| EVEX_W_0F58_P_0, |
| EVEX_W_0F58_P_1, |
| EVEX_W_0F58_P_2, |
| EVEX_W_0F58_P_3, |
| EVEX_W_0F59_P_0, |
| EVEX_W_0F59_P_1, |
| EVEX_W_0F59_P_2, |
| EVEX_W_0F59_P_3, |
| EVEX_W_0F5A_P_0, |
| EVEX_W_0F5A_P_1, |
| EVEX_W_0F5A_P_2, |
| EVEX_W_0F5A_P_3, |
| EVEX_W_0F5B_P_0, |
| EVEX_W_0F5B_P_1, |
| EVEX_W_0F5B_P_2, |
| EVEX_W_0F5C_P_0, |
| EVEX_W_0F5C_P_1, |
| EVEX_W_0F5C_P_2, |
| EVEX_W_0F5C_P_3, |
| EVEX_W_0F5D_P_0, |
| EVEX_W_0F5D_P_1, |
| EVEX_W_0F5D_P_2, |
| EVEX_W_0F5D_P_3, |
| EVEX_W_0F5E_P_0, |
| EVEX_W_0F5E_P_1, |
| EVEX_W_0F5E_P_2, |
| EVEX_W_0F5E_P_3, |
| EVEX_W_0F5F_P_0, |
| EVEX_W_0F5F_P_1, |
| EVEX_W_0F5F_P_2, |
| EVEX_W_0F5F_P_3, |
| EVEX_W_0F62_P_2, |
| EVEX_W_0F66_P_2, |
| EVEX_W_0F6A_P_2, |
| EVEX_W_0F6B_P_2, |
| EVEX_W_0F6C_P_2, |
| EVEX_W_0F6D_P_2, |
| EVEX_W_0F6E_P_2, |
| EVEX_W_0F6F_P_1, |
| EVEX_W_0F6F_P_2, |
| EVEX_W_0F6F_P_3, |
| EVEX_W_0F70_P_2, |
| EVEX_W_0F72_R_2_P_2, |
| EVEX_W_0F72_R_6_P_2, |
| EVEX_W_0F73_R_2_P_2, |
| EVEX_W_0F73_R_6_P_2, |
| EVEX_W_0F76_P_2, |
| EVEX_W_0F78_P_0, |
| EVEX_W_0F78_P_2, |
| EVEX_W_0F79_P_0, |
| EVEX_W_0F79_P_2, |
| EVEX_W_0F7A_P_1, |
| EVEX_W_0F7A_P_2, |
| EVEX_W_0F7A_P_3, |
| EVEX_W_0F7B_P_1, |
| EVEX_W_0F7B_P_2, |
| EVEX_W_0F7B_P_3, |
| EVEX_W_0F7E_P_1, |
| EVEX_W_0F7E_P_2, |
| EVEX_W_0F7F_P_1, |
| EVEX_W_0F7F_P_2, |
| EVEX_W_0F7F_P_3, |
| EVEX_W_0FC2_P_0, |
| EVEX_W_0FC2_P_1, |
| EVEX_W_0FC2_P_2, |
| EVEX_W_0FC2_P_3, |
| EVEX_W_0FC6_P_0, |
| EVEX_W_0FC6_P_2, |
| EVEX_W_0FD2_P_2, |
| EVEX_W_0FD3_P_2, |
| EVEX_W_0FD4_P_2, |
| EVEX_W_0FD6_P_2, |
| EVEX_W_0FE6_P_1, |
| EVEX_W_0FE6_P_2, |
| EVEX_W_0FE6_P_3, |
| EVEX_W_0FE7_P_2, |
| EVEX_W_0FF2_P_2, |
| EVEX_W_0FF3_P_2, |
| EVEX_W_0FF4_P_2, |
| EVEX_W_0FFA_P_2, |
| EVEX_W_0FFB_P_2, |
| EVEX_W_0FFE_P_2, |
| EVEX_W_0F380C_P_2, |
| EVEX_W_0F380D_P_2, |
| EVEX_W_0F3810_P_1, |
| EVEX_W_0F3810_P_2, |
| EVEX_W_0F3811_P_1, |
| EVEX_W_0F3811_P_2, |
| EVEX_W_0F3812_P_1, |
| EVEX_W_0F3812_P_2, |
| EVEX_W_0F3813_P_1, |
| EVEX_W_0F3813_P_2, |
| EVEX_W_0F3814_P_1, |
| EVEX_W_0F3815_P_1, |
| EVEX_W_0F3818_P_2, |
| EVEX_W_0F3819_P_2, |
| EVEX_W_0F381A_P_2, |
| EVEX_W_0F381B_P_2, |
| EVEX_W_0F381E_P_2, |
| EVEX_W_0F381F_P_2, |
| EVEX_W_0F3820_P_1, |
| EVEX_W_0F3821_P_1, |
| EVEX_W_0F3822_P_1, |
| EVEX_W_0F3823_P_1, |
| EVEX_W_0F3824_P_1, |
| EVEX_W_0F3825_P_1, |
| EVEX_W_0F3825_P_2, |
| EVEX_W_0F3826_P_1, |
| EVEX_W_0F3826_P_2, |
| EVEX_W_0F3828_P_1, |
| EVEX_W_0F3828_P_2, |
| EVEX_W_0F3829_P_1, |
| EVEX_W_0F3829_P_2, |
| EVEX_W_0F382A_P_1, |
| EVEX_W_0F382A_P_2, |
| EVEX_W_0F382B_P_2, |
| EVEX_W_0F3830_P_1, |
| EVEX_W_0F3831_P_1, |
| EVEX_W_0F3832_P_1, |
| EVEX_W_0F3833_P_1, |
| EVEX_W_0F3834_P_1, |
| EVEX_W_0F3835_P_1, |
| EVEX_W_0F3835_P_2, |
| EVEX_W_0F3837_P_2, |
| EVEX_W_0F3838_P_1, |
| EVEX_W_0F3839_P_1, |
| EVEX_W_0F383A_P_1, |
| EVEX_W_0F3840_P_2, |
| EVEX_W_0F3858_P_2, |
| EVEX_W_0F3859_P_2, |
| EVEX_W_0F385A_P_2, |
| EVEX_W_0F385B_P_2, |
| EVEX_W_0F3866_P_2, |
| EVEX_W_0F3875_P_2, |
| EVEX_W_0F3878_P_2, |
| EVEX_W_0F3879_P_2, |
| EVEX_W_0F387A_P_2, |
| EVEX_W_0F387B_P_2, |
| EVEX_W_0F387D_P_2, |
| EVEX_W_0F3883_P_2, |
| EVEX_W_0F388D_P_2, |
| EVEX_W_0F3891_P_2, |
| EVEX_W_0F3893_P_2, |
| EVEX_W_0F38A1_P_2, |
| EVEX_W_0F38A3_P_2, |
| EVEX_W_0F38C7_R_1_P_2, |
| EVEX_W_0F38C7_R_2_P_2, |
| EVEX_W_0F38C7_R_5_P_2, |
| EVEX_W_0F38C7_R_6_P_2, |
| |
| EVEX_W_0F3A00_P_2, |
| EVEX_W_0F3A01_P_2, |
| EVEX_W_0F3A04_P_2, |
| EVEX_W_0F3A05_P_2, |
| EVEX_W_0F3A08_P_2, |
| EVEX_W_0F3A09_P_2, |
| EVEX_W_0F3A0A_P_2, |
| EVEX_W_0F3A0B_P_2, |
| EVEX_W_0F3A16_P_2, |
| EVEX_W_0F3A18_P_2, |
| EVEX_W_0F3A19_P_2, |
| EVEX_W_0F3A1A_P_2, |
| EVEX_W_0F3A1B_P_2, |
| EVEX_W_0F3A1D_P_2, |
| EVEX_W_0F3A21_P_2, |
| EVEX_W_0F3A22_P_2, |
| EVEX_W_0F3A23_P_2, |
| EVEX_W_0F3A38_P_2, |
| EVEX_W_0F3A39_P_2, |
| EVEX_W_0F3A3A_P_2, |
| EVEX_W_0F3A3B_P_2, |
| EVEX_W_0F3A3E_P_2, |
| EVEX_W_0F3A3F_P_2, |
| EVEX_W_0F3A42_P_2, |
| EVEX_W_0F3A43_P_2, |
| EVEX_W_0F3A50_P_2, |
| EVEX_W_0F3A51_P_2, |
| EVEX_W_0F3A56_P_2, |
| EVEX_W_0F3A57_P_2, |
| EVEX_W_0F3A66_P_2, |
| EVEX_W_0F3A67_P_2 |
| }; |
| |
| typedef void (*op_rtn) (int bytemode, int sizeflag); |
| |
| struct dis386 { |
| const char *name; |
| struct |
| { |
| op_rtn rtn; |
| int bytemode; |
| } op[MAX_OPERANDS]; |
| unsigned int prefix_requirement; |
| }; |
| |
| /* Upper case letters in the instruction names here are macros. |
| 'A' => print 'b' if no register operands or suffix_always is true |
| 'B' => print 'b' if suffix_always is true |
| 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
| size prefix |
| 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
| suffix_always is true |
| 'E' => print 'e' if 32-bit form of jcxz |
| 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
| 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
| 'H' => print ",pt" or ",pn" branch hint |
| 'I' => honor following macro letter even in Intel mode (implemented only |
| for some of the macro letters) |
| 'J' => print 'l' |
| 'K' => print 'd' or 'q' if rex prefix is present. |
| 'L' => print 'l' if suffix_always is true |
| 'M' => print 'r' if intel_mnemonic is false. |
| 'N' => print 'n' if instruction has no wait "prefix" |
| 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
| 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
| or suffix_always is true. print 'q' if rex prefix is present. |
| 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
| is true |
| 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
| 'S' => print 'w', 'l' or 'q' if suffix_always is true |
| 'T' => print 'q' in 64bit mode if instruction has no operand size |
| prefix and behave as 'P' otherwise |
| 'U' => print 'q' in 64bit mode if instruction has no operand size |
| prefix and behave as 'Q' otherwise |
| 'V' => print 'q' in 64bit mode if instruction has no operand size |
| prefix and behave as 'S' otherwise |
| 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
| 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
| 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
| suffix_always is true. |
| 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
| '!' => change condition from true to false or from false to true. |
| '%' => add 1 upper case letter to the macro. |
| '^' => print 'w' or 'l' depending on operand size prefix or |
| suffix_always is true (lcall/ljmp). |
| '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
| on operand size prefix. |
| '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
| has no operand size prefix for AMD64 ISA, behave as 'P' |
| otherwise |
| |
| 2 upper case letter macros: |
| "XY" => print 'x' or 'y' if suffix_always is true or no register |
| operands and no broadcast. |
| "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no |
| register operands and no broadcast. |
| "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
| "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand |
| or suffix_always is true |
| "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
| "LS" => print "abs" in 64bit mode and behave as 'S' otherwise |
| "LV" => print "abs" for 64bit operand and behave as 'S' otherwise |
| "LW" => print 'd', 'q' depending on the VEX.W bit |
| "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
| an operand size prefix, or suffix_always is true. print |
| 'q' if rex prefix is present. |
| |
| Many of the above letters print nothing in Intel mode. See "putop" |
| for the details. |
| |
| Braces '{' and '}', and vertical bars '|', indicate alternative |
| mnemonic strings for AT&T and Intel. */ |
| |
| static const struct dis386 dis386[] = { |
| /* 00 */ |
| { "addB", { Ebh1, Gb }, 0 }, |
| { "addS", { Evh1, Gv }, 0 }, |
| { "addB", { Gb, EbS }, 0 }, |
| { "addS", { Gv, EvS }, 0 }, |
| { "addB", { AL, Ib }, 0 }, |
| { "addS", { eAX, Iv }, 0 }, |
| { X86_64_TABLE (X86_64_06) }, |
| { X86_64_TABLE (X86_64_07) }, |
| /* 08 */ |
| { "orB", { Ebh1, Gb }, 0 }, |
| { "orS", { Evh1, Gv }, 0 }, |
| { "orB", { Gb, EbS }, 0 }, |
| { "orS", { Gv, EvS }, 0 }, |
| { "orB", { AL, Ib }, 0 }, |
| { "orS", { eAX, Iv }, 0 }, |
| { X86_64_TABLE (X86_64_0D) }, |
| { Bad_Opcode }, /* 0x0f extended opcode escape */ |
| /* 10 */ |
| { "adcB", { Ebh1, Gb }, 0 }, |
| { "adcS", { Evh1, Gv }, 0 }, |
| { "adcB", { Gb, EbS }, 0 }, |
| { "adcS", { Gv, EvS }, 0 }, |
| { "adcB", { AL, Ib }, 0 }, |
| { "adcS", { eAX, Iv }, 0 }, |
| { X86_64_TABLE (X86_64_16) }, |
| { X86_64_TABLE (X86_64_17) }, |
| /* 18 */ |
| { "sbbB", { Ebh1, Gb }, 0 }, |
| { "sbbS", { Evh1, Gv }, 0 }, |
| { "sbbB", { Gb, EbS }, 0 }, |
| { "sbbS", { Gv, EvS }, 0 }, |
| { "sbbB", { AL, Ib }, 0 }, |
| { "sbbS", { eAX, Iv }, 0 }, |
| { X86_64_TABLE (X86_64_1E) }, |
| { X86_64_TABLE (X86_64_1F) }, |
| /* 20 */ |
| { "andB", { Ebh1, Gb }, 0 }, |
| { "andS", { Evh1, Gv }, 0 }, |
| { "andB", { Gb, EbS }, 0 }, |
| { "andS", { Gv, EvS }, 0 }, |
| { "andB", { AL, Ib }, 0 }, |
| { "andS", { eAX, Iv }, 0 }, |
| { Bad_Opcode }, /* SEG ES prefix */ |
| { X86_64_TABLE (X86_64_27) }, |
| /* 28 */ |
| { "subB", { Ebh1, Gb }, 0 }, |
| { "subS", { Evh1, Gv }, 0 }, |
| { "subB", { Gb, EbS }, 0 }, |
| { "subS", { Gv, EvS }, 0 }, |
| { "subB", { AL, Ib }, 0 }, |
| { "subS", { eAX, Iv }, 0 }, |
| { Bad_Opcode }, /* SEG CS prefix */ |
| { X86_64_TABLE (X86_64_2F) }, |
| /* 30 */ |
| { "xorB", { Ebh1, Gb }, 0 }, |
| { "xorS", { Evh1, Gv }, 0 }, |
| { "xorB", { Gb, EbS }, 0 }, |
| { "xorS", { Gv, EvS }, 0 }, |
| { "xorB", { AL, Ib }, 0 }, |
| { "xorS", { eAX, Iv }, 0 }, |
| { Bad_Opcode }, /* SEG SS prefix */ |
| { X86_64_TABLE (X86_64_37) }, |
| /* 38 */ |
| { "cmpB", { Eb, Gb }, 0 }, |
| { "cmpS", { Ev, Gv }, 0 }, |
| { "cmpB", { Gb, EbS }, 0 }, |
| { "cmpS", { Gv, EvS }, 0 }, |
| { "cmpB", { AL, Ib }, 0 }, |
| { "cmpS", { eAX, Iv }, 0 }, |
| { Bad_Opcode }, /* SEG DS prefix */ |
| { X86_64_TABLE (X86_64_3F) }, |
| /* 40 */ |
| { "inc{S|}", { RMeAX }, 0 }, |
| { "inc{S|}", { RMeCX }, 0 }, |
| { "inc{S|}", { RMeDX }, 0 }, |
| { "inc{S|}", { RMeBX }, 0 }, |
| { "inc{S|}", { RMeSP }, 0 }, |
| { "inc{S|}", { RMeBP }, 0 }, |
| { "inc{S|}", { RMeSI }, 0 }, |
| { "inc{S|}", { RMeDI }, 0 }, |
| /* 48 */ |
| { "dec{S|}", { RMeAX }, 0 }, |
| { "dec{S|}", { RMeCX }, 0 }, |
| { "dec{S|}", { RMeDX }, 0 }, |
| { "dec{S|}", { RMeBX }, 0 }, |
| { "dec{S|}", { RMeSP }, 0 }, |
| { "dec{S|}", { RMeBP }, 0 }, |
| { "dec{S|}", { RMeSI }, 0 }, |
| { "dec{S|}", { RMeDI }, 0 }, |
| /* 50 */ |
| { "pushV", { RMrAX }, 0 }, |
| { "pushV", { RMrCX }, 0 }, |
| { "pushV", { RMrDX }, 0 }, |
| { "pushV", { RMrBX }, 0 }, |
| { "pushV", { RMrSP }, 0 }, |
| { "pushV", { RMrBP }, 0 }, |
| { "pushV", { RMrSI }, 0 }, |
| { "pushV", { RMrDI }, 0 }, |
| /* 58 */ |
| { "popV", { RMrAX }, 0 }, |
| { "popV", { RMrCX }, 0 }, |
| { "popV", { RMrDX }, 0 }, |
| { "popV", { RMrBX }, 0 }, |
| { "popV", { RMrSP }, 0 }, |
| { "popV", { RMrBP }, 0 }, |
| { "popV", { RMrSI }, 0 }, |
| { "popV", { RMrDI }, 0 }, |
| /* 60 */ |
| { X86_64_TABLE (X86_64_60) }, |
| { X86_64_TABLE (X86_64_61) }, |
| { X86_64_TABLE (X86_64_62) }, |
| { X86_64_TABLE (X86_64_63) }, |
| { Bad_Opcode }, /* seg fs */ |
| { Bad_Opcode }, /* seg gs */ |
| { Bad_Opcode }, /* op size prefix */ |
| { Bad_Opcode }, /* adr size prefix */ |
| /* 68 */ |
| { "pushT", { sIv }, 0 }, |
| { "imulS", { Gv, Ev, Iv }, 0 }, |
| { "pushT", { sIbT }, 0 }, |
| { "imulS", { Gv, Ev, sIb }, 0 }, |
| { "ins{b|}", { Ybr, indirDX }, 0 }, |
| { X86_64_TABLE (X86_64_6D) }, |
| { "outs{b|}", { indirDXr, Xb }, 0 }, |
| { X86_64_TABLE (X86_64_6F) }, |
| /* 70 */ |
| { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jbH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jeH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jneH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jaH", { Jb, BND, cond_jump_flag }, 0 }, |
| /* 78 */ |
| { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jpH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jlH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jleH", { Jb, BND, cond_jump_flag }, 0 }, |
| { "jgH", { Jb, BND, cond_jump_flag }, 0 }, |
| /* 80 */ |
| { REG_TABLE (REG_80) }, |
| { REG_TABLE (REG_81) }, |
| { X86_64_TABLE (X86_64_82) }, |
| { REG_TABLE (REG_83) }, |
| { "testB", { Eb, Gb }, 0 }, |
| { "testS", { Ev, Gv }, 0 }, |
| { "xchgB", { Ebh2, Gb }, 0 }, |
| { "xchgS", { Evh2, Gv }, 0 }, |
| /* 88 */ |
| { "movB", { Ebh3, Gb }, 0 }, |
| { "movS", { Evh3, Gv }, 0 }, |
| { "movB", { Gb, EbS }, 0 }, |
| { "movS", { Gv, EvS }, 0 }, |
| { "movD", { Sv, Sw }, 0 }, |
| { MOD_TABLE (MOD_8D) }, |
| { "movD", { Sw, Sv }, 0 }, |
| { REG_TABLE (REG_8F) }, |
| /* 90 */ |
| { PREFIX_TABLE (PREFIX_90) }, |
| { "xchgS", { RMeCX, eAX }, 0 }, |
| { "xchgS", { RMeDX, eAX }, 0 }, |
| { "xchgS", { RMeBX, eAX }, 0 }, |
| { "xchgS", { RMeSP, eAX }, 0 }, |
| { "xchgS", { RMeBP, eAX }, 0 }, |
| { "xchgS", { RMeSI, eAX }, 0 }, |
| { "xchgS", { RMeDI, eAX }, 0 }, |
| /* 98 */ |
| { "cW{t|}R", { XX }, 0 }, |
| { "cR{t|}O", { XX }, 0 }, |
| { X86_64_TABLE (X86_64_9A) }, |
| { Bad_Opcode }, /* fwait */ |
| { "pushfT", { XX }, 0 }, |
| { "popfT", { XX }, 0 }, |
| { "sahf", { XX }, 0 }, |
| { "lahf", { XX }, 0 }, |
| /* a0 */ |
| { "mov%LB", { AL, Ob }, 0 }, |
| { "mov%LS", { eAX, Ov }, 0 }, |
| { "mov%LB", { Ob, AL }, 0 }, |
| { "mov%LS", { Ov, eAX }, 0 }, |
| { "movs{b|}", { Ybr, Xb }, 0 }, |
| { "movs{R|}", { Yvr, Xv }, 0 }, |
| { "cmps{b|}", { Xb, Yb }, 0 }, |
| { "cmps{R|}", { Xv, Yv }, 0 }, |
| /* a8 */ |
| { "testB", { AL, Ib }, 0 }, |
| { "testS", { eAX, Iv }, 0 }, |
| { "stosB", { Ybr, AL }, 0 }, |
| { "stosS", { Yvr, eAX }, 0 }, |
| { "lodsB", { ALr, Xb }, 0 }, |
| { "lodsS", { eAXr, Xv }, 0 }, |
| { "scasB", { AL, Yb }, 0 }, |
| { "scasS", { eAX, Yv }, 0 }, |
| /* b0 */ |
| { "movB", { RMAL, Ib }, 0 }, |
| { "movB", { RMCL, Ib }, 0 }, |
| { "movB", { RMDL, Ib }, 0 }, |
| { "movB", { RMBL, Ib }, 0 }, |
| { "movB", { RMAH, Ib }, 0 }, |
| { "movB", { RMCH, Ib }, 0 }, |
| { "movB", { RMDH, Ib }, 0 }, |
| { "movB", { RMBH, Ib }, 0 }, |
| /* b8 */ |
| { "mov%LV", { RMeAX, Iv64 }, 0 }, |
| { "mov%LV", { RMeCX, Iv64 }, 0 }, |
| { "mov%LV", { RMeDX, Iv64 }, 0 }, |
| { "mov%LV", { RMeBX, Iv64 }, 0 }, |
| { "mov%LV", { RMeSP, Iv64 }, 0 }, |
| { "mov%LV", { RMeBP, Iv64 }, 0 }, |
| { "mov%LV", { RMeSI, Iv64 }, 0 }, |
| { "mov%LV", { RMeDI, Iv64 }, 0 }, |
| /* c0 */ |
| { REG_TABLE (REG_C0) }, |
| { REG_TABLE (REG_C1) }, |
| { "retT", { Iw, BND }, 0 }, |
| { "retT", { BND }, 0 }, |
| { X86_64_TABLE (X86_64_C4) }, |
| { X86_64_TABLE (X86_64_C5) }, |
| { REG_TABLE (REG_C6) }, |
| { REG_TABLE (REG_C7) }, |
| /* c8 */ |
| { "enterT", { Iw, Ib }, 0 }, |
| { "leaveT", { XX }, 0 }, |
| { "Jret{|f}P", { Iw }, 0 }, |
| { "Jret{|f}P", { XX }, 0 }, |
| { "int3", { XX }, 0 }, |
| { "int", { Ib }, 0 }, |
| { X86_64_TABLE (X86_64_CE) }, |
| { "iret%LP", { XX }, 0 }, |
| /* d0 */ |
| { REG_TABLE (REG_D0) }, |
| { REG_TABLE (REG_D1) }, |
| { REG_TABLE (REG_D2) }, |
| { REG_TABLE (REG_D3) }, |
| { X86_64_TABLE (X86_64_D4) }, |
| { X86_64_TABLE (X86_64_D5) }, |
| { Bad_Opcode }, |
| { "xlat", { DSBX }, 0 }, |
| /* d8 */ |
| { FLOAT }, |
| { FLOAT }, |
| { FLOAT }, |
| { FLOAT }, |
| { FLOAT }, |
| { FLOAT }, |
| { FLOAT }, |
| { FLOAT }, |
| /* e0 */ |
| { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
| { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
| { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
| { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, |
| { "inB", { AL, Ib }, 0 }, |
| { "inG", { zAX, Ib }, 0 }, |
| { "outB", { Ib, AL }, 0 }, |
| { "outG", { Ib, zAX }, 0 }, |
| /* e8 */ |
| { X86_64_TABLE (X86_64_E8) }, |
| { X86_64_TABLE (X86_64_E9) }, |
| { X86_64_TABLE (X86_64_EA) }, |
| { "jmp", { Jb, BND }, 0 }, |
| { "inB", { AL, indirDX }, 0 }, |
| { "inG", { zAX, indirDX }, 0 }, |
| { "outB", { indirDX, AL }, 0 }, |
| { "outG", { indirDX, zAX }, 0 }, |
| /* f0 */ |
| { Bad_Opcode }, /* lock prefix */ |
| { "icebp", { XX }, 0 }, |
| { Bad_Opcode }, /* repne */ |
| { Bad_Opcode }, /* repz */ |
| { "hlt", { XX }, 0 }, |
| { "cmc", { XX }, 0 }, |
| { REG_TABLE (REG_F6) }, |
| { REG_TABLE (REG_F7) }, |
| /* f8 */ |
| { "clc", { XX }, 0 }, |
| { "stc", { XX }, 0 }, |
| { "cli", { XX }, 0 }, |
| { "sti", { XX }, 0 }, |
| { "cld", { XX }, 0 }, |
| { "std", { XX }, 0 }, |
| { REG_TABLE (REG_FE) }, |
| { REG_TABLE (REG_FF) }, |
| }; |
| |
| static const struct dis386 dis386_twobyte[] = { |
| /* 00 */ |
| { REG_TABLE (REG_0F00 ) }, |
| { REG_TABLE (REG_0F01 ) }, |
| { "larS", { Gv, Ew }, 0 }, |
| { "lslS", { Gv, Ew }, 0 }, |
| { Bad_Opcode }, |
| { "syscall", { XX }, 0 }, |
| { "clts", { XX }, 0 }, |
| { "sysret%LP", { XX }, 0 }, |
| /* 08 */ |
| { "invd", { XX }, 0 }, |
| { "wbinvd", { XX }, 0 }, |
| { Bad_Opcode }, |
| { "ud2", { XX }, 0 }, |
| { Bad_Opcode }, |
| { REG_TABLE (REG_0F0D) }, |
| { "femms", { XX }, 0 }, |
| { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ |
| /* 10 */ |
| { PREFIX_TABLE (PREFIX_0F10) }, |
| { PREFIX_TABLE (PREFIX_0F11) }, |
| { PREFIX_TABLE (PREFIX_0F12) }, |
| { MOD_TABLE (MOD_0F13) }, |
| { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
| { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0F16) }, |
| { MOD_TABLE (MOD_0F17) }, |
| /* 18 */ |
| { REG_TABLE (REG_0F18) }, |
| { "nopQ", { Ev }, 0 }, |
| { PREFIX_TABLE (PREFIX_0F1A) }, |
| { PREFIX_TABLE (PREFIX_0F1B) }, |
| { "nopQ", { Ev }, 0 }, |
| { "nopQ", { Ev }, 0 }, |
| { "nopQ", { Ev }, 0 }, |
| { "nopQ", { Ev }, 0 }, |
| /* 20 */ |
| { "movZ", { Rm, Cm }, 0 }, |
| { "movZ", { Rm, Dm }, 0 }, |
| { "movZ", { Cm, Rm }, 0 }, |
| { "movZ", { Dm, Rm }, 0 }, |
| { MOD_TABLE (MOD_0F24) }, |
| { Bad_Opcode }, |
| { MOD_TABLE (MOD_0F26) }, |
| { Bad_Opcode }, |
| /* 28 */ |
| { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
| { "movapX", { EXxS, XM }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0F2A) }, |
| { PREFIX_TABLE (PREFIX_0F2B) }, |
| { PREFIX_TABLE (PREFIX_0F2C) }, |
| { PREFIX_TABLE (PREFIX_0F2D) }, |
| { PREFIX_TABLE (PREFIX_0F2E) }, |
| { PREFIX_TABLE (PREFIX_0F2F) }, |
| /* 30 */ |
| { "wrmsr", { XX }, 0 }, |
| { "rdtsc", { XX }, 0 }, |
| { "rdmsr", { XX }, 0 }, |
| { "rdpmc", { XX }, 0 }, |
| { "sysenter", { XX }, 0 }, |
| { "sysexit", { XX }, 0 }, |
| { Bad_Opcode }, |
| { "getsec", { XX }, 0 }, |
| /* 38 */ |
| { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
| { Bad_Opcode }, |
| { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
| { Bad_Opcode }, |
| { Bad_Opcode }, |
| { Bad_Opcode }, |
| { Bad_Opcode }, |
| { Bad_Opcode }, |
| /* 40 */ |
| { "cmovoS", { Gv, Ev }, 0 }, |
| { "cmovnoS", { Gv, Ev }, 0 }, |
| { "cmovbS", { Gv, Ev }, 0 }, |
| { "cmovaeS", { Gv, Ev }, 0 }, |
| { "cmoveS", { Gv, Ev }, 0 }, |
| { "cmovneS", { Gv, Ev }, 0 }, |
| { "cmovbeS", { Gv, Ev }, 0 }, |
| { "cmovaS", { Gv, Ev }, 0 }, |
| /* 48 */ |
| { "cmovsS", { Gv, Ev }, 0 }, |
| { "cmovnsS", { Gv, Ev }, 0 }, |
| { "cmovpS", { Gv, Ev }, 0 }, |
| { "cmovnpS", { Gv, Ev }, 0 }, |
| { "cmovlS", { Gv, Ev }, 0 }, |
| { "cmovgeS", { Gv, Ev }, 0 }, |
| { "cmovleS", { Gv, Ev }, 0 }, |
| { "cmovgS", { Gv, Ev }, 0 }, |
| /* 50 */ |
| { MOD_TABLE (MOD_0F51) }, |
| { PREFIX_TABLE (PREFIX_0F51) }, |
| { PREFIX_TABLE (PREFIX_0F52) }, |
| { PREFIX_TABLE (PREFIX_0F53) }, |
| { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
| { "andnpX", { XM, EXx }, PREFIX_OPCODE }, |
| { "orpX", { XM, EXx }, PREFIX_OPCODE }, |
| { "xorpX", { XM, EXx }, PREFIX_OPCODE }, |
| /* 58 */ |
| { PREFIX_TABLE (PREFIX_0F58) }, |
| { PREFIX_TABLE (PREFIX_0F59) }, |
| { PREFIX_TABLE (PREFIX_0F5A) }, |
| { PREFIX_TABLE (PREFIX_0F5B) }, |
| { PREFIX_TABLE (PREFIX_0F5C) }, |
| { PREFIX_TABLE (PREFIX_0F5D) }, |
| { PREFIX_TABLE (PREFIX_0F5E) }, |
| { PREFIX_TABLE (PREFIX_0F5F) }, |
| /* 60 */ |
| { PREFIX_TABLE (PREFIX_0F60) }, |
| { PREFIX_TABLE (PREFIX_0F61) }, |
| { PREFIX_TABLE (PREFIX_0F62) }, |
| { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
| { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, |
| { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, |
| { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, |
| { "packuswb", { MX, EM }, PREFIX_OPCODE }, |
| /* 68 */ |
| { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
| { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, |
| { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, |
| { "packssdw", { MX, EM }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0F6C) }, |
| { PREFIX_TABLE (PREFIX_0F6D) }, |
| { "movK", { MX, Edq }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0F6F) }, |
| /* 70 */ |
| { PREFIX_TABLE (PREFIX_0F70) }, |
| { REG_TABLE (REG_0F71) }, |
| { REG_TABLE (REG_0F72) }, |
| { REG_TABLE (REG_0F73) }, |
| { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
| { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, |
| { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, |
| { "emms", { XX }, PREFIX_OPCODE }, |
| /* 78 */ |
| { PREFIX_TABLE (PREFIX_0F78) }, |
| { PREFIX_TABLE (PREFIX_0F79) }, |
| { Bad_Opcode }, |
| { Bad_Opcode }, |
| { PREFIX_TABLE (PREFIX_0F7C) }, |
| { PREFIX_TABLE (PREFIX_0F7D) }, |
| { PREFIX_TABLE (PREFIX_0F7E) }, |
| { PREFIX_TABLE (PREFIX_0F7F) }, |
| /* 80 */ |
| { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jbH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jeH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jneH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jaH", { Jv, BND, cond_jump_flag }, 0 }, |
| /* 88 */ |
| { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jpH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jlH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jleH", { Jv, BND, cond_jump_flag }, 0 }, |
| { "jgH", { Jv, BND, cond_jump_flag }, 0 }, |
| /* 90 */ |
| { "seto", { Eb }, 0 }, |
| { "setno", { Eb }, 0 }, |
| { "setb", { Eb }, 0 }, |
| { "setae", { Eb }, 0 }, |
| { "sete", { Eb }, 0 }, |
| { "setne", { Eb }, 0 }, |
| { "setbe", { Eb }, 0 }, |
| { "seta", { Eb }, 0 }, |
| /* 98 */ |
| { "sets", { Eb }, 0 }, |
| { "setns", { Eb }, 0 }, |
| { "setp", { Eb }, 0 }, |
| { "setnp", { Eb }, 0 }, |
| { "setl", { Eb }, 0 }, |
| { "setge", { Eb }, 0 }, |
| { "setle", { Eb }, 0 }, |
| { "setg", { Eb }, 0 }, |
| /* a0 */ |
| { "pushT", { fs }, 0 }, |
| { "popT", { fs }, 0 }, |
| { "cpuid", { XX }, 0 }, |
| { "btS", { Ev, Gv }, 0 }, |
| { "shldS", { Ev, Gv, Ib }, 0 }, |
| { "shldS", { Ev, Gv, CL }, 0 }, |
| { REG_TABLE (REG_0FA6) }, |
| { REG_TABLE (REG_0FA7) }, |
| /* a8 */ |
| { "pushT", { gs }, 0 }, |
| { "popT", { gs }, 0 }, |
| { "rsm", { XX }, 0 }, |
| { "btsS", { Evh1, Gv }, 0 }, |
| { "shrdS", { Ev, Gv, Ib }, 0 }, |
| { "shrdS", { Ev, Gv, CL }, 0 }, |
| { REG_TABLE (REG_0FAE) }, |
| { "imulS", { Gv, Ev }, 0 }, |
| /* b0 */ |
| { "cmpxchgB", { Ebh1, Gb }, 0 }, |
| { "cmpxchgS", { Evh1, Gv }, 0 }, |
| { MOD_TABLE (MOD_0FB2) }, |
| { "btrS", { Evh1, Gv }, 0 }, |
| { MOD_TABLE (MOD_0FB4) }, |
| { MOD_TABLE (MOD_0FB5) }, |
| { "movz{bR|x}", { Gv, Eb }, 0 }, |
| { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ |
| /* b8 */ |
| { PREFIX_TABLE (PREFIX_0FB8) }, |
| { "ud1", { XX }, 0 }, |
| { REG_TABLE (REG_0FBA) }, |
| { "btcS", { Evh1, Gv }, 0 }, |
| { PREFIX_TABLE (PREFIX_0FBC) }, |
| { PREFIX_TABLE (PREFIX_0FBD) }, |
| { "movs{bR|x}", { Gv, Eb }, 0 }, |
| { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ |
| /* c0 */ |
| { "xaddB", { Ebh1, Gb }, 0 }, |
| { "xaddS", { Evh1, Gv }, 0 }, |
| { PREFIX_TABLE (PREFIX_0FC2) }, |
| { MOD_TABLE (MOD_0FC3) }, |
| { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
| { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, |
| { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, |
| { REG_TABLE (REG_0FC7) }, |
| /* c8 */ |
| { "bswap", { RMeAX }, 0 }, |
| { "bswap", { RMeCX }, 0 }, |
| { "bswap", { RMeDX }, 0 }, |
| { "bswap", { RMeBX }, 0 }, |
| { "bswap", { RMeSP }, 0 }, |
| { "bswap", { RMeBP }, 0 }, |
| { "bswap", { RMeSI }, 0 }, |
| { "bswap", { RMeDI }, 0 }, |
| /* d0 */ |
| { PREFIX_TABLE (PREFIX_0FD0) }, |
| { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
| { "psrld", { MX, EM }, PREFIX_OPCODE }, |
| { "psrlq", { MX, EM }, PREFIX_OPCODE }, |
| { "paddq", { MX, EM }, PREFIX_OPCODE }, |
| { "pmullw", { MX, EM }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0FD6) }, |
| { MOD_TABLE (MOD_0FD7) }, |
| /* d8 */ |
| { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
| { "psubusw", { MX, EM }, PREFIX_OPCODE }, |
| { "pminub", { MX, EM }, PREFIX_OPCODE }, |
| { "pand", { MX, EM }, PREFIX_OPCODE }, |
| { "paddusb", { MX, EM }, PREFIX_OPCODE }, |
| { "paddusw", { MX, EM }, PREFIX_OPCODE }, |
| { "pmaxub", { MX, EM }, PREFIX_OPCODE }, |
| { "pandn", { MX, EM }, PREFIX_OPCODE }, |
| /* e0 */ |
| { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
| { "psraw", { MX, EM }, PREFIX_OPCODE }, |
| { "psrad", { MX, EM }, PREFIX_OPCODE }, |
| { "pavgw", { MX, EM }, PREFIX_OPCODE }, |
| { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, |
| { "pmulhw", { MX, EM }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0FE6) }, |
| { PREFIX_TABLE (PREFIX_0FE7) }, |
| /* e8 */ |
| { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
| { "psubsw", { MX, EM }, PREFIX_OPCODE }, |
| { "pminsw", { MX, EM }, PREFIX_OPCODE }, |
| { "por", { MX, EM }, PREFIX_OPCODE }, |
| { "paddsb", { MX, EM }, PREFIX_OPCODE }, |
| { "paddsw", { MX, EM }, PREFIX_OPCODE }, |
| { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, |
| { "pxor", { MX, EM }, PREFIX_OPCODE }, |
| /* f0 */ |
| { PREFIX_TABLE (PREFIX_0FF0) }, |
| { "psllw", { MX, EM }, PREFIX_OPCODE }, |
| { "pslld", { MX, EM }, PREFIX_OPCODE }, |
| { "psllq", { MX, EM }, PREFIX_OPCODE }, |
| { "pmuludq", { MX, EM }, PREFIX_OPCODE }, |
| { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, |
| { "psadbw", { MX, EM }, PREFIX_OPCODE }, |
| { PREFIX_TABLE (PREFIX_0FF7) }, |
| /* f8 */ |
| { "psubb", { MX, EM }, PREFIX_OPCODE }, |
| { "psubw", { MX, EM }, PREFIX_OPCODE }, |
| { "psubd", { MX, EM }, PREFIX_OPCODE }, |
| { "psubq", { MX, EM }, PREFIX_OPCODE }, |
| { "paddb", { MX, EM }, PREFIX_OPCODE }, |
| { "paddw", { MX, EM }, PREFIX_OPCODE }, |
| { "paddd", { MX, EM }, PREFIX_OPCODE }, |
| { Bad_Opcode }, |
| }; |
| |
| static const unsigned char onebyte_has_modrm[256] = { |
| /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| /* ------------------------------- */ |
| /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ |
| /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ |
| /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ |
| /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ |
| /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ |
| /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ |
| /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ |
| /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ |
| /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ |
| /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ |
| /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ |
| /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ |
| /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ |
| /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ |
| /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ |
| /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ |
| /* ------------------------------- */ |
| /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| }; |
| |
| static const unsigned char twobyte_has_modrm[256] = { |
| /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| /* ------------------------------- */ |
| /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
| /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
| /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
|
