| /* aarch64-tbl.h -- AArch64 opcode description table and instruction |
| operand description table. |
| Copyright (C) 2012-2016 Free Software Foundation, Inc. |
| |
| This file is part of the GNU opcodes library. |
| |
| This library is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| |
| It is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with this file; see the file COPYING. If not, write to the |
| Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| |
| #include "aarch64-opc.h" |
| |
| #ifndef VERIFIER |
| #error VERIFIER must be defined. |
| #endif |
| |
| /* Operand type. */ |
| |
| #define OPND(x) AARCH64_OPND_##x |
| #define OP0() {} |
| #define OP1(a) {OPND(a)} |
| #define OP2(a,b) {OPND(a), OPND(b)} |
| #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} |
| #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} |
| #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} |
| |
| #define QLF(x) AARCH64_OPND_QLF_##x |
| #define QLF1(a) {QLF(a)} |
| #define QLF2(a,b) {QLF(a), QLF(b)} |
| #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} |
| #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} |
| #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} |
| |
| /* Qualifiers list. */ |
| |
| /* e.g. MSR <systemreg>, <Xt>. */ |
| #define QL_SRC_X \ |
| { \ |
| QLF2(NIL,X), \ |
| } |
| |
| /* e.g. MRS <Xt>, <systemreg>. */ |
| #define QL_DST_X \ |
| { \ |
| QLF2(X,NIL), \ |
| } |
| |
| /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ |
| #define QL_SYS \ |
| { \ |
| QLF5(NIL,NIL,NIL,NIL,X), \ |
| } |
| |
| /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ |
| #define QL_SYSL \ |
| { \ |
| QLF5(X,NIL,NIL,NIL,NIL), \ |
| } |
| |
| /* e.g. ADRP <Xd>, <label>. */ |
| #define QL_ADRP \ |
| { \ |
| QLF2(X,NIL), \ |
| } |
| |
| /* e.g. B.<cond> <label>. */ |
| #define QL_PCREL_NIL \ |
| { \ |
| QLF1(NIL), \ |
| } |
| |
| /* e.g. TBZ <Xt>, #<imm>, <label>. */ |
| #define QL_PCREL_14 \ |
| { \ |
| QLF3(X,imm_0_63,NIL), \ |
| } |
| |
| /* e.g. BL <label>. */ |
| #define QL_PCREL_26 \ |
| { \ |
| QLF1(NIL), \ |
| } |
| |
| /* e.g. LDRSW <Xt>, <label>. */ |
| #define QL_X_PCREL \ |
| { \ |
| QLF2(X,NIL), \ |
| } |
| |
| /* e.g. LDR <Wt>, <label>. */ |
| #define QL_R_PCREL \ |
| { \ |
| QLF2(W,NIL), \ |
| QLF2(X,NIL), \ |
| } |
| |
| /* e.g. LDR <Dt>, <label>. */ |
| #define QL_FP_PCREL \ |
| { \ |
| QLF2(S_S,NIL), \ |
| QLF2(S_D,NIL), \ |
| QLF2(S_Q,NIL), \ |
| } |
| |
| /* e.g. PRFM <prfop>, <label>. */ |
| #define QL_PRFM_PCREL \ |
| { \ |
| QLF2(NIL,NIL), \ |
| } |
| |
| /* e.g. BR <Xn>. */ |
| #define QL_I1X \ |
| { \ |
| QLF1(X), \ |
| } |
| |
| /* e.g. RBIT <Wd>, <Wn>. */ |
| #define QL_I2SAME \ |
| { \ |
| QLF2(W,W), \ |
| QLF2(X,X), \ |
| } |
| |
| /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */ |
| #define QL_I2_EXT \ |
| { \ |
| QLF2(W,W), \ |
| QLF2(X,W), \ |
| QLF2(X,X), \ |
| } |
| |
| /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */ |
| #define QL_I2SP \ |
| { \ |
| QLF2(WSP,W), \ |
| QLF2(W,WSP), \ |
| QLF2(SP,X), \ |
| QLF2(X,SP), \ |
| } |
| |
| /* e.g. REV <Wd>, <Wn>. */ |
| #define QL_I2SAMEW \ |
| { \ |
| QLF2(W,W), \ |
| } |
| |
| /* e.g. REV32 <Xd>, <Xn>. */ |
| #define QL_I2SAMEX \ |
| { \ |
| QLF2(X,X), \ |
| } |
| |
| #define QL_I2SAMER \ |
| { \ |
| QLF2(W,W), \ |
| QLF2(X,X), \ |
| } |
| |
| /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */ |
| #define QL_I3SAMEW \ |
| { \ |
| QLF3(W,W,W), \ |
| } |
| |
| /* e.g. SMULH <Xd>, <Xn>, <Xm>. */ |
| #define QL_I3SAMEX \ |
| { \ |
| QLF3(X,X,X), \ |
| } |
| |
| /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */ |
| #define QL_I3WWX \ |
| { \ |
| QLF3(W,W,X), \ |
| } |
| |
| /* e.g. UDIV <Xd>, <Xn>, <Xm>. */ |
| #define QL_I3SAMER \ |
| { \ |
| QLF3(W,W,W), \ |
| QLF3(X,X,X), \ |
| } |
| |
| /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */ |
| #define QL_I3_EXT \ |
| { \ |
| QLF3(W,W,W), \ |
| QLF3(X,X,W), \ |
| QLF3(X,X,X), \ |
| } |
| |
| /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */ |
| #define QL_I4SAMER \ |
| { \ |
| QLF4(W,W,W,W), \ |
| QLF4(X,X,X,X), \ |
| } |
| |
| /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ |
| #define QL_I3SAMEL \ |
| { \ |
| QLF3(X,W,W), \ |
| } |
| |
| /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ |
| #define QL_I4SAMEL \ |
| { \ |
| QLF4(X,W,W,X), \ |
| } |
| |
| /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */ |
| #define QL_CSEL \ |
| { \ |
| QLF4(W, W, W, NIL), \ |
| QLF4(X, X, X, NIL), \ |
| } |
| |
| /* e.g. CSET <Wd>, <cond>. */ |
| #define QL_DST_R \ |
| { \ |
| QLF2(W, NIL), \ |
| QLF2(X, NIL), \ |
| } |
| |
| /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */ |
| #define QL_BF \ |
| { \ |
| QLF4(W,W,imm_0_31,imm_0_31), \ |
| QLF4(X,X,imm_0_63,imm_0_63), \ |
| } |
| |
| /* e.g. BFC <Wd>, #<immr>, #<imms>. */ |
| #define QL_BF1 \ |
| { \ |
| QLF3 (W, imm_0_31, imm_1_32), \ |
| QLF3 (X, imm_0_63, imm_1_64), \ |
| } |
| |
| /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ |
| #define QL_BF2 \ |
| { \ |
| QLF4(W,W,imm_0_31,imm_1_32), \ |
| QLF4(X,X,imm_0_63,imm_1_64), \ |
| } |
| |
| /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */ |
| #define QL_FIX2FP \ |
| { \ |
| QLF3(S_D,W,imm_1_32), \ |
| QLF3(S_S,W,imm_1_32), \ |
| QLF3(S_D,X,imm_1_64), \ |
| QLF3(S_S,X,imm_1_64), \ |
| } |
| |
| /* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */ |
| #define QL_FIX2FP_H \ |
| { \ |
| QLF3 (S_H, W, imm_1_32), \ |
| QLF3 (S_H, X, imm_1_64), \ |
| } |
| |
| /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */ |
| #define QL_FP2FIX \ |
| { \ |
| QLF3(W,S_D,imm_1_32), \ |
| QLF3(W,S_S,imm_1_32), \ |
| QLF3(X,S_D,imm_1_64), \ |
| QLF3(X,S_S,imm_1_64), \ |
| } |
| |
| /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */ |
| #define QL_FP2FIX_H \ |
| { \ |
| QLF3 (W, S_H, imm_1_32), \ |
| QLF3 (X, S_H, imm_1_64), \ |
| } |
| |
| /* e.g. SCVTF <Dd>, <Wn>. */ |
| #define QL_INT2FP \ |
| { \ |
| QLF2(S_D,W), \ |
| QLF2(S_S,W), \ |
| QLF2(S_D,X), \ |
| QLF2(S_S,X), \ |
| } |
| |
| /* e.g. SCVTF <Hd>, <Wn>. */ |
| #define QL_INT2FP_H \ |
| { \ |
| QLF2 (S_H, W), \ |
| QLF2 (S_H, X), \ |
| } |
| |
| /* e.g. FCVTNS <Xd>, <Dn>. */ |
| #define QL_FP2INT \ |
| { \ |
| QLF2(W,S_D), \ |
| QLF2(W,S_S), \ |
| QLF2(X,S_D), \ |
| QLF2(X,S_S), \ |
| } |
| |
| /* e.g. FCVTNS <Hd>, <Wn>. */ |
| #define QL_FP2INT_H \ |
| { \ |
| QLF2 (W, S_H), \ |
| QLF2 (X, S_H), \ |
| } |
| |
| /* e.g. FJCVTZS <Wd>, <Dn>. */ |
| #define QL_FP2INT_W_D \ |
| { \ |
| QLF2 (W, S_D), \ |
| } |
| |
| /* e.g. FMOV <Xd>, <Vn>.D[1]. */ |
| #define QL_XVD1 \ |
| { \ |
| QLF2(X,S_D), \ |
| } |
| |
| /* e.g. FMOV <Vd>.D[1], <Xn>. */ |
| #define QL_VD1X \ |
| { \ |
| QLF2(S_D,X), \ |
| } |
| |
| /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */ |
| #define QL_EXTR \ |
| { \ |
| QLF4(W,W,W,imm_0_31), \ |
| QLF4(X,X,X,imm_0_63), \ |
| } |
| |
| /* e.g. LSL <Wd>, <Wn>, #<uimm>. */ |
| #define QL_SHIFT \ |
| { \ |
| QLF3(W,W,imm_0_31), \ |
| QLF3(X,X,imm_0_63), \ |
| } |
| |
| /* e.g. UXTH <Xd>, <Wn>. */ |
| #define QL_EXT \ |
| { \ |
| QLF2(W,W), \ |
| QLF2(X,W), \ |
| } |
| |
| /* e.g. UXTW <Xd>, <Wn>. */ |
| #define QL_EXT_W \ |
| { \ |
| QLF2(X,W), \ |
| } |
| |
| /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */ |
| #define QL_SSHIFT \ |
| { \ |
| QLF3(S_B , S_B , S_B ), \ |
| QLF3(S_H , S_H , S_H ), \ |
| QLF3(S_S , S_S , S_S ), \ |
| QLF3(S_D , S_D , S_D ) \ |
| } |
| |
| /* e.g. SSHR <V><d>, <V><n>, #<shift>. */ |
| #define QL_SSHIFT_D \ |
| { \ |
| QLF3(S_D , S_D , S_D ) \ |
| } |
| |
| /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| #define QL_SSHIFT_SD \ |
| { \ |
| QLF3(S_S , S_S , S_S ), \ |
| QLF3(S_D , S_D , S_D ) \ |
| } |
| |
| /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| #define QL_SSHIFT_H \ |
| { \ |
| QLF3 (S_H, S_H, S_H) \ |
| } |
| |
| /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ |
| #define QL_SSHIFTN \ |
| { \ |
| QLF3(S_B , S_H , S_B ), \ |
| QLF3(S_H , S_S , S_H ), \ |
| QLF3(S_S , S_D , S_S ), \ |
| } |
| |
| /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>. |
| The register operand variant qualifiers are deliberately used for the |
| immediate operand to ease the operand encoding/decoding and qualifier |
| sequence matching. */ |
| #define QL_VSHIFT \ |
| { \ |
| QLF3(V_8B , V_8B , V_8B ), \ |
| QLF3(V_16B, V_16B, V_16B), \ |
| QLF3(V_4H , V_4H , V_4H ), \ |
| QLF3(V_8H , V_8H , V_8H ), \ |
| QLF3(V_2S , V_2S , V_2S ), \ |
| QLF3(V_4S , V_4S , V_4S ), \ |
| QLF3(V_2D , V_2D , V_2D ) \ |
| } |
| |
| /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| #define QL_VSHIFT_SD \ |
| { \ |
| QLF3(V_2S , V_2S , V_2S ), \ |
| QLF3(V_4S , V_4S , V_4S ), \ |
| QLF3(V_2D , V_2D , V_2D ) \ |
| } |
| |
| /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ |
| #define QL_VSHIFT_H \ |
| { \ |
| QLF3 (V_4H, V_4H, V_4H), \ |
| QLF3 (V_8H, V_8H, V_8H) \ |
| } |
| |
| /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ |
| #define QL_VSHIFTN \ |
| { \ |
| QLF3(V_8B , V_8H , V_8B ), \ |
| QLF3(V_4H , V_4S , V_4H ), \ |
| QLF3(V_2S , V_2D , V_2S ), \ |
| } |
| |
| /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ |
| #define QL_VSHIFTN2 \ |
| { \ |
| QLF3(V_16B, V_8H, V_16B), \ |
| QLF3(V_8H , V_4S , V_8H ), \ |
| QLF3(V_4S , V_2D , V_4S ), \ |
| } |
| |
| /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. |
| the 3rd qualifier is used to help the encoding. */ |
| #define QL_VSHIFTL \ |
| { \ |
| QLF3(V_8H , V_8B , V_8B ), \ |
| QLF3(V_4S , V_4H , V_4H ), \ |
| QLF3(V_2D , V_2S , V_2S ), \ |
| } |
| |
| /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ |
| #define QL_VSHIFTL2 \ |
| { \ |
| QLF3(V_8H , V_16B, V_16B), \ |
| QLF3(V_4S , V_8H , V_8H ), \ |
| QLF3(V_2D , V_4S , V_4S ), \ |
| } |
| |
| /* e.g. TBL. */ |
| #define QL_TABLE \ |
| { \ |
| QLF3(V_8B , V_16B, V_8B ), \ |
| QLF3(V_16B, V_16B, V_16B), \ |
| } |
| |
| /* e.g. SHA1H. */ |
| #define QL_2SAMES \ |
| { \ |
| QLF2(S_S, S_S), \ |
| } |
| |
| /* e.g. ABS <V><d>, <V><n>. */ |
| #define QL_2SAMED \ |
| { \ |
| QLF2(S_D, S_D), \ |
| } |
| |
| /* e.g. CMGT <V><d>, <V><n>, #0. */ |
| #define QL_SISD_CMP_0 \ |
| { \ |
| QLF3(S_D, S_D, NIL), \ |
| } |
| |
| /* e.g. FCMEQ <V><d>, <V><n>, #0. */ |
| #define QL_SISD_FCMP_0 \ |
| { \ |
| QLF3(S_S, S_S, NIL), \ |
| QLF3(S_D, S_D, NIL), \ |
| } |
| |
| /* e.g. FCMEQ <V><d>, <V><n>, #0. */ |
| #define QL_SISD_FCMP_H_0 \ |
| { \ |
| QLF3 (S_H, S_H, NIL), \ |
| } |
| |
| /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
| #define QL_SISD_PAIR \ |
| { \ |
| QLF2(S_S, V_2S), \ |
| QLF2(S_D, V_2D), \ |
| } |
| |
| /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ |
| #define QL_SISD_PAIR_H \ |
| { \ |
| QLF2 (S_H, V_2H), \ |
| } |
| |
| /* e.g. ADDP <V><d>, <Vn>.<T>. */ |
| #define QL_SISD_PAIR_D \ |
| { \ |
| QLF2(S_D, V_2D), \ |
| } |
| |
| /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */ |
| #define QL_S_2SAME \ |
| { \ |
| QLF2(S_B, S_B), \ |
| QLF2(S_H, S_H), \ |
| QLF2(S_S, S_S), \ |
| QLF2(S_D, S_D), \ |
| } |
| |
| /* e.g. FCVTNS <V><d>, <V><n>. */ |
| #define QL_S_2SAMESD \ |
| { \ |
| QLF2(S_S, S_S), \ |
| QLF2(S_D, S_D), \ |
| } |
| |
| /* e.g. FCVTNS <V><d>, <V><n>. */ |
| #define QL_S_2SAMEH \ |
| { \ |
| QLF2 (S_H, S_H), \ |
| } |
| |
| /* e.g. SQXTN <Vb><d>, <Va><n>. */ |
| #define QL_SISD_NARROW \ |
| { \ |
| QLF2(S_B, S_H), \ |
| QLF2(S_H, S_S), \ |
| QLF2(S_S, S_D), \ |
| } |
| |
| /* e.g. FCVTXN <Vb><d>, <Va><n>. */ |
| #define QL_SISD_NARROW_S \ |
| { \ |
| QLF2(S_S, S_D), \ |
| } |
| |
| /* e.g. FCVT. */ |
| #define QL_FCVT \ |
| { \ |
| QLF2(S_S, S_H), \ |
| QLF2(S_S, S_D), \ |
| QLF2(S_D, S_H), \ |
| QLF2(S_D, S_S), \ |
| QLF2(S_H, S_S), \ |
| QLF2(S_H, S_D), \ |
| } |
| |
| /* FMOV <Dd>, <Dn>. */ |
| #define QL_FP2 \ |
| { \ |
| QLF2(S_S, S_S), \ |
| QLF2(S_D, S_D), \ |
| } |
| |
| /* FMOV <Hd>, <Hn>. */ |
| #define QL_FP2_H \ |
| { \ |
| QLF2 (S_H, S_H), \ |
| } |
| |
| /* e.g. SQADD <V><d>, <V><n>, <V><m>. */ |
| #define QL_S_3SAME \ |
| { \ |
| QLF3(S_B, S_B, S_B), \ |
| QLF3(S_H, S_H, S_H), \ |
| QLF3(S_S, S_S, S_S), \ |
| QLF3(S_D, S_D, S_D), \ |
| } |
| |
| /* e.g. CMGE <V><d>, <V><n>, <V><m>. */ |
| #define QL_S_3SAMED \ |
| { \ |
| QLF3(S_D, S_D, S_D), \ |
| } |
| |
| /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */ |
| #define QL_SISD_HS \ |
| { \ |
| QLF3(S_H, S_H, S_H), \ |
| QLF3(S_S, S_S, S_S), \ |
| } |
| |
| /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */ |
| #define QL_SISDL_HS \ |
| { \ |
| QLF3(S_S, S_H, S_H), \ |
| QLF3(S_D, S_S, S_S), \ |
| } |
| |
| /* FMUL <Sd>, <Sn>, <Sm>. */ |
| #define QL_FP3 \ |
| { \ |
| QLF3(S_S, S_S, S_S), \ |
| QLF3(S_D, S_D, S_D), \ |
| } |
| |
| /* FMUL <Hd>, <Hn>, <Hm>. */ |
| #define QL_FP3_H \ |
| { \ |
| QLF3 (S_H, S_H, S_H), \ |
| } |
| |
| /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */ |
| #define QL_FP4 \ |
| { \ |
| QLF4(S_S, S_S, S_S, S_S), \ |
| QLF4(S_D, S_D, S_D, S_D), \ |
| } |
| |
| /* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */ |
| #define QL_FP4_H \ |
| { \ |
| QLF4 (S_H, S_H, S_H, S_H), \ |
| } |
| |
| /* e.g. FCMP <Dn>, #0.0. */ |
| #define QL_DST_SD \ |
| { \ |
| QLF2(S_S, NIL), \ |
| QLF2(S_D, NIL), \ |
| } |
| |
| /* e.g. FCMP <Hn>, #0.0. */ |
| #define QL_DST_H \ |
| { \ |
| QLF2 (S_H, NIL), \ |
| } |
| |
| /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */ |
| #define QL_FP_COND \ |
| { \ |
| QLF4(S_S, S_S, S_S, NIL), \ |
| QLF4(S_D, S_D, S_D, NIL), \ |
| } |
| |
| /* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */ |
| #define QL_FP_COND_H \ |
| { \ |
| QLF4 (S_H, S_H, S_H, NIL), \ |
| } |
| |
| /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */ |
| #define QL_CCMP \ |
| { \ |
| QLF4(W, W, NIL, NIL), \ |
| QLF4(X, X, NIL, NIL), \ |
| } |
| |
| /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */ |
| #define QL_CCMP_IMM \ |
| { \ |
| QLF4(W, NIL, NIL, NIL), \ |
| QLF4(X, NIL, NIL, NIL), \ |
| } |
| |
| /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ |
| #define QL_FCCMP \ |
| { \ |
| QLF4(S_S, S_S, NIL, NIL), \ |
| QLF4(S_D, S_D, NIL, NIL), \ |
| } |
| |
| /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ |
| #define QL_FCCMP_H \ |
| { \ |
| QLF4 (S_H, S_H, NIL, NIL), \ |
| } |
| |
| /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */ |
| #define QL_DUP_VX \ |
| { \ |
| QLF2(V_8B , S_B ), \ |
| QLF2(V_16B, S_B ), \ |
| QLF2(V_4H , S_H ), \ |
| QLF2(V_8H , S_H ), \ |
| QLF2(V_2S , S_S ), \ |
| QLF2(V_4S , S_S ), \ |
| QLF2(V_2D , S_D ), \ |
| } |
| |
| /* e.g. DUP <Vd>.<T>, <Wn>. */ |
| #define QL_DUP_VR \ |
| { \ |
| QLF2(V_8B , W ), \ |
| QLF2(V_16B, W ), \ |
| QLF2(V_4H , W ), \ |
| QLF2(V_8H , W ), \ |
| QLF2(V_2S , W ), \ |
| QLF2(V_4S , W ), \ |
| QLF2(V_2D , X ), \ |
| } |
| |
| /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */ |
| #define QL_INS_XR \ |
| { \ |
| QLF2(S_H , W ), \ |
| QLF2(S_S , W ), \ |
| QLF2(S_D , X ), \ |
| QLF2(S_B , W ), \ |
| } |
| |
| /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */ |
| #define QL_SMOV \ |
| { \ |
| QLF2(W , S_H), \ |
| QLF2(X , S_H), \ |
| QLF2(X , S_S), \ |
| QLF2(W , S_B), \ |
| QLF2(X , S_B), \ |
| } |
| |
| /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */ |
| #define QL_UMOV \ |
| { \ |
| QLF2(W , S_H), \ |
| QLF2(W , S_S), \ |
| QLF2(X , S_D), \ |
| QLF2(W , S_B), \ |
| } |
| |
| /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */ |
| #define QL_MOV \ |
| { \ |
| QLF2(W , S_S), \ |
| QLF2(X , S_D), \ |
| } |
| |
| /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */ |
| #define QL_V2SAME \ |
| { \ |
| QLF2(V_8B , V_8B ), \ |
| QLF2(V_16B, V_16B), \ |
| QLF2(V_4H , V_4H ), \ |
| QLF2(V_8H , V_8H ), \ |
| QLF2(V_2S , V_2S ), \ |
| QLF2(V_4S , V_4S ), \ |
| QLF2(V_2D , V_2D ), \ |
| } |
| |
| /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */ |
| #define QL_V2SAMES \ |
| { \ |
| QLF2(V_2S , V_2S ), \ |
| QLF2(V_4S , V_4S ), \ |
| } |
| |
| /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */ |
| #define QL_V2SAMEBH \ |
| { \ |
| QLF2(V_8B , V_8B ), \ |
| QLF2(V_16B, V_16B), \ |
| QLF2(V_4H , V_4H ), \ |
| QLF2(V_8H , V_8H ), \ |
| } |
| |
| /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */ |
| #define QL_V2SAMESD \ |
| { \ |
| QLF2(V_2S , V_2S ), \ |
| QLF2(V_4S , V_4S ), \ |
| QLF2(V_2D , V_2D ), \ |
| } |
| |
| /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */ |
| #define QL_V2SAMEBHS \ |
| { \ |
| QLF2(V_8B , V_8B ), \ |
| QLF2(V_16B, V_16B), \ |
| QLF2(V_4H , V_4H ), \ |
| QLF2(V_8H , V_8H ), \ |
| QLF2(V_2S , V_2S ), \ |
| QLF2(V_4S , V_4S ), \ |
| } |
| |
| /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */ |
| #define QL_V2SAMEH \ |
| { \ |
| QLF2 (V_4H, V_4H), \ |
| QLF2 (V_8H, V_8H), \ |
| } |
| |
| /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ |
| #define QL_V2SAMEB \ |
| { \ |
| QLF2(V_8B , V_8B ), \ |
| QLF2(V_16B, V_16B), \ |
| } |
| |
| /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */ |
| #define QL_V2PAIRWISELONGBHS \ |
| { \ |
| QLF2(V_4H , V_8B ), \ |
| QLF2(V_8H , V_16B), \ |
| QLF2(V_2S , V_4H ), \ |
| QLF2(V_4S , V_8H ), \ |
| QLF2(V_1D , V_2S ), \ |
| QLF2(V_2D , V_4S ), \ |
| } |
| |
| /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ |
| #define QL_V2LONGBHS \ |
| { \ |
| QLF2(V_8H , V_8B ), \ |
| QLF2(V_4S , V_4H ), \ |
| QLF2(V_2D , V_2S ), \ |
| } |
| |
| /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ |
| #define QL_V2LONGBHS2 \ |
| { \ |
| QLF2(V_8H , V_16B), \ |
| QLF2(V_4S , V_8H ), \ |
| QLF2(V_2D , V_4S ), \ |
| } |
| |
| /* */ |
| #define QL_V3SAME \ |
| { \ |
| QLF3(V_8B , V_8B , V_8B ), \ |
| QLF3(V_16B, V_16B, V_16B), \ |
| QLF3(V_4H , V_4H , V_4H ), \ |
| QLF3(V_8H , V_8H , V_8H ), \ |
| QLF3(V_2S , V_2S , V_2S ), \ |
| QLF3(V_4S , V_4S , V_4S ), \ |
| QLF3(V_2D , V_2D , V_2D ) \ |
| } |
| |
| /* e.g. SHADD. */ |
| #define QL_V3SAMEBHS \ |
| { \ |
| QLF3(V_8B , V_8B , V_8B ), \ |
| QLF3(V_16B, V_16B, V_16B), \ |
| QLF3(V_4H , V_4H , V_4H ), \ |
| QLF3(V_8H , V_8H , V_8H ), \ |
| QLF3(V_2S , V_2S , V_2S ), \ |
| QLF3(V_4S , V_4S , V_4S ), \ |
| } |
| |
| /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ |
| #define QL_V2NARRS \ |
| { \ |
| QLF2(V_2S , V_2D ), \ |
| } |
| |
| /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ |
| #define QL_V2NARRS2 \ |
| { \ |
| QLF2(V_4S , V_2D ), \ |
| } |
| |
| /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ |
| #define QL_V2NARRHS \ |
| { \ |
| QLF2(V_4H , V_4S ), \ |
| QLF2(V_2S , V_2D ), \ |
| } |
| |
| /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ |
| #define QL_V2NARRHS2 \ |
| { \ |
| QLF2(V_8H , V_4S ), \ |
| QLF2(V_4S , V_2D ), \ |
| } |
| |
| /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ |
| #define QL_V2LONGHS \ |
| { \ |
| QLF2(V_4S , V_4H ), \ |
| QLF2(V_2D , V_2S ), \ |
| } |
| |
| /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ |
| #define QL_V2LONGHS2 \ |
| { \ |
| QLF2(V_4S , V_8H ), \ |
| QLF2(V_2D , V_4S ), \ |
| } |
| |
| /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ |
| #define QL_V2NARRBHS \ |
| { \ |
| QLF2(V_8B , V_8H ), \ |
| QLF2(V_4H , V_4S ), \ |
| QLF2(V_2S , V_2D ), \ |
| } |
| |
| /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ |
| #define QL_V2NARRBHS2 \ |
| { \ |
| QLF2(V_16B, V_8H ), \ |
| QLF2(V_8H , V_4S ), \ |
| QLF2(V_4S , V_2D ), \ |
| } |
| |
| /* e.g. ORR. */ |
| #define QL_V2SAMEB \ |
| { \ |
| QLF2(V_8B , V_8B ), \ |
| QLF2(V_16B, V_16B), \ |
| } |
| |
| /* e.g. AESE. */ |
| #define QL_V2SAME16B \ |
| { \ |
| QLF2(V_16B, V_16B), \ |
| } |
| |
| /* e.g. SHA1SU1. */ |
| #define QL_V2SAME4S \ |
| { \ |
| QLF2(V_4S, V_4S), \ |
| } |
| |
| /* e.g. SHA1SU0. */ |
| #define QL_V3SAME4S \ |
| { \ |
| QLF3(V_4S, V_4S, V_4S), \ |
| } |
| |
| /* e.g. SHADD. */ |
| #define QL_V3SAMEB \ |
| { \ |
| QLF3(V_8B , V_8B , V_8B ), \ |
| QLF3(V_16B, V_16B, V_16B), \ |
| } |
| |
| /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */ |
| #define QL_VEXT \ |
| { \ |
| QLF4(V_8B , V_8B , V_8B , imm_0_7), \ |
| QLF4(V_16B, V_16B, V_16B, imm_0_15), \ |
| } |
| |
| /* e.g. . */ |
| #define QL_V3SAMEHS \ |
| { \ |
| QLF3(V_4H , V_4H , V_4H ), \ |
| QLF3(V_8H , V_8H , V_8H ), \ |
| QLF3(V_2S , V_2S , V_2S ), \ |
| QLF3(V_4S , V_4S , V_4S ), \ |
| } |
| |
| /* */ |
| #define QL_V3SAMESD \ |
| { \ |
| QLF3(V_2S , V_2S , V_2S ), \ |
| QLF3(V_4S , V_4S , V_4S ), \ |
| QLF3(V_2D , V_2D , V_2D ) \ |
| } |
| |
| /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */ |
| #define QL_V3SAMEHSD_ROT \ |
| { \ |
| QLF4 (V_4H, V_4H, V_4H, NIL), \ |
| QLF4 (V_8H, V_8H, V_8H, NIL), \ |
| QLF4 (V_2S, V_2S, V_2S, NIL), \ |
| QLF4 (V_4S, V_4S, V_4S, NIL), \ |
| QLF4 (V_2D, V_2D, V_2D, NIL), \ |
| } |
| |
| /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */ |
| #define QL_V3SAMEH \ |
| { \ |
| QLF3 (V_4H , V_4H , V_4H ), \ |
| QLF3 (V_8H , V_8H , V_8H ), \ |
| } |
| |
| /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
| #define QL_V3LONGHS \ |
| { \ |
| QLF3(V_4S , V_4H , V_4H ), \ |
| QLF3(V_2D , V_2S , V_2S ), \ |
| } |
| |
| /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
| #define QL_V3LONGHS2 \ |
| { \ |
| QLF3(V_4S , V_8H , V_8H ), \ |
| QLF3(V_2D , V_4S , V_4S ), \ |
| } |
| |
| /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
| #define QL_V3LONGBHS \ |
| { \ |
| QLF3(V_8H , V_8B , V_8B ), \ |
| QLF3(V_4S , V_4H , V_4H ), \ |
| QLF3(V_2D , V_2S , V_2S ), \ |
| } |
| |
| /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ |
| #define QL_V3LONGBHS2 \ |
| { \ |
| QLF3(V_8H , V_16B , V_16B ), \ |
| QLF3(V_4S , V_8H , V_8H ), \ |
| QLF3(V_2D , V_4S , V_4S ), \ |
| } |
| |
| /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ |
| #define QL_V3WIDEBHS \ |
| { \ |
| QLF3(V_8H , V_8H , V_8B ), \ |
| QLF3(V_4S , V_4S , V_4H ), \ |
| QLF3(V_2D , V_2D , V_2S ), \ |
| } |
| |
| /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ |
| #define QL_V3WIDEBHS2 \ |
| { \ |
| QLF3(V_8H , V_8H , V_16B ), \ |
| QLF3(V_4S , V_4S , V_8H ), \ |
| QLF3(V_2D , V_2D , V_4S ), \ |
| } |
| |
| /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ |
| #define QL_V3NARRBHS \ |
| { \ |
| QLF3(V_8B , V_8H , V_8H ), \ |
| QLF3(V_4H , V_4S , V_4S ), \ |
| QLF3(V_2S , V_2D , V_2D ), \ |
| } |
| |
| /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ |
| #define QL_V3NARRBHS2 \ |
| { \ |
| QLF3(V_16B , V_8H , V_8H ), \ |
| QLF3(V_8H , V_4S , V_4S ), \ |
| QLF3(V_4S , V_2D , V_2D ), \ |
| } |
| |
| /* e.g. PMULL. */ |
| #define QL_V3LONGB \ |
| { \ |
| QLF3(V_8H , V_8B , V_8B ), \ |
| } |
| |
| /* e.g. PMULL crypto. */ |
| #define QL_V3LONGD \ |
| { \ |
| QLF3(V_1Q , V_1D , V_1D ), \ |
| } |
| |
| /* e.g. PMULL2. */ |
| #define QL_V3LONGB2 \ |
| { \ |
| QLF3(V_8H , V_16B, V_16B), \ |
| } |
| |
| /* e.g. PMULL2 crypto. */ |
| #define QL_V3LONGD2 \ |
| { \ |
| QLF3(V_1Q , V_2D , V_2D ), \ |
| } |
| |
| /* e.g. SHA1C. */ |
| #define QL_SHAUPT \ |
| { \ |
| QLF3(S_Q, S_S, V_4S), \ |
| } |
| |
| /* e.g. SHA256H2. */ |
| #define QL_SHA256UPT \ |
| { \ |
| QLF3(S_Q, S_Q, V_4S), \ |
| } |
| |
| /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */ |
| #define QL_W1_LDST_EXC \ |
| { \ |
| QLF2(W, NIL), \ |
| } |
| |
| /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */ |
| #define QL_R1NIL \ |
| { \ |
| QLF2(W, NIL), \ |
| QLF2(X, NIL), \ |
| } |
| |
| /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ |
| #define QL_W2_LDST_EXC \ |
| { \ |
| QLF3(W, W, NIL), \ |
| } |
| |
| /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */ |
| #define QL_R2_LDST_EXC \ |
| { \ |
| QLF3(W, W, NIL), \ |
| QLF3(W, X, NIL), \ |
| } |
| |
| /* e.g. LDRAA <Xt>, [<Xn|SP>{,#imm}]. */ |
| #define QL_X1NIL \ |
| { \ |
| QLF2(X, NIL), \ |
| } |
| |
| /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| #define QL_R2NIL \ |
| { \ |
| QLF3(W, W, NIL), \ |
| QLF3(X, X, NIL), \ |
| } |
| |
| /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ |
| #define QL_R4NIL \ |
| { \ |
| QLF5(W, W, W, W, NIL), \ |
| QLF5(X, X, X, X, NIL), \ |
| } |
| |
| /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ |
| #define QL_R3_LDST_EXC \ |
| { \ |
| QLF4(W, W, W, NIL), \ |
| QLF4(W, X, X, NIL), \ |
| } |
| |
| /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_FP \ |
| { \ |
| QLF2(S_B, S_B), \ |
| QLF2(S_H, S_H), \ |
| QLF2(S_S, S_S), \ |
| QLF2(S_D, S_D), \ |
| QLF2(S_Q, S_Q), \ |
| } |
| |
| /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_R \ |
| { \ |
| QLF2(W, S_S), \ |
| QLF2(X, S_D), \ |
| } |
| |
| /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_W8 \ |
| { \ |
| QLF2(W, S_B), \ |
| } |
| |
| /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_R8 \ |
| { \ |
| QLF2(W, S_B), \ |
| QLF2(X, S_B), \ |
| } |
| |
| /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_W16 \ |
| { \ |
| QLF2(W, S_H), \ |
| } |
| |
| /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_X32 \ |
| { \ |
| QLF2(X, S_S), \ |
| } |
| |
| /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_R16 \ |
| { \ |
| QLF2(W, S_H), \ |
| QLF2(X, S_H), \ |
| } |
| |
| /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ |
| #define QL_LDST_PRFM \ |
| { \ |
| QLF2(NIL, S_D), \ |
| } |
| |
| /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ |
| #define QL_LDST_PAIR_X32 \ |
| { \ |
| QLF3(X, X, S_S), \ |
| } |
| |
| /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */ |
| #define QL_LDST_PAIR_R \ |
| { \ |
| QLF3(W, W, S_S), \ |
| QLF3(X, X, S_D), \ |
| } |
| |
| /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ |
| #define QL_LDST_PAIR_FP \ |
| { \ |
| QLF3(S_S, S_S, S_S), \ |
| QLF3(S_D, S_D, S_D), \ |
| QLF3(S_Q, S_Q, S_Q), \ |
| } |
| |
| /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ |
| #define QL_SIMD_LDST \ |
| { \ |
| QLF2(V_8B, NIL), \ |
| QLF2(V_16B, NIL), \ |
| QLF2(V_4H, NIL), \ |
| QLF2(V_8H, NIL), \ |
| QLF2(V_2S, NIL), \ |
| QLF2(V_4S, NIL), \ |
| QLF2(V_2D, NIL), \ |
| } |
| |
| /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ |
| #define QL_SIMD_LDST_ANY \ |
| { \ |
| QLF2(V_8B, NIL), \ |
| QLF2(V_16B, NIL), \ |
| QLF2(V_4H, NIL), \ |
| QLF2(V_8H, NIL), \ |
| QLF2(V_2S, NIL), \ |
| QLF2(V_4S, NIL), \ |
| QLF2(V_1D, NIL), \ |
| QLF2(V_2D, NIL), \ |
| } |
| |
| /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */ |
| #define QL_SIMD_LDSTONE \ |
| { \ |
| QLF2(S_B, NIL), \ |
| QLF2(S_H, NIL), \ |
| QLF2(S_S, NIL), \ |
| QLF2(S_D, NIL), \ |
| } |
| |
| /* e.g. ADDV <V><d>, <Vn>.<T>. */ |
| #define QL_XLANES \ |
| { \ |
| QLF2(S_B, V_8B), \ |
| QLF2(S_B, V_16B), \ |
| QLF2(S_H, V_4H), \ |
| QLF2(S_H, V_8H), \ |
| QLF2(S_S, V_4S), \ |
| } |
| |
| /* e.g. FMINV <V><d>, <Vn>.<T>. */ |
| #define QL_XLANES_FP \ |
| { \ |
| QLF2(S_S, V_4S), \ |
| } |
| |
| /* e.g. FMINV <V><d>, <Vn>.<T>. */ |
| #define QL_XLANES_FP_H \ |
| { \ |
| QLF2 (S_H, V_4H), \ |
| QLF2 (S_H, V_8H), \ |
| } |
| |
| /* e.g. SADDLV <V><d>, <Vn>.<T>. */ |
| #define QL_XLANES_L \ |
| { \ |
| QLF2(S_H, V_8B), \ |
| QLF2(S_H, V_16B), \ |
| QLF2(S_S, V_4H), \ |
| QLF2(S_S, V_8H), \ |
| QLF2(S_D, V_4S), \ |
| } |
| |
| /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */ |
| #define QL_ELEMENT \ |
| { \ |
| QLF3(V_4H, V_4H, S_H), \ |
| QLF3(V_8H, V_8H, S_H), \ |
| QLF3(V_2S, V_2S, S_S), \ |
| QLF3(V_4S, V_4S, S_S), \ |
| } |
| |
| /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ |
| #define QL_ELEMENT_L \ |
| { \ |
| QLF3(V_4S, V_4H, S_H), \ |
| QLF3(V_2D, V_2S, S_S), \ |
| } |
| |
| /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ |
| #define QL_ELEMENT_L2 \ |
| { \ |
| QLF3(V_4S, V_8H, S_H), \ |
| QLF3(V_2D, V_4S, S_S), \ |
| } |
| |
| /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ |
| #define QL_ELEMENT_FP \ |
| { \ |
| QLF3(V_2S, V_2S, S_S), \ |
| QLF3(V_4S, V_4S, S_S), \ |
| QLF3(V_2D, V_2D, S_D), \ |
| } |
| |
| /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ |
| #define QL_ELEMENT_FP_H \ |
| { \ |
| QLF3 (V_4H, V_4H, S_H), \ |
| QLF3 (V_8H, V_8H, S_H), \ |
| } |
| |
| /* e.g. FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>. */ |
| #define QL_ELEMENT_ROT \ |
| { \ |
| QLF4 (V_4H, V_4H, S_H, NIL), \ |
| QLF4 (V_8H, V_8H, S_H, NIL), \ |
| QLF4 (V_4S, V_4S, S_S, NIL), \ |
| } |
| |
| /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ |
| #define QL_SIMD_IMM_S0W \ |
| { \ |
| QLF2(V_2S, LSL), \ |
| QLF2(V_4S, LSL), \ |
| } |
| |
| /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */ |
| #define QL_SIMD_IMM_S1W \ |
| { \ |
| QLF2(V_2S, MSL), \ |
| QLF2(V_4S, MSL), \ |
| } |
| |
| /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */ |
| #define QL_SIMD_IMM_S0H \ |
| { \ |
| QLF2(V_4H, LSL), \ |
| QLF2(V_8H, LSL), \ |
| } |
| |
| /* e.g. FMOV <Vd>.<T>, #<imm>. */ |
| #define QL_SIMD_IMM_S \ |
| { \ |
| QLF2(V_2S, NIL), \ |
| QLF2(V_4S, NIL), \ |
| } |
| |
| /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ |
| #define QL_SIMD_IMM_B \ |
| { \ |
| QLF2(V_8B, LSL), \ |
| QLF2(V_16B, LSL), \ |
| } |
| /* e.g. MOVI <Dd>, #<imm>. */ |
| #define QL_SIMD_IMM_D \ |
| { \ |
| QLF2(S_D, NIL), \ |
| } |
| |
| /* e.g. FMOV <Vd>.<T>, #<imm>. */ |
| #define QL_SIMD_IMM_H \ |
| { \ |
| QLF2 (V_4H, NIL), \ |
| QLF2 (V_8H, NIL), \ |
| } |
| |
| /* e.g. MOVI <Vd>.2D, #<imm>. */ |
| #define QL_SIMD_IMM_V2D \ |
| { \ |
| QLF2(V_2D, NIL), \ |
| } |
| |
| /* The naming convention for SVE macros is: |
| |
| OP_SVE_<operands>[_<sizes>]* |
| |
| <operands> contains one character per operand, using the following scheme: |
| |
| - U: the operand is unqualified (NIL). |
| |
| - [BHSD]: the operand has a S_[BHSD] qualifier and the choice of |
| qualifier is the same for all variants. This is used for both |
| .[BHSD] suffixes on an SVE predicate or vector register and |
| scalar FPRs of the form [BHSD]<number>. |
| |
| - [WX]: the operand has a [WX] qualifier and the choice of qualifier |
| is the same for all variants. |
| |
| - [ZM]: the operand has a /[ZM] suffix and the choice of suffix |
| is the same for all variants. |
| |
| - V: the operand has a S_[BHSD] qualifier and the choice of qualifier |
| is not the same for all variants. |
| |
| - R: the operand has a [WX] qualifier and the choice of qualifier is |
| not the same for all variants. |
| |
| - P: the operand has a /[ZM] suffix and the choice of suffix is not |
| the same for all variants. |
| |
| The _<sizes>, if present, give the subset of [BHSD] that are accepted |
| by the V entries in <operands>. */ |
| #define OP_SVE_B \ |
| { \ |
| QLF1(S_B), \ |
| } |
| #define OP_SVE_BB \ |
| { \ |
| QLF2(S_B,S_B), \ |
| } |
| #define OP_SVE_BBBU \ |
| { \ |
| QLF4(S_B,S_B,S_B,NIL), \ |
| } |
| #define OP_SVE_BMB \ |
| { \ |
| QLF3(S_B,P_M,S_B), \ |
| } |
| #define OP_SVE_BPB \ |
| { \ |
| QLF3(S_B,P_Z,S_B), \ |
| QLF3(S_B,P_M,S_B), \ |
| } |
| #define OP_SVE_BUB \ |
| { \ |
| QLF3(S_B,NIL,S_B), \ |
| } |
| #define OP_SVE_BUBB \ |
| { \ |
| QLF4(S_B,NIL,S_B,S_B), \ |
| } |
| #define OP_SVE_BUU \ |
| { \ |
| QLF3(S_B,NIL,NIL), \ |
| } |
| #define OP_SVE_BZ \ |
| { \ |
| QLF2(S_B,P_Z), \ |
| } |
| #define OP_SVE_BZB \ |
| { \ |
| QLF3(S_B,P_Z,S_B), \ |
| } |
| #define OP_SVE_BZBB \ |
| { \ |
| QLF4(S_B,P_Z,S_B,S_B), \ |
| } |
| #define OP_SVE_BZU \ |
| { \ |
| QLF3(S_B,P_Z,NIL), \ |
| } |
| #define OP_SVE_DD \ |
| { \ |
| QLF2(S_D,S_D), \ |
| } |
| #define OP_SVE_DDD \ |
| { \ |
| QLF3(S_D,S_D,S_D), \ |
| } |
| #define OP_SVE_DMD \ |
| { \ |
| QLF3(S_D,P_M,S_D), \ |
| } |
| #define OP_SVE_DMH \ |
| { \ |
| QLF3(S_D,P_M,S_H), \ |
| } |
| #define OP_SVE_DMS \ |
| { \ |
| QLF3(S_D,P_M,S_S), \ |
| } |
| #define OP_SVE_DU \ |
| { \ |
| QLF2(S_D,NIL), \ |
| } |
| #define OP_SVE_DUD \ |
| { \ |
| QLF3(S_D,NIL,S_D), \ |
| } |
| #define OP_SVE_DUU \ |
| { \ |
| QLF3(S_D,NIL,NIL), \ |
| } |
| #define OP_SVE_DUV_BHS \ |
| { \ |
| QLF3(S_D,NIL,S_B), \ |
| QLF3(S_D,NIL,S_H), \ |
| QLF3(S_D,NIL,S_S), \ |
| } |
| #define OP_SVE_DUV_BHSD \ |
| { \ |
| QLF3(S_D,NIL,S_B), \ |
| QLF3(S_D,NIL,S_H), \ |
| QLF3(S_D,NIL,S_S), \ |
| QLF3(S_D,NIL,S_D), \ |
| } |
| #define OP_SVE_DZD \ |
| { \ |
| QLF3(S_D,P_Z,S_D), \ |
| } |
| #define OP_SVE_DZU \ |
| { \ |
| QLF3(S_D,P_Z,NIL), \ |
| } |
| #define OP_SVE_HB \ |
| { \ |
| QLF2(S_H,S_B), \ |
| } |
| #define OP_SVE_HMD \ |
| { \ |
| QLF3(S_H,P_M,S_D), \ |
| } |
| #define OP_SVE_HMS \ |
| { \ |
| QLF3(S_H,P_M,S_S), \ |
| } |
| #define OP_SVE_HU \ |
| { \ |
| QLF2(S_H,NIL), \ |
| } |
| #define OP_SVE_HUU \ |
| { \ |
| QLF3(S_H,NIL,NIL), \ |
| } |
| #define OP_SVE_HZU \ |
| { \ |
| QLF3(S_H,P_Z,NIL), \ |
| } |
| #define OP_SVE_RR \ |
| { \ |
| QLF2(W,W), \ |
| QLF2(X,X), \ |
| } |
| #define OP_SVE_RURV_BHSD \ |
| { \ |
| QLF4(W,NIL,W,S_B), \ |
| QLF4(W,NIL,W,S_H), \ |
| QLF4(W,NIL,W,S_S), \ |
| QLF4(X,NIL,X,S_D), \ |
| } |
| #define OP_SVE_RUV_BHSD \ |
| { \ |
| QLF3(W,NIL,S_B), \ |
| QLF3(W,NIL,S_H), \ |
| QLF3(W,NIL,S_S), \ |
| QLF3(X,NIL,S_D), \ |
| } |
| #define OP_SVE_SMD \ |
| { \ |
| QLF3(S_S,P_M,S_D), \ |
| } |
| #define OP_SVE_SMH \ |
| { \ |
| QLF3(S_S,P_M,S_H), \ |
| } |
| #define OP_SVE_SMS \ |
| { \ |
| QLF3(S_S,P_M,S_S), \ |
| } |
| #define OP_SVE_SU \ |
| { \ |
| QLF2(S_S,NIL), \ |
| } |
| #define OP_SVE_SUS \ |
| { \ |
| QLF3(S_S,NIL,S_S), \ |
| } |
| #define OP_SVE_SUU \ |
| { \ |
| QLF3(S_S,NIL,NIL), \ |
| } |
| #define OP_SVE_SZS \ |
| { \ |
| QLF3(S_S,P_Z,S_S), \ |
| } |
| #define OP_SVE_SZU \ |
| { \ |
| QLF3(S_S,P_Z,NIL), \ |
| } |
| #define OP_SVE_UB \ |
| { \ |
| QLF2(NIL,S_B), \ |
| } |
| #define OP_SVE_UUD \ |
| { \ |
| QLF3(NIL,NIL,S_D), \ |
| } |
| #define OP_SVE_UUS \ |
| { \ |
| QLF3(NIL,NIL,S_S), \ |
| } |
| #define OP_SVE_VMR_BHSD \ |
| { \ |
| QLF3(S_B,P_M,W), \ |
| QLF3(S_H,P_M,W), \ |
| QLF3(S_S,P_M,W), \ |
| QLF3(S_D,P_M,X), \ |
| } |
| #define OP_SVE_VMU_SD \ |
| { \ |
| QLF3(S_S,P_M,NIL), \ |
| QLF3(S_D,P_M,NIL), \ |
| } |
| #define OP_SVE_VMVD_BHS \ |
| { \ |
| QLF4(S_B,P_M,S_B,S_D), \ |
| QLF4(S_H,P_M,S_H,S_D), \ |
| QLF4(S_S,P_M,S_S,S_D), \ |
| } |
| #define OP_SVE_VMVU_BHSD \ |
| { \ |
| QLF4(S_B,P_M,S_B,NIL), \ |
| QLF4(S_H,P_M,S_H,NIL), \ |
| QLF4(S_S,P_M,S_S,NIL), \ |
| QLF4(S_D,P_M,S_D,NIL), \ |
| } |
| #define OP_SVE_VMVU_SD \ |
| { \ |
| QLF4(S_S,P_M,S_S,NIL), \ |
| QLF4(S_D,P_M,S_D,NIL), \ |
| } |
| #define OP_SVE_VMVV_BHSD \ |
| { \ |
| QLF4(S_B,P_M,S_B,S_B), \ |
| QLF4(S_H,P_M,S_H,S_H), \ |
| QLF4(S_S,P_M,S_S,S_S), \ |
| QLF4(S_D,P_M,S_D,S_D), \ |
| } |
| #define OP_SVE_VMVV_SD \ |
| { \ |
| QLF4(S_S,P_M,S_S,S_S), \ |
| QLF4(S_D,P_M,S_D,S_D), \ |
| } |
| #define OP_SVE_VMV_BHSD \ |
| { \ |
| QLF3(S_B,P_M,S_B), \ |
| QLF3(S_H,P_M,S_H), \ |
| QLF3(S_S,P_M,S_S), \ |
| QLF3(S_D,P_M,S_D), \ |
| } |
| #define OP_SVE_VMV_HSD \ |
| { \ |
| QLF3(S_H,P_M,S_H), \ |
| QLF3(S_S,P_M,S_S), \ |
| QLF3(S_D,P_M,S_D), \ |
| } |
| #define OP_SVE_VMV_SD \ |
| { \ |
| QLF3(S_S,P_M,S_S), \ |
| QLF3(S_D,P_M,S_D), \ |
| } |
| #define OP_SVE_VM_SD \ |
| { \ |
| QLF2(S_S,P_M), \ |
| QLF2(S_D,P_M), \ |
| } |
| #define OP_SVE_VPU_BHSD \ |
| { \ |
| QLF3(S_B,P_Z,NIL), \ |
| QLF3(S_B,P_M,NIL), \ |
| QLF3(S_H,P_Z,NIL), \ |
| QLF3(S_H,P_M,NIL), \ |
| QLF3(S_S,P_Z,NIL), \ |
| QLF3(S_S,P_M,NIL), \ |
| QLF3(S_D,P_Z,NIL), \ |
| QLF3(S_D,P_M,NIL), \ |
| } |
| #define OP_SVE_VPV_BHSD \ |
| { \ |
| QLF3(S_B,P_Z,S_B), \ |
| QLF3(S_B,P_M,S_B), \ |
| QLF3(S_H,P_Z,S_H), \ |
| QLF3(S_H,P_M,S_H), \ |
| QLF3(S_S,P_Z,S_S), \ |
| QLF3(S_S,P_M,S_S), \ |
| QLF3(S_D,P_Z,S_D), \ |
| QLF3(S_D,P_M,S_D), \ |
| } |
| #define OP_SVE_VRR_BHSD \ |
| { \ |
| QLF3(S_B,W,W), \ |
| QLF3(S_H,W,W), \ |
| QLF3(S_S,W,W), \ |
| QLF3(S_D,X,X), \ |
| } |
| #define OP_SVE_VRU_BHSD \ |
| { \ |
| QLF3(S_B,W,NIL), \ |
| QLF3(S_H,W,NIL), \ |
| QLF3(S_S,W,NIL), \ |
| QLF3(S_D,X,NIL), \ |
| } |
| #define OP_SVE_VR_BHSD \ |
| { \ |
| QLF2(S_B,W), \ |
| QLF2(S_H,W), \ |
| QLF2(S_S,W), \ |
| QLF2(S_D,X), \ |
| } |
| #define OP_SVE_VUR_BHSD \ |
| { \ |
| QLF3(S_B,NIL,W), \ |
| QLF3(S_H,NIL,W), \ |
| QLF3(S_S,NIL,W), \ |
| QLF3(S_D,NIL,X), \ |
| } |
| #define OP_SVE_VUU_BHSD \ |
| { \ |
| QLF3(S_B,NIL,NIL), \ |
| QLF3(S_H,NIL,NIL), \ |
| QLF3(S_S,NIL,NIL), \ |
| QLF3(S_D,NIL,NIL), \ |
| } |
| #define OP_SVE_VUVV_BHSD \ |
| { \ |
| QLF4(S_B,NIL,S_B,S_B), \ |
| QLF4(S_H,NIL,S_H,S_H), \ |
| QLF4(S_S,NIL,S_S,S_S), \ |
| QLF4(S_D,NIL,S_D,S_D), \ |
| } |
| #define OP_SVE_VUVV_SD \ |
| { \ |
| QLF4(S_S,NIL,S_S,S_S), \ |
| QLF4(S_D,NIL,S_D,S_D), \ |
| } |
| #define OP_SVE_VUV_BHSD \ |
| { \ |
| QLF3(S_B,NIL,S_B), \ |
| QLF3(S_H,NIL,S_H), \ |
| QLF3(S_S,NIL,S_S), \ |
| QLF3(S_D,NIL,S_D), \ |
| } |
| #define OP_SVE_VUV_SD \ |
| { \ |
| QLF3(S_S,NIL,S_S), \ |
| QLF3(S_D,NIL,S_D), \ |
| } |
| #define OP_SVE_VU_BHSD \ |
| { \ |
| QLF2(S_B,NIL), \ |
| QLF2(S_H,NIL), \ |
| QLF2(S_S,NIL), \ |
| QLF2(S_D,NIL), \ |
| } |
| #define OP_SVE_VU_HSD \ |
| { \ |
| QLF2(S_H,NIL), \ |
| QLF2(S_S,NIL), \ |
| QLF2(S_D,NIL), \ |
| } |
| #define OP_SVE_VU_SD \ |
| { \ |
| QLF2(S_S,NIL), \ |
| QLF2(S_D,NIL), \ |
| } |
| #define OP_SVE_VVD_BHS \ |
| { \ |
| QLF3(S_B,S_B,S_D), \ |
| QLF3(S_H,S_H,S_D), \ |
| QLF3(S_S,S_S,S_D), \ |
| } |
| #define OP_SVE_VVU_BHSD \ |
| { \ |
| QLF3(S_B,S_B,NIL), \ |
| QLF3(S_H,S_H,NIL), \ |
| QLF3(S_S,S_S,NIL), \ |
| QLF3(S_D,S_D,NIL), \ |
| } |
| #define OP_SVE_VVVU_SD \ |
| { \ |
| QLF4(S_S,S_S,S_S,NIL), \ |
| QLF4(S_D,S_D,S_D,NIL), \ |
| } |
| #define OP_SVE_VVV_BHSD \ |
| { \ |
| QLF3(S_B,S_B,S_B), \ |
| QLF3(S_H,S_H,S_H), \ |
| QLF3(S_S,S_S,S_S), \ |
| QLF3(S_D,S_D,S_D), \ |
| } |
| #define OP_SVE_VVV_SD \ |
| { \ |
| QLF3(S_S,S_S,S_S), \ |
| QLF3(S_D,S_D,S_D), \ |
| } |
| #define OP_SVE_VV_BHSD \ |
| { \ |
| QLF2(S_B,S_B), \ |
| QLF2(S_H,S_H), \ |
| QLF2(S_S,S_S), \ |
| QLF2(S_D,S_D), \ |
| } |
| #define OP_SVE_VV_HSD_BHS \ |
| { \ |
| QLF2(S_H,S_B), \ |
| QLF2(S_S,S_H), \ |
| QLF2(S_D,S_S), \ |
| } |
| #define OP_SVE_VV_SD \ |
| { \ |
| QLF2(S_S,S_S), \ |
| QLF2(S_D,S_D), \ |
| } |
| #define OP_SVE_VWW_BHSD \ |
| { \ |
| QLF3(S_B,W,W), \ |
| QLF3(S_H,W,W), \ |
| QLF3(S_S,W,W), \ |
| QLF3(S_D,W,W), \ |
| } |
| #define OP_SVE_VXX_BHSD \ |
| { \ |
| QLF3(S_B,X,X), \ |
| QLF3(S_H,X,X), \ |
| QLF3(S_S,X,X), \ |
| QLF3(S_D,X,X), \ |
| } |
| #define OP_SVE_VZVD_BHS \ |
| { \ |
| QLF4(S_B,P_Z,S_B,S_D), \ |
| QLF4(S_H,P_Z,S_H,S_D), \ |
| QLF4(S_S,P_Z,S_S,S_D), \ |
| } |
| #define OP_SVE_VZVU_BHSD \ |
| { \ |
| QLF4(S_B,P_Z,S_B,NIL), \ |
| QLF4(S_H,P_Z,S_H,NIL), \ |
| QLF4(S_S,P_Z,S_S,NIL), \ |
| QLF4(S_D,P_Z,S_D,NIL), \ |
| } |
| #define OP_SVE_VZVV_BHSD \ |
| { \ |
| QLF4(S_B,P_Z,S_B,S_B), \ |
| QLF4(S_H,P_Z,S_H,S_H), \ |
| QLF4(S_S,P_Z,S_S,S_S), \ |
| QLF4(S_D,P_Z,S_D,S_D), \ |
| } |
| #define OP_SVE_VZVV_SD \ |
| { \ |
| QLF4(S_S,P_Z,S_S,S_S), \ |
| QLF4(S_D,P_Z,S_D,S_D), \ |
| } |
| #define OP_SVE_VZV_SD \ |
| { \ |
| QLF3(S_S,P_Z,S_S), \ |
| QLF3(S_D,P_Z,S_D), \ |
| } |
| #define OP_SVE_V_SD \ |
| { \ |
| QLF1(S_S), \ |
| QLF1(S_D), \ |
| } |
| #define OP_SVE_WU \ |
| { \ |
| QLF2(W,NIL), \ |
| } |
| #define OP_SVE_WV_BHSD \ |
| { \ |
| QLF2(W,S_B), \ |
| QLF2(W,S_H), \ |
| QLF2(W,S_S), \ |
| QLF2(W,S_D), \ |
| } |
| #define OP_SVE_XU \ |
| { \ |
| QLF2(X,NIL), \ |
| } |
| #define OP_SVE_XUV_BHSD \ |
| { \ |
| QLF3(X,NIL,S_B), \ |
| QLF3(X,NIL,S_H), \ |
| QLF3(X,NIL,S_S), \ |
| QLF3(X,NIL,S_D), \ |
| } |
| #define OP_SVE_XVW_BHSD \ |
| { \ |
| QLF3(X,S_B,W), \ |
| QLF3(X,S_H,W), \ |
| QLF3(X,S_S,W), \ |
| QLF3(X,S_D,W), \ |
| } |
| #define OP_SVE_XV_BHSD \ |
| { \ |
| QLF2(X,S_B), \ |
| QLF2(X,S_H), \ |
| QLF2(X,S_S), \ |
| QLF2(X,S_D), \ |
| } |
| #define OP_SVE_XWU \ |
| { \ |
| QLF3(X,W,NIL), \ |
| } |
| #define OP_SVE_XXU \ |
| { \ |
| QLF3(X,X,NIL), \ |
| } |
| |
| /* Opcode table. */ |
| |
| static const aarch64_feature_set aarch64_feature_v8 = |
| AARCH64_FEATURE (AARCH64_FEATURE_V8, 0); |
| static const aarch64_feature_set aarch64_feature_fp = |
| AARCH64_FEATURE (AARCH64_FEATURE_FP, 0); |
| static const aarch64_feature_set aarch64_feature_simd = |
| AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0); |
| static const aarch64_feature_set aarch64_feature_crypto = |
| AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0); |
| static const aarch64_feature_set aarch64_feature_crc = |
| AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); |
| static const aarch64_feature_set aarch64_feature_lse = |
| AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); |
| static const aarch64_feature_set aarch64_feature_lor = |
| AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); |
| static const aarch64_feature_set aarch64_feature_rdma = |
| AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); |
| static const aarch64_feature_set aarch64_feature_ras = |
| AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0); |
| static const aarch64_feature_set aarch64_feature_v8_2 = |
| AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0); |
| static const aarch64_feature_set aarch64_feature_fp_f16 = |
| AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); |
| static const aarch64_feature_set aarch64_feature_simd_f16 = |
| AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0); |
| static const aarch64_feature_set aarch64_feature_stat_profile = |
| AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0); |
| static const aarch64_feature_set aarch64_feature_sve = |
| AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0); |
| static const aarch64_feature_set aarch64_feature_v8_3 = |
| AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0); |
| static const aarch64_feature_set aarch64_feature_fp_v8_3 = |
| AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0); |
| static const aarch64_feature_set aarch64_feature_simd_v8_3 = |
| AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0); |
| |
| #define CORE &aarch64_feature_v8 |
| #define FP &aarch64_feature_fp |
| #define SIMD &aarch64_feature_simd |
| #define CRYPTO &aarch64_feature_crypto |
| #define CRC &aarch64_feature_crc |
| #define LSE &aarch64_feature_lse |
| #define LOR &aarch64_feature_lor |
| #define RDMA &aarch64_feature_rdma |
| #define FP_F16 &aarch64_feature_fp_f16 |
| #define SIMD_F16 &aarch64_feature_simd_f16 |
| #define RAS &aarch64_feature_ras |
| #define STAT_PROFILE &aarch64_feature_stat_profile |
| #define ARMV8_2 &aarch64_feature_v8_2 |
| #define SVE &aarch64_feature_sve |
| #define ARMV8_3 &aarch64_feature_v8_3 |
| #define FP_V8_3 &aarch64_feature_fp_v8_3 |
| #define SIMD_V8_3 &aarch64_feature_simd_v8_3 |
| |
| #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL } |
| #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, NULL } |
| #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, NULL } |
| #define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, NULL } |
| #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, NULL } |
| #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, NULL } |
| #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, NULL } |
| #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, NULL } |
| #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, NULL } |
| #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, NULL } |
| #define V8_2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2, OPS, QUALS, FLAGS, 0, NULL } |
| #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ |
| { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ |
| FLAGS | F_STRICT, TIED, NULL } |
| #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ |
| { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL } |
| |
| struct aarch64_opcode aarch64_opcode_table[] = |
| { |
| /* Add/subtract (with carry). */ |
| CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
| CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), |
| CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), |
| CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), |
| /* Add/subtract (extended register). */ |
| CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), |
| CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), |
| CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), |
| CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), |
| /* Add/subtract (immediate). */ |
| CORE_INSN ("add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), |
| CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), |
| CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF), |
| CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), |
| /* Add/subtract (shifted register). */ |
| CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), |
| CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
| CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
| CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), |
| CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
| CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), |
| /* AdvSIMD across lanes. */ |
| SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |
| SIMD_INSN ("smaxv", 0x0e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), |
| SIMD_INSN ("sminv", 0x0e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), |
| SIMD_INSN ("addv", 0x0e31b800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), |
| SIMD_INSN ("uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), |
| SIMD_INSN ("umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), |
| SIMD_INSN ("uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), |
| SIMD_INSN ("fmaxnmv",0x2e30c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| SF16_INSN ("fmaxnmv",0x0e30c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| SIMD_INSN ("fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| SF16_INSN ("fmaxv", 0x0e30f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| SIMD_INSN ("fminnmv",0x2eb0c800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| SF16_INSN ("fminnmv",0x0eb0c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| SIMD_INSN ("fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), |
| SF16_INSN ("fminv", 0x0eb0f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), |
| /* AdvSIMD three different. */ |
| SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), |
| SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), |
| SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), |
| SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), |
| SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), |
| SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), |
| SIMD_INSN ("subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), |
| SIMD_INSN ("sqdmlal2",0x4e209000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), |
| SIMD_INSN ("smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), |
| SIMD_INSN ("sqdmlsl2",0x4e20b000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), |
| SIMD_INSN ("smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), |
| SIMD_INSN ("sqdmull2",0x4e20d000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), |
| SIMD_INSN ("pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0), |
| CRYP_INSN ("pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0), |
| SIMD_INSN ("pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0), |
| CRYP_INSN ("pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0), |
| SIMD_INSN ("uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), |
| SIMD_INSN ("uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), |
| SIMD_INSN ("usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), |
| SIMD_INSN ("usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), |
| SIMD_INSN ("raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), |
| SIMD_INSN ("raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), |
| SIMD_INSN ("rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), |
| SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), |
| /* AdvSIMD vector x indexed element. */ |
| SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), |
| SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), |
| SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), |
| SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), |
| SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), |
| SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), |
| SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), |
| RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), |
| {"fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, SIMD_V8_3, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ, 0, NULL}, |
| /* AdvSIMD EXT. */ |
| SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), |
| /* AdvSIMD modified immediate. */ |
| SIMD_INSN ("movi", 0x0f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| SIMD_INSN ("orr", 0x0f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| SIMD_INSN ("movi", 0x0f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), |
| SIMD_INSN ("orr", 0x0f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), |
| SIMD_INSN ("movi", 0x0f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), |
| SIMD_INSN ("movi", 0x0f00e400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ), |
| SIMD_INSN ("fmov", 0x0f00f400, 0xbff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ), |
| SF16_INSN ("fmov", 0x0f00fc00, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ), |
| SIMD_INSN ("mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| SIMD_INSN ("bic", 0x2f001400, 0xbff89c00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), |
| SIMD_INSN ("mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), |
| SIMD_INSN ("bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), |
| SIMD_INSN ("mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), |
| SIMD_INSN ("movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ), |
| SIMD_INSN ("movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ), |
| SIMD_INSN ("fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ), |
| /* AdvSIMD copy. */ |
| SIMD_INSN ("dup", 0x0e000400, 0xbfe0fc00, asimdins, 0, OP2 (Vd, En), QL_DUP_VX, F_T), |
| SIMD_INSN ("dup", 0x0e000c00, 0xbfe0fc00, asimdins, 0, OP2 (Vd, Rn), QL_DUP_VR, F_T), |
| SIMD_INSN ("smov",0x0e002c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q), |
| SIMD_INSN ("umov",0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q), |
| SIMD_INSN ("mov", 0x0e003c00, 0xbfe0fc00, asimdins, 0, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q), |
| SIMD_INSN ("ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS), |
| SIMD_INSN ("mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS), |
| SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS), |
| SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_ALIAS), |
| /* AdvSIMD two-reg misc. */ |
| SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), |
| SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), |
| SIMD_INSN ("suqadd",0x0e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("cls", 0x0e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("cnt", 0x0e205800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), |
| SIMD_INSN ("sadalp",0x0e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), |
| SIMD_INSN ("sqabs", 0x0e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("cmgt", 0x0e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("cmeq", 0x0e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("cmlt", 0x0e20a800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("abs", 0x0e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("xtn", 0x0e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), |
| SIMD_INSN ("xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), |
| SIMD_INSN ("sqxtn2",0x4e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("fcvtn", 0x0e216800, 0xffbffc00, asimdmisc, OP_FCVTN, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC), |
| SIMD_INSN ("fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC), |
| SIMD_INSN ("fcvtl", 0x0e217800, 0xffbffc00, asimdmisc, OP_FCVTL, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC), |
| SIMD_INSN ("fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC), |
| SIMD_INSN ("frintn", 0x0e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frintn", 0x0e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("frintm", 0x0e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frintm", 0x0e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtns", 0x0e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtns", 0x0e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtms", 0x0e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtms", 0x0e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtas", 0x0e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtas", 0x0e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("scvtf", 0x0e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("scvtf", 0x0e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmgt", 0x0ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmgt", 0x0ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmeq", 0x0ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmeq", 0x0ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmlt", 0x0ea0e800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmlt", 0x0ef8e800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fabs", 0x0ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fabs", 0x0ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("frintp", 0x0ea18800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frintp", 0x0ef98800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("frintz", 0x0ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frintz", 0x0ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtps", 0x0ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtps", 0x0ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtzs", 0x0ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtzs", 0x0ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("urecpe", 0x0ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
| SIMD_INSN ("frecpe", 0x0ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frecpe", 0x0ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ), |
| SIMD_INSN ("uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), |
| SIMD_INSN ("usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), |
| SIMD_INSN ("sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), |
| SIMD_INSN ("sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), |
| SIMD_INSN ("sqxtun2",0x6e212800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ), |
| SIMD_INSN ("shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ), |
| SIMD_INSN ("uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), |
| SIMD_INSN ("uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), |
| SIMD_INSN ("fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS, 0), |
| SIMD_INSN ("fcvtxn2",0x6e616800, 0xfffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2NARRS2, 0), |
| SIMD_INSN ("frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frinta", 0x2e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frintx", 0x2e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("not", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS), |
| SIMD_INSN ("mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS), |
| SIMD_INSN ("rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), |
| SIMD_INSN ("fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frinti", 0x2ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("ursqrte",0x2ea1c800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), |
| SIMD_INSN ("frsqrte",0x2ea1d800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("frsqrte",0x2ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| SIMD_INSN ("fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), |
| SF16_INSN ("fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), |
| /* AdvSIMD ZIP/UZP/TRN. */ |
| SIMD_INSN ("uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| /* AdvSIMD three same. */ |
| SIMD_INSN ("shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("smax", 0xe206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("add", 0xe208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("mla", 0xe209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
| SIMD_INSN ("addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmla", 0xe400c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fadd", 0xe401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmax", 0xe403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("frecps", 0xe403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fminnm", 0xec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmls", 0xec00c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fsub", 0xec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmin", 0xec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ), |
| SIMD_INSN ("mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV), |
| SIMD_INSN ("orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), |
| SIMD_INSN ("mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), |
| SIMD_INSN ("sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
| SIMD_INSN ("fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("faddp", 0x2e401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("facge", 0x2e402c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), |
| SF16_INSN ("fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), |
| SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), |
| /* AdvSIMD three same extension. */ |
| RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
| RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), |
| {"fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL}, |
| {"fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, SIMD_V8_3, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ, 0, NULL}, |
| /* AdvSIMD shift by immediate. */ |
| SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("shl", 0xf005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), |
| SIMD_INSN ("sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), |
| SIMD_INSN ("shrn", 0xf008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), |
| SIMD_INSN ("sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
| SIMD_INSN ("sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
| SIMD_INSN ("sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
| SIMD_INSN ("scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| SF16_INSN ("scvtf", 0xf10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| SIMD_INSN ("fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| SF16_INSN ("fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| SIMD_INSN ("ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), |
| SIMD_INSN ("sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), |
| SIMD_INSN ("sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), |
| SIMD_INSN ("uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), |
| SIMD_INSN ("sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), |
| SIMD_INSN ("uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), |
| SIMD_INSN ("ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), |
| SIMD_INSN ("uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV), |
| SIMD_INSN ("ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), |
| SIMD_INSN ("uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV), |
| SIMD_INSN ("ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| SF16_INSN ("ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| SIMD_INSN ("fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), |
| SF16_INSN ("fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), |
| /* AdvSIMD TBL/TBX. */ |
| SIMD_INSN ("tbl", |