Update headers from rnndb
diff --git a/src/cmdstream.xml.h b/src/cmdstream.xml.h
index 09591d2..7cef950 100644
--- a/src/cmdstream.xml.h
+++ b/src/cmdstream.xml.h
@@ -8,11 +8,11 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- cmdstream.xml ( 14313 bytes, from 2016-11-17 18:46:23)
+- cmdstream.xml ( 16929 bytes, from 2017-10-13 12:22:46)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
-Copyright (C) 2012-2016 by the following authors:
+Copyright (C) 2012-2017 by the following authors:
- Wladimir J. van der Laan <laanwj@gmail.com>
- Christian Gmeiner <christian.gmeiner@gmail.com>
- Lucas Stach <l.stach@pengutronix.de>
@@ -52,6 +52,9 @@
#define FE_OPCODE_RETURN 0x0000000b
#define FE_OPCODE_DRAW_INSTANCED 0x0000000c
#define FE_OPCODE_CHIP_SELECT 0x0000000d
+#define FE_OPCODE_WAIT_FENCE 0x0000000f
+#define FE_OPCODE_DRAW_INDIRECT 0x00000010
+#define FE_OPCODE_SNAP_PAGES 0x00000013
#define PRIMITIVE_TYPE_POINTS 0x00000001
#define PRIMITIVE_TYPE_LINES 0x00000002
#define PRIMITIVE_TYPE_LINE_STRIP 0x00000003
@@ -192,6 +195,9 @@
#define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00
#define VIV_FE_STALL_TOKEN_TO__SHIFT 8
#define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
+#define VIV_FE_STALL_TOKEN_UNK28__MASK 0x30000000
+#define VIV_FE_STALL_TOKEN_UNK28__SHIFT 28
+#define VIV_FE_STALL_TOKEN_UNK28(x) (((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK)
#define VIV_FE_CALL 0x00000000
@@ -266,5 +272,43 @@
#define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT 0
#define VIV_FE_DRAW_INSTANCED_START_INDEX(x) (((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK)
+#define VIV_FE_WAIT_FENCE 0x00000000
+
+#define VIV_FE_WAIT_FENCE_HEADER 0x00000000
+#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK 0xf8000000
+#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT 27
+#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE 0x78000000
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK 0x00030000
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT 16
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK)
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK 0x0000ffff
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT 0
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK)
+
+#define VIV_FE_WAIT_FENCE_ADDRESS 0x00000004
+
+#define VIV_FE_DRAW_INDIRECT 0x00000000
+
+#define VIV_FE_DRAW_INDIRECT_HEADER 0x00000000
+#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK 0xf8000000
+#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT 27
+#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT 0x80000000
+#define VIV_FE_DRAW_INDIRECT_HEADER_UNK8 0x00000100
+#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK 0x0000000f
+#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT 0
+#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK)
+
+#define VIV_FE_DRAW_INDIRECT_ADDRESS 0x00000004
+
+#define VIV_FE_SNAP_PAGES 0x00000000
+
+#define VIV_FE_SNAP_PAGES_HEADER 0x00000000
+#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK 0xf8000000
+#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT 27
+#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES 0x98000000
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK 0x0000001f
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT 0
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x) (((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK)
+
#endif /* CMDSTREAM_XML */
diff --git a/src/common.xml.h b/src/common.xml.h
index b4732cc..b85bd8a 100644
--- a/src/common.xml.h
+++ b/src/common.xml.h
@@ -8,13 +8,10 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 19930 bytes, from 2017-01-07 14:27:54)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
-- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54)
-- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
-- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 67197 bytes, from 2017-07-23 10:53:21)
-- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
+- texdesc_3d.xml ( 3146 bytes, from 2017-10-13 12:18:33)
+- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
Copyright (C) 2012-2017 by the following authors:
- Wladimir J. van der Laan <laanwj@gmail.com>
@@ -49,12 +46,7 @@
#define SYNC_RECIPIENT_RA 0x00000005
#define SYNC_RECIPIENT_PE 0x00000007
#define SYNC_RECIPIENT_DE 0x0000000b
-#define SYNC_RECIPIENT_VG 0x0000000f
-#define SYNC_RECIPIENT_TESSELATOR 0x00000010
-#define SYNC_RECIPIENT_VG2 0x00000011
-#define SYNC_RECIPIENT_TESSELATOR2 0x00000012
-#define SYNC_RECIPIENT_VG3 0x00000013
-#define SYNC_RECIPIENT_TESSELATOR3 0x00000014
+#define SYNC_RECIPIENT_BLT 0x00000010
#define ENDIAN_MODE_NO_SWAP 0x00000000
#define ENDIAN_MODE_SWAP_16 0x00000001
#define ENDIAN_MODE_SWAP_32 0x00000002
@@ -77,6 +69,7 @@
#define chipModel_GC800 0x00000800
#define chipModel_GC860 0x00000860
#define chipModel_GC880 0x00000880
+#define chipModel_GC900 0x00000900
#define chipModel_GC1000 0x00001000
#define chipModel_GC1500 0x00001500
#define chipModel_GC2000 0x00002000
@@ -88,6 +81,12 @@
#define chipModel_GC5000 0x00005000
#define chipModel_GC5200 0x00005200
#define chipModel_GC6400 0x00006400
+#define chipModel_GC7000 0x00007000
+#define chipModel_GC7400 0x00007400
+#define chipModel_GC8000 0x00008000
+#define chipModel_GC8100 0x00008100
+#define chipModel_GC8200 0x00008200
+#define chipModel_GC8400 0x00008400
#define RGBA_BITS_R 0x00000001
#define RGBA_BITS_G 0x00000002
#define RGBA_BITS_B 0x00000004
@@ -203,7 +202,7 @@
#define chipMinorFeatures2_RGB888 0x00001000
#define chipMinorFeatures2_TX__YUV_ASSEMBLER 0x00002000
#define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING 0x00004000
-#define chipMinorFeatures2_EXTRA_TEXTURE_STATE 0x00008000
+#define chipMinorFeatures2_TX_FILTER 0x00008000
#define chipMinorFeatures2_FULL_DIRECTFB 0x00010000
#define chipMinorFeatures2_2D_TILING 0x00020000
#define chipMinorFeatures2_THREAD_WALKER_IN_PS 0x00040000
@@ -242,36 +241,36 @@
#define chipMinorFeatures3_TX_ENHANCEMENTS1 0x00080000
#define chipMinorFeatures3_SH_ENHANCEMENTS1 0x00100000
#define chipMinorFeatures3_SH_ENHANCEMENTS2 0x00200000
-#define chipMinorFeatures3_UNK22 0x00400000
+#define chipMinorFeatures3_PE_ENHANCEMENTS1 0x00400000
#define chipMinorFeatures3_2D_FC_SOURCE 0x00800000
-#define chipMinorFeatures3_UNK24 0x01000000
-#define chipMinorFeatures3_UNK25 0x02000000
+#define chipMinorFeatures3_BUG_FIXES_14 0x01000000
+#define chipMinorFeatures3_POWER_OPTIMIZATIONS_0 0x02000000
#define chipMinorFeatures3_NEW_HZ 0x04000000
#define chipMinorFeatures3_PE_DITHER_FIX 0x08000000
-#define chipMinorFeatures3_UNK28 0x10000000
+#define chipMinorFeatures3_DE_ENHANCEMENTS3 0x10000000
#define chipMinorFeatures3_SH_ENHANCEMENTS3 0x20000000
-#define chipMinorFeatures3_UNK30 0x40000000
-#define chipMinorFeatures3_UNK31 0x80000000
-#define chipMinorFeatures4_UNK0 0x00000001
+#define chipMinorFeatures3_SH_ENHANCEMENTS4 0x40000000
+#define chipMinorFeatures3_TX_ENHANCEMENTS2 0x80000000
+#define chipMinorFeatures4_FE_ENHANCEMENTS1 0x00000001
#define chipMinorFeatures4_PE_ENHANCEMENTS2 0x00000002
#define chipMinorFeatures4_FRUSTUM_CLIP_FIX 0x00000004
-#define chipMinorFeatures4_UNK3 0x00000008
-#define chipMinorFeatures4_UNK4 0x00000010
+#define chipMinorFeatures4_DE_NO_GAMMA 0x00000008
+#define chipMinorFeatures4_PA_ENHANCEMENTS_2 0x00000010
#define chipMinorFeatures4_2D_GAMMA 0x00000020
#define chipMinorFeatures4_SINGLE_BUFFER 0x00000040
-#define chipMinorFeatures4_UNK7 0x00000080
-#define chipMinorFeatures4_UNK8 0x00000100
-#define chipMinorFeatures4_UNK9 0x00000200
-#define chipMinorFeatures4_UNK10 0x00000400
+#define chipMinorFeatures4_HI_ENHANCEMENTS_1 0x00000080
+#define chipMinorFeatures4_TX_ENHANCEMENTS_3 0x00000100
+#define chipMinorFeatures4_SH_ENHANCEMENTS_5 0x00000200
+#define chipMinorFeatures4_FE_ENHANCEMENTS_2 0x00000400
#define chipMinorFeatures4_TX_LERP_PRECISION_FIX 0x00000800
#define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION 0x00001000
#define chipMinorFeatures4_TEXTURE_ASTC 0x00002000
-#define chipMinorFeatures4_UNK14 0x00004000
-#define chipMinorFeatures4_UNK15 0x00008000
+#define chipMinorFeatures4_PE_ENHANCEMENTS_4 0x00004000
+#define chipMinorFeatures4_MC_ENHANCEMENTS_1 0x00008000
#define chipMinorFeatures4_HALTI2 0x00010000
#define chipMinorFeatures4_2D_MIRROR_EXTENSION 0x00020000
#define chipMinorFeatures4_SMALL_MSAA 0x00040000
-#define chipMinorFeatures4_UNK19 0x00080000
+#define chipMinorFeatures4_BUG_FIXES_17 0x00080000
#define chipMinorFeatures4_NEW_RA 0x00100000
#define chipMinorFeatures4_2D_OPF_YUV_OUTPUT 0x00200000
#define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2 0x00400000
@@ -280,41 +279,46 @@
#define chipMinorFeatures4_BUG_FIXES18 0x02000000
#define chipMinorFeatures4_2D_COMPRESSION 0x04000000
#define chipMinorFeatures4_PROBE 0x08000000
-#define chipMinorFeatures4_UNK28 0x10000000
+#define chipMinorFeatures4_MEDIUM_PRECISION 0x10000000
#define chipMinorFeatures4_2D_SUPER_TILE_VERSION 0x20000000
-#define chipMinorFeatures4_UNK30 0x40000000
-#define chipMinorFeatures4_UNK31 0x80000000
-#define chipMinorFeatures5_UNK0 0x00000001
-#define chipMinorFeatures5_UNK1 0x00000002
-#define chipMinorFeatures5_UNK2 0x00000004
-#define chipMinorFeatures5_UNK3 0x00000008
+#define chipMinorFeatures4_BUG_FIXES19 0x40000000
+#define chipMinorFeatures4_SH_ENHANCEMENTS6 0x80000000
+#define chipMinorFeatures5_SH_ENHANCEMENTS7 0x00000001
+#define chipMinorFeatures5_BUG_FIXES20 0x00000002
+#define chipMinorFeatures5_DE_ADDRESS_40 0x00000004
+#define chipMinorFeatures5_MINI_MMU_FIX 0x00000008
#define chipMinorFeatures5_EEZ 0x00000010
-#define chipMinorFeatures5_UNK5 0x00000020
-#define chipMinorFeatures5_UNK6 0x00000040
-#define chipMinorFeatures5_UNK7 0x00000080
-#define chipMinorFeatures5_UNK8 0x00000100
+#define chipMinorFeatures5_BUG_FIXES21 0x00000020
+#define chipMinorFeatures5_EXTRA_VG_CAPS 0x00000040
+#define chipMinorFeatures5_MULTI_SRC_V15 0x00000080
+#define chipMinorFeatures5_BUG_FIXES22 0x00000100
#define chipMinorFeatures5_HALTI3 0x00000200
-#define chipMinorFeatures5_UNK10 0x00000400
+#define chipMinorFeatures5_TESSELATION_SHADERS 0x00000400
#define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP 0x00000800
-#define chipMinorFeatures5_UNK12 0x00001000
+#define chipMinorFeatures5_MULTI_SRC_V2_STR_QUAD 0x00001000
#define chipMinorFeatures5_SEPARATE_SRC_DST 0x00002000
#define chipMinorFeatures5_HALTI4 0x00004000
-#define chipMinorFeatures5_UNK15 0x00008000
+#define chipMinorFeatures5_RA_WRITE_DEPTH 0x00008000
#define chipMinorFeatures5_ANDROID_ONLY 0x00010000
#define chipMinorFeatures5_HAS_PRODUCTID 0x00020000
-#define chipMinorFeatures5_UNK18 0x00040000
-#define chipMinorFeatures5_UNK19 0x00080000
+#define chipMinorFeatures5_TX_SUPPORT_DEC 0x00040000
+#define chipMinorFeatures5_S8_MSAA_COMPRESSION 0x00080000
#define chipMinorFeatures5_PE_DITHER_FIX2 0x00100000
-#define chipMinorFeatures5_UNK21 0x00200000
-#define chipMinorFeatures5_UNK22 0x00400000
-#define chipMinorFeatures5_UNK23 0x00800000
-#define chipMinorFeatures5_UNK24 0x01000000
-#define chipMinorFeatures5_UNK25 0x02000000
-#define chipMinorFeatures5_UNK26 0x04000000
+#define chipMinorFeatures5_L2_CACHE_REMOVE 0x00200000
+#define chipMinorFeatures5_FE_ALLOW_RND_VTX_CNT 0x00400000
+#define chipMinorFeatures5_CUBE_MAP_FL28 0x00800000
+#define chipMinorFeatures5_TX_6BIT_FRAC 0x01000000
+#define chipMinorFeatures5_FE_ALLOW_STALL_PREFETCH_ENG 0x02000000
+#define chipMinorFeatures5_THIRD_PARTY_COMPRESSION 0x04000000
#define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT 0x08000000
#define chipMinorFeatures5_V2_MSAA_COMP_FIX 0x10000000
-#define chipMinorFeatures5_UNK29 0x20000000
-#define chipMinorFeatures5_UNK30 0x40000000
-#define chipMinorFeatures5_UNK31 0x80000000
+#define chipMinorFeatures5_HALTI5 0x20000000
+#define chipMinorFeatures5_EVIS 0x40000000
+#define chipMinorFeatures5_BLT_ENGINE 0x80000000
+#define chipMinorFeatures6_BUG_FIXES_23 0x00000001
+#define chipMinorFeatures6_BUG_FIXES_24 0x00000002
+#define chipMinorFeatures6_DEC 0x00000004
+#define chipMinorFeatures6_VS_TILE_NV12 0x00000008
+#define chipMinorFeatures6_VS_TILE_NV12_10BIT 0x00000010
#endif /* COMMON_XML */
diff --git a/src/common_3d.xml.h b/src/common_3d.xml.h
new file mode 100644
index 0000000..1832655
--- /dev/null
+++ b/src/common_3d.xml.h
@@ -0,0 +1,140 @@
+#ifndef COMMON_3D_XML
+#define COMMON_3D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- texdesc_3d.xml ( 3146 bytes, from 2017-10-13 12:18:33)
+- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+
+Copyright (C) 2012-2017 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define TEXTURE_FORMAT_NONE 0x00000000
+#define TEXTURE_FORMAT_A8 0x00000001
+#define TEXTURE_FORMAT_L8 0x00000002
+#define TEXTURE_FORMAT_I8 0x00000003
+#define TEXTURE_FORMAT_A8L8 0x00000004
+#define TEXTURE_FORMAT_A4R4G4B4 0x00000005
+#define TEXTURE_FORMAT_X4R4G4B4 0x00000006
+#define TEXTURE_FORMAT_A8R8G8B8 0x00000007
+#define TEXTURE_FORMAT_X8R8G8B8 0x00000008
+#define TEXTURE_FORMAT_A8B8G8R8 0x00000009
+#define TEXTURE_FORMAT_X8B8G8R8 0x0000000a
+#define TEXTURE_FORMAT_R5G6B5 0x0000000b
+#define TEXTURE_FORMAT_A1R5G5B5 0x0000000c
+#define TEXTURE_FORMAT_X1R5G5B5 0x0000000d
+#define TEXTURE_FORMAT_YUY2 0x0000000e
+#define TEXTURE_FORMAT_UYVY 0x0000000f
+#define TEXTURE_FORMAT_D16 0x00000010
+#define TEXTURE_FORMAT_D24S8 0x00000011
+#define TEXTURE_FORMAT_DXT1 0x00000013
+#define TEXTURE_FORMAT_DXT2_DXT3 0x00000014
+#define TEXTURE_FORMAT_DXT4_DXT5 0x00000015
+#define TEXTURE_FORMAT_E5B9G9R9 0x0000001d
+#define TEXTURE_FORMAT_ETC1 0x0000001e
+#define TEXTURE_FORMAT_EXT_NONE 0x00000000
+#define TEXTURE_FORMAT_EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 0x00000001
+#define TEXTURE_FORMAT_EXT_RGBA8_ETC2_EAC 0x00000002
+#define TEXTURE_FORMAT_EXT_R11_EAC 0x00000003
+#define TEXTURE_FORMAT_EXT_RG11_EAC 0x00000004
+#define TEXTURE_FORMAT_EXT_SIGNED_RG11_EAC 0x00000005
+#define TEXTURE_FORMAT_EXT_G8R8 0x00000006
+#define TEXTURE_FORMAT_EXT_R16F 0x00000007
+#define TEXTURE_FORMAT_EXT_G16R16F 0x00000008
+#define TEXTURE_FORMAT_EXT_A16B16G16R16F 0x00000009
+#define TEXTURE_FORMAT_EXT_R32F 0x0000000a
+#define TEXTURE_FORMAT_EXT_G32R32F 0x0000000b
+#define TEXTURE_FORMAT_EXT_A2B10G10R10 0x0000000c
+#define TEXTURE_FORMAT_EXT_SIGNED_R11_EAC 0x0000000d
+#define TEXTURE_FORMAT_EXT_R8_SNORM 0x0000000e
+#define TEXTURE_FORMAT_EXT_G8R8_SNORM 0x0000000f
+#define TEXTURE_FORMAT_EXT_X8B8G8R8_SNORM 0x00000010
+#define TEXTURE_FORMAT_EXT_A8B8G8R8_SNORM 0x00000011
+#define TEXTURE_FORMAT_EXT_ASTC 0x00000014
+#define TEXTURE_FORMAT_EXT_R8I 0x00000015
+#define TEXTURE_FORMAT_EXT_G8R8I 0x00000016
+#define TEXTURE_FORMAT_EXT_A8B8G8R8I 0x00000017
+#define TEXTURE_FORMAT_EXT_R16I 0x00000018
+#define TEXTURE_FORMAT_EXT_G16R16I 0x00000019
+#define TEXTURE_FORMAT_EXT_A16B16G16R16I 0x0000001a
+#define TEXTURE_FORMAT_EXT_B10G11R11F 0x0000001b
+#define TEXTURE_FORMAT_EXT_A2B10G10R10UI 0x0000001c
+#define TEXTURE_FORMAT_EXT_R8 0x00000021
+#define TEXTURE_FORMAT_EXT_D24S8 0x00000022
+#define TEXTURE_FORMAT_EXT_R32I 0x00000023
+#define TEXTURE_FORMAT_EXT_G32R32I 0x00000024
+#define TEXTURE_FORMAT_EXT_AYUV 0x00000025
+#define TEXTURE_FILTER_NONE 0x00000000
+#define TEXTURE_FILTER_NEAREST 0x00000001
+#define TEXTURE_FILTER_LINEAR 0x00000002
+#define TEXTURE_FILTER_ANISOTROPIC 0x00000003
+#define TEXTURE_TYPE_NONE 0x00000000
+#define TEXTURE_TYPE_1D 0x00000001
+#define TEXTURE_TYPE_2D 0x00000002
+#define TEXTURE_TYPE_3D 0x00000003
+#define TEXTURE_TYPE_CUBE_MAP 0x00000005
+#define TEXTURE_WRAPMODE_REPEAT 0x00000000
+#define TEXTURE_WRAPMODE_MIRRORED_REPEAT 0x00000001
+#define TEXTURE_WRAPMODE_CLAMP_TO_EDGE 0x00000002
+#define TEXTURE_WRAPMODE_CLAMP_TO_BORDER 0x00000003
+#define TEXTURE_FACE_POS_X 0x00000000
+#define TEXTURE_FACE_NEG_X 0x00000001
+#define TEXTURE_FACE_POS_Y 0x00000002
+#define TEXTURE_FACE_NEG_Y 0x00000003
+#define TEXTURE_FACE_POS_Z 0x00000004
+#define TEXTURE_FACE_NEG_Z 0x00000005
+#define TEXTURE_SWIZZLE_RED 0x00000000
+#define TEXTURE_SWIZZLE_GREEN 0x00000001
+#define TEXTURE_SWIZZLE_BLUE 0x00000002
+#define TEXTURE_SWIZZLE_ALPHA 0x00000003
+#define TEXTURE_SWIZZLE_ZERO 0x00000004
+#define TEXTURE_SWIZZLE_ONE 0x00000005
+#define TEXTURE_HALIGN_FOUR 0x00000000
+#define TEXTURE_HALIGN_SIXTEEN 0x00000001
+#define TEXTURE_HALIGN_SUPER_TILED 0x00000002
+#define TEXTURE_HALIGN_SPLIT_TILED 0x00000003
+#define TEXTURE_HALIGN_SPLIT_SUPER_TILED 0x00000004
+#define COLOR_COMPRESSION_FORMAT_A4R4G4B4 0x00000000
+#define COLOR_COMPRESSION_FORMAT_A1R5G5B5 0x00000001
+#define COLOR_COMPRESSION_FORMAT_R5G6B5 0x00000002
+#define COLOR_COMPRESSION_FORMAT_A8R8G8B8 0x00000003
+#define COLOR_COMPRESSION_FORMAT_X8R8G8B8 0x00000004
+#define TE_SAMPLER_CONFIG2_UNK16 0x00010000
+#define TE_SAMPLER_CONFIG2_UNK17 0x00020000
+#define TE_SAMPLER_CONFIG2_UNK18 0x00040000
+#define TE_SAMPLER_CONFIG2_UNK19 0x00080000
+#define TE_SAMPLER_CONFIG2_UNK23 0x00800000
+#define TE_SAMPLER_CONFIG3_MSAA 0x00000008
+
+#endif /* COMMON_3D_XML */
diff --git a/src/etnaviv_cl_bench.c b/src/etnaviv_cl_bench.c
index ac962a3..2503cc6 100644
--- a/src/etnaviv_cl_bench.c
+++ b/src/etnaviv_cl_bench.c
@@ -181,7 +181,7 @@
static void gen_cmd_stream_gc3000(struct etna_cmd_stream *stream, struct gpu_code *gpu_code,
struct etna_bo *bmp, uint32_t out_gpu_addr)
{
- etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4);
+ etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST | VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL);
etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, 0x1000);
@@ -243,7 +243,7 @@
static void gen_cmd_stream_gc2000(struct etna_cmd_stream *stream, struct gpu_code *gpu_code,
struct etna_bo *bmp, uint32_t out_gpu_addr)
{
- etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4);
+ etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST | VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL);
etna_set_state(stream, VIVS_VS_INPUT_COUNT, VIVS_VS_INPUT_COUNT_COUNT(1) | VIVS_VS_INPUT_COUNT_UNK8(31));
diff --git a/src/etnaviv_cl_test_gc2000.c b/src/etnaviv_cl_test_gc2000.c
index 1ae836c..3752999 100644
--- a/src/etnaviv_cl_test_gc2000.c
+++ b/src/etnaviv_cl_test_gc2000.c
@@ -24,7 +24,7 @@
static void gen_cmd_stream(struct etna_cmd_stream *stream, struct etna_bo *bmp)
{
- etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4);
+ etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST | VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL);
etna_set_state(stream, VIVS_VS_INPUT_COUNT, VIVS_VS_INPUT_COUNT_COUNT(1) | VIVS_VS_INPUT_COUNT_UNK8(31));
etna_set_state(stream, VIVS_VS_INPUT(0), VIVS_VS_INPUT_I0(0) | VIVS_VS_INPUT_I1(1) | VIVS_VS_INPUT_I2(2) | VIVS_VS_INPUT_I3(3));
diff --git a/src/etnaviv_cl_test_gc3000.c b/src/etnaviv_cl_test_gc3000.c
index d8336b0..3180c67 100644
--- a/src/etnaviv_cl_test_gc3000.c
+++ b/src/etnaviv_cl_test_gc3000.c
@@ -45,7 +45,7 @@
static void gen_cmd_stream(struct etna_cmd_stream *stream, struct etna_bo *code, struct etna_bo *bmp)
{
- etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4);
+ etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST | VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL);
etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, 0x1000);
diff --git a/src/etnaviv_verifyops.c b/src/etnaviv_verifyops.c
index 2aa0445..588d5d8 100644
--- a/src/etnaviv_verifyops.c
+++ b/src/etnaviv_verifyops.c
@@ -69,7 +69,7 @@
unsigned uniform_base = 0;
unsigned inst_range_max = gpu_code->size / 4 - 2;
- etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4);
+ etna_set_state(stream, VIVS_PA_SYSTEM_MODE, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST | VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL);
if (hwt == HWT_GC2000) {
diff --git a/src/isa.xml.h b/src/isa.xml.h
index 98dbbb6..80964db 100644
--- a/src/isa.xml.h
+++ b/src/isa.xml.h
@@ -8,7 +8,7 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- isa.xml ( 34708 bytes, from 2017-07-11 11:56:17)
+- isa.xml ( 35432 bytes, from 2017-10-01 09:57:00)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
Copyright (C) 2012-2017 by the following authors:
diff --git a/src/state.xml.h b/src/state.xml.h
index 9705bad..94adff7 100644
--- a/src/state.xml.h
+++ b/src/state.xml.h
@@ -8,12 +8,14 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 19930 bytes, from 2017-01-07 14:27:54)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
-- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54)
+- state.xml ( 25532 bytes, from 2017-10-13 12:19:04)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 67197 bytes, from 2017-07-23 10:53:21)
+- state_3d.xml ( 74317 bytes, from 2017-10-13 12:43:31)
+- state_blt.xml ( 11153 bytes, from 2017-10-13 12:39:38)
- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
Copyright (C) 2012-2017 by the following authors:
@@ -47,6 +49,19 @@
#define VARYING_COMPONENT_USE_USED 0x00000001
#define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
#define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
+#define FE_DATA_TYPE_BYTE 0x00000000
+#define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
+#define FE_DATA_TYPE_SHORT 0x00000002
+#define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
+#define FE_DATA_TYPE_INT 0x00000004
+#define FE_DATA_TYPE_UNSIGNED_INT 0x00000005
+#define FE_DATA_TYPE_FLOAT 0x00000008
+#define FE_DATA_TYPE_HALF_FLOAT 0x00000009
+#define FE_DATA_TYPE_FIXED 0x0000000b
+#define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c
+#define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d
+#define FE_DATA_TYPE_BYTE_I 0x0000000e
+#define FE_DATA_TYPE_SHORT_I 0x0000000f
#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff
#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0
#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
@@ -60,17 +75,7 @@
#define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_BYTE 0x00000000
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_BYTE 0x00000001
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_SHORT 0x00000002
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_SHORT 0x00000003
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT 0x00000004
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT 0x00000005
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT 0x00000008
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_HALF_FLOAT 0x00000009
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FIXED 0x0000000b
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT_10_10_10_2 0x0000000c
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
@@ -192,17 +197,40 @@
#define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0))
-#define VIVS_FE_UNK00700(i0) (0x00000700 + 0x4*(i0))
-#define VIVS_FE_UNK00700__ESIZE 0x00000004
-#define VIVS_FE_UNK00700__LEN 0x00000010
+#define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
+#define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004
+#define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010
-#define VIVS_FE_UNK00740(i0) (0x00000740 + 0x4*(i0))
-#define VIVS_FE_UNK00740__ESIZE 0x00000004
-#define VIVS_FE_UNK00740__LEN 0x00000010
+#define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0))
-#define VIVS_FE_UNK00780(i0) (0x00000780 + 0x4*(i0))
-#define VIVS_FE_UNK00780__ESIZE 0x00000004
-#define VIVS_FE_UNK00780__LEN 0x00000010
+#define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0))
+
+#define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0))
+
+#define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))
+
+#define VIVS_FE_HALTI5_UNK007C4 0x000007c4
+
+#define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))
+#define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004
+#define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002
+
+#define VIVS_FE_HALTI5_UNK007D8 0x000007d8
+
+#define VIVS_FE_DESC_START 0x000007dc
+
+#define VIVS_FE_DESC_END 0x000007e0
+
+#define VIVS_FE_DESC_AVAIL 0x000007e4
+#define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f
+#define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0
+#define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
+
+#define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8
+
+#define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4
+
+#define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
#define VIVS_GL 0x00000000
@@ -228,6 +256,9 @@
#define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00
#define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8
#define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
#define VIVS_GL_FLUSH_CACHE 0x0000380c
#define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001
@@ -237,6 +268,10 @@
#define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010
#define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020
#define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040
+#define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400
+#define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
+#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
+#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
#define VIVS_GL_FLUSH_MMU 0x00003810
#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
@@ -298,6 +333,8 @@
#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT 28
#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x) (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK)
+#define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824
+
#define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0))
#define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004
#define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002
@@ -350,6 +387,10 @@
#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30
#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
+#define VIVS_GL_UNK0382C 0x0000382c
+
+#define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830
+
#define VIVS_GL_UNK03834 0x00003834
#define VIVS_GL_UNK03838 0x00003838
@@ -363,8 +404,44 @@
#define VIVS_GL_UNK03854 0x00003854
+#define VIVS_GL_BUG_FIXES 0x00003860
+
+#define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868
+
+#define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c
+
+#define VIVS_GL_HALTI5_UNK03884 0x00003884
+
+#define VIVS_GL_HALTI5_UNK03888 0x00003888
+
+#define VIVS_GL_GS_UNK0388C 0x0000388c
+
+#define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898
+
+#define VIVS_GL_SHADER_INDEX 0x0000389c
+
+#define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0))
+#define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004
+#define VIVS_GL_GS_UNK038A0__LEN 0x00000008
+
+#define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0))
+#define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004
+#define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010
+
+#define VIVS_GL_SECURITY_UNK3900 0x00003900
+
+#define VIVS_GL_SECURITY_UNK3904 0x00003904
+
#define VIVS_GL_UNK03A00 0x00003a00
+#define VIVS_GL_UNK03A04 0x00003a04
+
+#define VIVS_GL_UNK03A08 0x00003a08
+
+#define VIVS_GL_UNK03A0C 0x00003a0c
+
+#define VIVS_GL_UNK03A10 0x00003a10
+
#define VIVS_GL_STALL_TOKEN 0x00003c00
#define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f
#define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0
@@ -387,6 +464,47 @@
#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0))
+#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))
+
+#define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004
+#define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020
+
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)
+
+#define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0))
+
+#define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0))
+
+#define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0))
+
+#define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0))
+
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800
+
#define VIVS_DUMMY 0x00000000
#define VIVS_DUMMY_DUMMY 0x0003fffc
diff --git a/src/state_2d.xml.h b/src/state_2d.xml.h
index f035a68..7e4e12e 100644
--- a/src/state_2d.xml.h
+++ b/src/state_2d.xml.h
@@ -8,12 +8,14 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 19930 bytes, from 2017-01-07 14:27:54)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
-- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54)
+- state.xml ( 25532 bytes, from 2017-10-13 12:19:04)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 67197 bytes, from 2017-07-23 10:53:21)
+- state_3d.xml ( 74317 bytes, from 2017-10-13 12:43:31)
+- state_blt.xml ( 11153 bytes, from 2017-10-13 12:39:38)
- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
Copyright (C) 2012-2016 by the following authors:
diff --git a/src/state_3d.xml.h b/src/state_3d.xml.h
index d8b7a94..a9d5bfd 100644
--- a/src/state_3d.xml.h
+++ b/src/state_3d.xml.h
@@ -8,12 +8,14 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 19930 bytes, from 2017-01-07 14:27:54)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
-- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54)
+- state.xml ( 25532 bytes, from 2017-10-13 12:19:04)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 67197 bytes, from 2017-07-23 10:53:21)
+- state_3d.xml ( 74317 bytes, from 2017-10-13 12:43:31)
+- state_blt.xml ( 11153 bytes, from 2017-10-13 12:39:38)
- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
Copyright (C) 2012-2017 by the following authors:
@@ -87,6 +89,7 @@
#define RS_FORMAT_X8R8G8B8 0x00000005
#define RS_FORMAT_A8R8G8B8 0x00000006
#define RS_FORMAT_YUY2 0x00000007
+#define RS_FORMAT_A8 0x00000010
#define RS_FORMAT_R16F 0x00000011
#define RS_FORMAT_G16R16F 0x00000012
#define RS_FORMAT_A16B16G16R16F 0x00000013
@@ -102,83 +105,7 @@
#define RS_FORMAT_B10G11R11F 0x0000001d
#define RS_FORMAT_A2B10G10R10UI 0x0000001e
#define RS_FORMAT_G8R8 0x0000001f
-#define TEXTURE_FORMAT_NONE 0x00000000
-#define TEXTURE_FORMAT_A8 0x00000001
-#define TEXTURE_FORMAT_L8 0x00000002
-#define TEXTURE_FORMAT_I8 0x00000003
-#define TEXTURE_FORMAT_A8L8 0x00000004
-#define TEXTURE_FORMAT_A4R4G4B4 0x00000005
-#define TEXTURE_FORMAT_X4R4G4B4 0x00000006
-#define TEXTURE_FORMAT_A8R8G8B8 0x00000007
-#define TEXTURE_FORMAT_X8R8G8B8 0x00000008
-#define TEXTURE_FORMAT_A8B8G8R8 0x00000009
-#define TEXTURE_FORMAT_X8B8G8R8 0x0000000a
-#define TEXTURE_FORMAT_R5G6B5 0x0000000b
-#define TEXTURE_FORMAT_A1R5G5B5 0x0000000c
-#define TEXTURE_FORMAT_X1R5G5B5 0x0000000d
-#define TEXTURE_FORMAT_YUY2 0x0000000e
-#define TEXTURE_FORMAT_UYVY 0x0000000f
-#define TEXTURE_FORMAT_D16 0x00000010
-#define TEXTURE_FORMAT_D24S8 0x00000011
-#define TEXTURE_FORMAT_DXT1 0x00000013
-#define TEXTURE_FORMAT_DXT2_DXT3 0x00000014
-#define TEXTURE_FORMAT_DXT4_DXT5 0x00000015
-#define TEXTURE_FORMAT_E5B9G9R9 0x0000001d
-#define TEXTURE_FORMAT_ETC1 0x0000001e
-#define TEXTURE_FORMAT_EXT_NONE 0x00000000
-#define TEXTURE_FORMAT_EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 0x00000001
-#define TEXTURE_FORMAT_EXT_RGBA8_ETC2_EAC 0x00000002
-#define TEXTURE_FORMAT_EXT_R11_EAC 0x00000003
-#define TEXTURE_FORMAT_EXT_RG11_EAC 0x00000004
-#define TEXTURE_FORMAT_EXT_SIGNED_RG11_EAC 0x00000005
-#define TEXTURE_FORMAT_EXT_G8R8 0x00000006
-#define TEXTURE_FORMAT_EXT_R16F 0x00000007
-#define TEXTURE_FORMAT_EXT_G16R16F 0x00000008
-#define TEXTURE_FORMAT_EXT_A16B16G16R16F 0x00000009
-#define TEXTURE_FORMAT_EXT_R32F 0x0000000a
-#define TEXTURE_FORMAT_EXT_G32R32F 0x0000000b
-#define TEXTURE_FORMAT_EXT_A2B10G10R10 0x0000000c
-#define TEXTURE_FORMAT_EXT_SIGNED_R11_EAC 0x0000000d
-#define TEXTURE_FORMAT_EXT_R8_SNORM 0x0000000e
-#define TEXTURE_FORMAT_EXT_G8R8_SNORM 0x0000000f
-#define TEXTURE_FORMAT_EXT_X8B8G8R8_SNORM 0x00000010
-#define TEXTURE_FORMAT_EXT_A8B8G8R8_SNORM 0x00000011
-#define TEXTURE_FORMAT_EXT_ASTC 0x00000014
-#define TEXTURE_FORMAT_EXT_R8I 0x00000015
-#define TEXTURE_FORMAT_EXT_G8R8I 0x00000016
-#define TEXTURE_FORMAT_EXT_A8B8G8R8I 0x00000017
-#define TEXTURE_FORMAT_EXT_R16I 0x00000018
-#define TEXTURE_FORMAT_EXT_G16R16I 0x00000019
-#define TEXTURE_FORMAT_EXT_A16B16G16R16I 0x0000001a
-#define TEXTURE_FORMAT_EXT_B10G11R11F 0x0000001b
-#define TEXTURE_FORMAT_EXT_A2B10G10R10UI 0x0000001c
-#define TEXTURE_FILTER_NONE 0x00000000
-#define TEXTURE_FILTER_NEAREST 0x00000001
-#define TEXTURE_FILTER_LINEAR 0x00000002
-#define TEXTURE_FILTER_ANISOTROPIC 0x00000003
-#define TEXTURE_TYPE_NONE 0x00000000
-#define TEXTURE_TYPE_2D 0x00000002
-#define TEXTURE_TYPE_CUBE_MAP 0x00000005
-#define TEXTURE_WRAPMODE_REPEAT 0x00000000
-#define TEXTURE_WRAPMODE_MIRRORED_REPEAT 0x00000001
-#define TEXTURE_WRAPMODE_CLAMP_TO_EDGE 0x00000002
-#define TEXTURE_FACE_POS_X 0x00000000
-#define TEXTURE_FACE_NEG_X 0x00000001
-#define TEXTURE_FACE_POS_Y 0x00000002
-#define TEXTURE_FACE_NEG_Y 0x00000003
-#define TEXTURE_FACE_POS_Z 0x00000004
-#define TEXTURE_FACE_NEG_Z 0x00000005
-#define TEXTURE_SWIZZLE_RED 0x00000000
-#define TEXTURE_SWIZZLE_GREEN 0x00000001
-#define TEXTURE_SWIZZLE_BLUE 0x00000002
-#define TEXTURE_SWIZZLE_ALPHA 0x00000003
-#define TEXTURE_SWIZZLE_ZERO 0x00000004
-#define TEXTURE_SWIZZLE_ONE 0x00000005
-#define TEXTURE_HALIGN_FOUR 0x00000000
-#define TEXTURE_HALIGN_SIXTEEN 0x00000001
-#define TEXTURE_HALIGN_SUPER_TILED 0x00000002
-#define TEXTURE_HALIGN_SPLIT_TILED 0x00000003
-#define TEXTURE_HALIGN_SPLIT_SUPER_TILED 0x00000004
+#define RS_FORMAT_R8 0x00000023
#define LOGIC_OP_CLEAR 0x00000000
#define LOGIC_OP_NOR 0x00000001
#define LOGIC_OP_AND_INVERTED 0x00000002
@@ -292,6 +219,47 @@
#define VIVS_VS_INST_ADDR 0x0000086c
+#define VIVS_VS_HALTI5_UNK00870 0x00000870
+
+#define VIVS_VS_NEWRANGE_LOW 0x00000874
+
+#define VIVS_VS_HALTI5_UNK00878 0x00000878
+
+#define VIVS_VS_HALTI5_UNK00880 0x00000880
+
+#define VIVS_VS_HALTI1_UNK00884 0x00000884
+
+#define VIVS_VS_UNK0088C 0x0000088c
+
+#define VIVS_VS_ICACHE_UNK00890 0x00000890
+
+#define VIVS_VS_HALTI5_UNK00898(i0) (0x00000898 + 0x4*(i0))
+#define VIVS_VS_HALTI5_UNK00898__ESIZE 0x00000004
+#define VIVS_VS_HALTI5_UNK00898__LEN 0x00000002
+
+#define VIVS_VS_HALTI5_UNK008A0 0x000008a0
+
+#define VIVS_VS_HALTI5_UNK008A8 0x000008a8
+
+#define VIVS_VS_ICACHE_INVALIDATE 0x000008b0
+#define VIVS_VS_ICACHE_INVALIDATE_UNK0 0x00000001
+#define VIVS_VS_ICACHE_INVALIDATE_UNK1 0x00000002
+#define VIVS_VS_ICACHE_INVALIDATE_UNK2 0x00000004
+#define VIVS_VS_ICACHE_INVALIDATE_UNK3 0x00000008
+#define VIVS_VS_ICACHE_INVALIDATE_UNK4 0x00000010
+
+#define VIVS_VS_HALTI5_UNK008B8 0x000008b8
+
+#define VIVS_VS_NEWRANGE_HIGH 0x000008bc
+
+#define VIVS_VS_HALTI5_UNK008C0(i0) (0x000008c0 + 0x4*(i0))
+#define VIVS_VS_HALTI5_UNK008C0__ESIZE 0x00000004
+#define VIVS_VS_HALTI5_UNK008C0__LEN 0x00000008
+
+#define VIVS_VS_HALTI5_UNK008E0(i0) (0x000008e0 + 0x4*(i0))
+#define VIVS_VS_HALTI5_UNK008E0__ESIZE 0x00000004
+#define VIVS_VS_HALTI5_UNK008E0__LEN 0x00000008
+
#define VIVS_VS_INST_MEM(i0) (0x00004000 + 0x4*(i0))
#define VIVS_VS_INST_MEM__ESIZE 0x00000004
#define VIVS_VS_INST_MEM__LEN 0x00000400
@@ -300,6 +268,10 @@
#define VIVS_VS_UNIFORMS__ESIZE 0x00000004
#define VIVS_VS_UNIFORMS__LEN 0x00000400
+#define VIVS_VS_HALTI5_UNK15600 0x00015600
+
+#define VIVS_VS_HALTI5_UNK15604 0x00015604
+
#define VIVS_CL 0x00000000
#define VIVS_CL_CONFIG 0x00000900
@@ -391,6 +363,12 @@
#define VIVS_CL_UNK00954 0x00000954
+#define VIVS_CL_HALTI5_UNK00958 0x00000958
+
+#define VIVS_CL_HALTI5_UNK0095C 0x0000095c
+
+#define VIVS_CL_HALTI5_UNK00960 0x00000960
+
#define VIVS_PA 0x00000000
#define VIVS_PA_VIEWPORT_SCALE_X 0x00000a00
@@ -409,9 +387,11 @@
#define VIVS_PA_POINT_SIZE 0x00000a1c
+#define VIVS_PA_UNK00A24 0x00000a24
+
#define VIVS_PA_SYSTEM_MODE 0x00000a28
-#define VIVS_PA_SYSTEM_MODE_UNK0 0x00000001
-#define VIVS_PA_SYSTEM_MODE_UNK4 0x00000010
+#define VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST 0x00000001
+#define VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER 0x00000010
#define VIVS_PA_W_CLIP_LIMIT 0x00000a2c
@@ -473,6 +453,12 @@
#define VIVS_PA_ZFARCLIPPING 0x00000a8c
+#define VIVS_PA_HALTI5_UNK00A90(i0) (0x00000a90 + 0x4*(i0))
+#define VIVS_PA_HALTI5_UNK00A90__ESIZE 0x00000004
+#define VIVS_PA_HALTI5_UNK00A90__LEN 0x00000004
+
+#define VIVS_PA_HALTI5_UNK00AA8 0x00000aa8
+
#define VIVS_SE 0x00000000
#define VIVS_SE_SCISSOR_LEFT 0x00000c00
@@ -518,6 +504,10 @@
#define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT 12
#define VIVS_RA_HDEPTH_CONTROL_COMPARE(x) (((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK)
+#define VIVS_RA_UNK00E24 0x00000e24
+
+#define VIVS_RA_HALTI5_UNK00E34 0x00000e34
+
#define VIVS_RA_CENTROID_TABLE(i0) (0x00000e40 + 0x4*(i0))
#define VIVS_RA_CENTROID_TABLE__ESIZE 0x00000004
#define VIVS_RA_CENTROID_TABLE__LEN 0x00000010
@@ -561,11 +551,43 @@
#define VIVS_PS_INST_ADDR 0x00001028
+#define VIVS_PS_UNK0102C 0x0000102c
+
#define VIVS_PS_CONTROL_EXT 0x00001030
#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK 0x00000003
#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT 0
#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT(x) (((x) << VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT) & VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK)
+#define VIVS_PS_UNK01034 0x00001034
+
+#define VIVS_PS_UNK01038 0x00001038
+
+#define VIVS_PS_HALTI3_UNK0103C 0x0000103c
+
+#define VIVS_PS_UNK01040(i0) (0x00001040 + 0x4*(i0))
+#define VIVS_PS_UNK01040__ESIZE 0x00000004
+#define VIVS_PS_UNK01040__LEN 0x00000002
+
+#define VIVS_PS_UNK01048 0x00001048
+
+#define VIVS_PS_ICACHE_UNK0104C 0x0000104c
+
+#define VIVS_PS_HALTI4_UNK01054 0x00001054
+
+#define VIVS_PS_HALTI5_UNK01058 0x00001058
+
+#define VIVS_PS_HALTI5_UNK01080(i0) (0x00001080 + 0x4*(i0))
+#define VIVS_PS_HALTI5_UNK01080__ESIZE 0x00000004
+#define VIVS_PS_HALTI5_UNK01080__LEN 0x00000004
+
+#define VIVS_PS_NEWRANGE_LOW 0x0000087c
+
+#define VIVS_PS_NEWRANGE_HIGH 0x00001090
+
+#define VIVS_PS_HALTI5_UNK01094 0x00001094
+
+#define VIVS_PS_HALTI5_UNK01098 0x00001098
+
#define VIVS_PS_INST_MEM(i0) (0x00006000 + 0x4*(i0))
#define VIVS_PS_INST_MEM__ESIZE 0x00000004
#define VIVS_PS_INST_MEM__LEN 0x00000400
@@ -574,6 +596,122 @@
#define VIVS_PS_UNIFORMS__ESIZE 0x00000004
#define VIVS_PS_UNIFORMS__LEN 0x00000400
+#define VIVS_GS 0x00000000
+
+#define VIVS_GS_UNK01100 0x00001100
+
+#define VIVS_GS_UNK01104 0x00001104
+
+#define VIVS_GS_UNK01108 0x00001108
+
+#define VIVS_GS_UNK0110C 0x0000110c
+
+#define VIVS_GS_UNK01110 0x00001110
+
+#define VIVS_GS_UNK01114 0x00001114
+
+#define VIVS_GS_UNK0111C 0x0000111c
+
+#define VIVS_GS_UNK01120(i0) (0x00001120 + 0x4*(i0))
+#define VIVS_GS_UNK01120__ESIZE 0x00000004
+#define VIVS_GS_UNK01120__LEN 0x00000008
+
+#define VIVS_GS_UNK01140 0x00001140
+
+#define VIVS_GS_UNK01144 0x00001144
+
+#define VIVS_GS_UNK01148 0x00001148
+
+#define VIVS_GS_UNK0114C 0x0000114c
+
+#define VIVS_GS_UNK01154 0x00001154
+
+#define VIVS_TCS 0x00000000
+
+#define VIVS_TCS_UNK007C0 0x000007c0
+
+#define VIVS_TCS_UNK14A00 0x00014a00
+
+#define VIVS_TCS_UNK14A04 0x00014a04
+
+#define VIVS_TCS_UNK14A08 0x00014a08
+
+#define VIVS_TCS_UNK14A10 0x00014a10
+
+#define VIVS_TCS_UNK14A14 0x00014a14
+
+#define VIVS_TCS_UNK14A18 0x00014a18
+
+#define VIVS_TCS_UNK14A1C 0x00014a1c
+
+#define VIVS_TCS_UNK14A20(i0) (0x00014a20 + 0x4*(i0))
+#define VIVS_TCS_UNK14A20__ESIZE 0x00000004
+#define VIVS_TCS_UNK14A20__LEN 0x00000008
+
+#define VIVS_TCS_UNK14A40 0x00014a40
+
+#define VIVS_TCS_UNK14A44 0x00014a44
+
+#define VIVS_TCS_UNK14A4C 0x00014a4c
+
+#define VIVS_TES 0x00000000
+
+#define VIVS_TES_UNK14B00 0x00014b00
+
+#define VIVS_TES_UNK14B04 0x00014b04
+
+#define VIVS_TES_UNK14B08 0x00014b08
+
+#define VIVS_TES_UNK14B0C 0x00014b0c
+
+#define VIVS_TES_UNK14B14 0x00014b14
+
+#define VIVS_TES_UNK14B18 0x00014b18
+
+#define VIVS_TES_UNK14B1C 0x00014b1c
+
+#define VIVS_TES_UNK14B20 0x00014b20
+
+#define VIVS_TES_UNK14B24 0x00014b24
+
+#define VIVS_TES_UNK14B2C 0x00014b2c
+
+#define VIVS_TES_UNK14B34 0x00014b34
+
+#define VIVS_TES_UNK14B40(i0) (0x00014b40 + 0x4*(i0))
+#define VIVS_TES_UNK14B40__ESIZE 0x00000004
+#define VIVS_TES_UNK14B40__LEN 0x00000008
+
+#define VIVS_TFB 0x00000000
+
+#define VIVS_TFB_UNK1C000 0x0001c000
+
+#define VIVS_TFB_UNK1C008 0x0001c008
+
+#define VIVS_TFB_FLUSH 0x0001c00c
+
+#define VIVS_TFB_UNK1C014 0x0001c014
+
+#define VIVS_TFB_UNK1C040(i0) (0x0001c040 + 0x4*(i0))
+#define VIVS_TFB_UNK1C040__ESIZE 0x00000004
+#define VIVS_TFB_UNK1C040__LEN 0x00000004
+
+#define VIVS_TFB_UNK1C080(i0) (0x0001c080 + 0x4*(i0))
+#define VIVS_TFB_UNK1C080__ESIZE 0x00000004
+#define VIVS_TFB_UNK1C080__LEN 0x00000004
+
+#define VIVS_TFB_UNK1C0C0(i0) (0x0001c0c0 + 0x4*(i0))
+#define VIVS_TFB_UNK1C0C0__ESIZE 0x00000004
+#define VIVS_TFB_UNK1C0C0__LEN 0x00000004
+
+#define VIVS_TFB_UNK1C100(i0) (0x0001c100 + 0x4*(i0))
+#define VIVS_TFB_UNK1C100__ESIZE 0x00000004
+#define VIVS_TFB_UNK1C100__LEN 0x00000004
+
+#define VIVS_TFB_UNK1C800(i0) (0x0001c800 + 0x4*(i0))
+#define VIVS_TFB_UNK1C800__ESIZE 0x00000004
+#define VIVS_TFB_UNK1C800__LEN 0x00000200
+
#define VIVS_PE 0x00000000
#define VIVS_PE_DEPTH_CONFIG 0x00001400
@@ -738,7 +876,7 @@
#define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK 0x00020000
#define VIVS_PE_COLOR_FORMAT_SUPER_TILED 0x00100000
#define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK 0x00200000
-#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK 0x3f000000
+#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK 0x7f000000
#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT 24
#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT(x) (((x) << VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK)
#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT_MASK 0x80000000
@@ -770,6 +908,8 @@
#define VIVS_PE_PIPE_ADDR_UNK01520(i0) (0x00001520 + 0x4*(i0))
+#define VIVS_PE_PIPE_ADDR_UNK01540(i0) (0x00001540 + 0x4*(i0))
+
#define VIVS_PE_STENCIL_CONFIG_EXT 0x000014a0
#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK 0x000000ff
#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT 0
@@ -799,6 +939,8 @@
#define VIVS_PE_LOGIC_OP_UNK24__SHIFT 24
#define VIVS_PE_LOGIC_OP_UNK24(x) (((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK)
#define VIVS_PE_LOGIC_OP_UNK24_MASK 0x08000000
+#define VIVS_PE_LOGIC_OP_UNK31_MASK 0x40000000
+#define VIVS_PE_LOGIC_OP_UNK31 0x80000000
#define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0))
#define VIVS_PE_DITHER__ESIZE 0x00000004
@@ -828,6 +970,12 @@
#define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT 8
#define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK)
+#define VIVS_PE_HALTI3_UNK014BC 0x000014bc
+
+#define VIVS_PE_HALTI4_UNK014C0 0x000014c0
+
+#define VIVS_PE_ROBUSTNESS_UNK014C4 0x000014c4
+
#define VIVS_PE_UNK01580(i0) (0x00001580 + 0x4*(i0))
#define VIVS_PE_UNK01580__ESIZE 0x00000004
#define VIVS_PE_UNK01580__LEN 0x00000003
@@ -850,6 +998,30 @@
#define VIVS_PE_RT_CONFIG_UNK16__SHIFT 16
#define VIVS_PE_RT_CONFIG_UNK16(x) (((x) << VIVS_PE_RT_CONFIG_UNK16__SHIFT) & VIVS_PE_RT_CONFIG_UNK16__MASK)
+#define VIVS_PE_HALTI5_UNK14920(i0) (0x00014920 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14920__ESIZE 0x00000004
+#define VIVS_PE_HALTI5_UNK14920__LEN 0x00000007
+
+#define VIVS_PE_HALTI5_UNK14940(i0) (0x00014940 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14940__ESIZE 0x00000004
+#define VIVS_PE_HALTI5_UNK14940__LEN 0x00000007
+
+#define VIVS_PE_HALTI5_UNK14960(i0) (0x00014960 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14960__ESIZE 0x00000004
+#define VIVS_PE_HALTI5_UNK14960__LEN 0x00000007
+
+#define VIVS_PE_HALTI5_UNK14980(i0) (0x00014980 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14980__ESIZE 0x00000004
+#define VIVS_PE_HALTI5_UNK14980__LEN 0x00000007
+
+#define VIVS_PE_HALTI5_UNK149A0(i0) (0x000149a0 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK149A0__ESIZE 0x00000004
+#define VIVS_PE_HALTI5_UNK149A0__LEN 0x00000007
+
+#define VIVS_PE_ROBUSTNESS_UNK149C0(i0) (0x000149c0 + 0x4*(i0))
+#define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE 0x00000004
+#define VIVS_PE_ROBUSTNESS_UNK149C0__LEN 0x00000008
+
#define VIVS_CO 0x00000000
#define VIVS_CO_UNK03008 0x00003008
@@ -874,6 +1046,8 @@
#define VIVS_CO_UNK03048 0x00003048
+#define VIVS_CO_ICACHE_UNK0304C 0x0000304c
+
#define VIVS_CO_SAMPLER(i0) (0x00000000 + 0x4*(i0))
#define VIVS_CO_SAMPLER__ESIZE 0x00000004
#define VIVS_CO_SAMPLER__LEN 0x00000008
@@ -985,15 +1159,13 @@
#define VIVS_RS_EXTRA_CONFIG_UNK20 0x00100000
#define VIVS_RS_EXTRA_CONFIG_UNK28 0x10000000
-#define VIVS_RS_UNK016B0 0x000016b0
+#define VIVS_RS_KICKER_INPLACE 0x000016b0
#define VIVS_RS_UNK016B4 0x000016b4
#define VIVS_RS_SINGLE_BUFFER 0x000016b8
#define VIVS_RS_SINGLE_BUFFER_ENABLE 0x00000001
-#define VIVS_RS_UNK016BC 0x000016bc
-
#define VIVS_RS_PIPE(i0) (0x00000000 + 0x4*(i0))
#define VIVS_RS_PIPE__ESIZE 0x00000004
#define VIVS_RS_PIPE__LEN 0x00000008
@@ -1022,16 +1194,14 @@
#define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE 0x00000010
#define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE 0x00000020
#define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION 0x00000040
-#define VIVS_TS_MEM_CONFIG_MSAA 0x00000080
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__MASK 0x00000f00
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__SHIFT 8
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A4R4G4B4 0x00000000
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A1R5G5B5 0x00000100
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_R5G6B5 0x00000200
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8 0x00000300
-#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_X8R8G8B8 0x00000400
+#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION 0x00000080
+#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK 0x00000f00
+#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT 8
+#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK)
#define VIVS_TS_MEM_CONFIG_UNK12 0x00001000
#define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE 0x00002000
+#define VIVS_TS_MEM_CONFIG_UNK14 0x00004000
+#define VIVS_TS_MEM_CONFIG_UNK21 0x00200000
#define VIVS_TS_COLOR_STATUS_BASE 0x00001658
@@ -1055,6 +1225,8 @@
#define VIVS_TS_HDEPTH_SIZE 0x000016ac
+#define VIVS_TS_COLOR_CLEAR_VALUE_EXT 0x000016bc
+
#define VIVS_TS_SAMPLER(i0) (0x00000000 + 0x4*(i0))
#define VIVS_TS_SAMPLER__ESIZE 0x00000004
#define VIVS_TS_SAMPLER__LEN 0x00000008
@@ -1066,6 +1238,9 @@
#define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK 0x000000f0
#define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT 4
#define VIVS_TS_SAMPLER_CONFIG_FORMAT(x) (((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK)
+#define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK 0x00003800
+#define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT 11
+#define VIVS_TS_SAMPLER_CONFIG_UNK11(x) (((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK)
#define VIVS_TS_SAMPLER_STATUS_BASE(i0) (0x00001740 + 0x4*(i0))
@@ -1073,6 +1248,8 @@
#define VIVS_TS_SAMPLER_CLEAR_VALUE2(i0) (0x00001780 + 0x4*(i0))
+#define VIVS_TS_SAMPLER_SURFACE_BASE(i0) (0x00001a80 + 0x4*(i0))
+
#define VIVS_TS_RT(i0) (0x00000000 + 0x4*(i0))
#define VIVS_TS_RT__ESIZE 0x00000004
#define VIVS_TS_RT__LEN 0x00000008
@@ -1181,10 +1358,19 @@
#define VIVS_TE_SAMPLER_UNK02140(i0) (0x00002140 + 0x4*(i0))
-#define VIVS_TE_SAMPLER_UNK02180(i0) (0x00002180 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_3D_CONFIG(i0) (0x00002180 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff
+#define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0
+#define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK)
+#define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000
+#define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16
+#define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK)
+#define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000
+#define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28
+#define VIVS_TE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK)
#define VIVS_TE_SAMPLER_CONFIG1(i0) (0x000021c0 + 0x4*(i0))
-#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000001f
+#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f
#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0
#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700
@@ -1199,6 +1385,11 @@
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK 0x00800000
+#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT 23
+#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE_128 0x00000000
+#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE_256 0x00800000
+#define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000
#define VIVS_TE_SAMPLER_CONFIG1_UNK25 0x02000000
#define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000
#define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT 26
@@ -1212,9 +1403,9 @@
#define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE 0x00000040
#define VIVS_TE_SAMPLER_LOD_ADDR__LEN 0x0000000e
-#define VIVS_TE_SAMPLER_UNK02C00(i0, i1) (0x00002c00 + 0x4*(i0) + 0x40*(i1))
-#define VIVS_TE_SAMPLER_UNK02C00__ESIZE 0x00000040
-#define VIVS_TE_SAMPLER_UNK02C00__LEN 0x0000000e
+#define VIVS_TE_SAMPLER_LINEAR_STRIDE(i0, i1) (0x00002c00 + 0x4*(i0) + 0x40*(i1))
+#define VIVS_TE_SAMPLER_LINEAR_STRIDE__ESIZE 0x00000040
+#define VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN 0x0000000e
#define VIVS_NTE 0x00000000
@@ -1286,10 +1477,19 @@
#define VIVS_NTE_SAMPLER_UNK10280(i0) (0x00010280 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_UNK10300(i0) (0x00010300 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_3D_CONFIG(i0) (0x00010300 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff
+#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0
+#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK)
+#define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000
+#define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16
+#define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK)
+#define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000
+#define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28
+#define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK)
#define VIVS_NTE_SAMPLER_CONFIG1(i0) (0x00010380 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000001f
+#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f
#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0
#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700
@@ -1304,6 +1504,11 @@
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK 0x00800000
+#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT 23
+#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE_128 0x00000000
+#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE_256 0x00800000
+#define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000
#define VIVS_NTE_SAMPLER_CONFIG1_UNK25 0x02000000
#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000
#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT 26
@@ -1313,9 +1518,38 @@
#define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_UNK10500(i0) (0x00010500 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_ASTC0(i0) (0x00010500 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_UNK10700(i0) (0x00010700 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_ASTC1(i0) (0x00010580 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_ASTC2(i0) (0x00010600 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010600 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_BASELOD(i0) (0x00010700 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_BASELOD_UNK23 0x00800000
+#define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK 0x0000000f
+#define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT 0
+#define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK)
+#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK 0x00000f00
+#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT 8
+#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK)
+
+#define VIVS_NTE_SAMPLER_UNK10780(i0) (0x00010780 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11000(i0) (0x00011000 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11080(i0) (0x00011080 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11100(i0) (0x00011100 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11180(i0) (0x00011180 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_HALTI4_UNK11200(i0) (0x00011200 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_HALTI4_UNK11280(i0) (0x00011280 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11300(i0) (0x00011300 + 0x4*(i0))
#define VIVS_NTE_SAMPLER_ADDR(i0) (0x00010800 + 0x40*(i0))
#define VIVS_NTE_SAMPLER_ADDR__ESIZE 0x00000040
@@ -1333,6 +1567,94 @@
#define VIVS_NTE_UNK12400__ESIZE 0x00000004
#define VIVS_NTE_UNK12400__LEN 0x00000100
+#define VIVS_NTE_HALTI3_UNK14C00(i0) (0x00014c00 + 0x4*(i0))
+#define VIVS_NTE_HALTI3_UNK14C00__ESIZE 0x00000004
+#define VIVS_NTE_HALTI3_UNK14C00__LEN 0x00000010
+
+#define VIVS_NTE_DESCRIPTOR_UNK14C40 0x00014c40
+#define VIVS_NTE_DESCRIPTOR_UNK14C40_UNK0 0x00000001
+
+#define VIVS_NTE_UNK14C44 0x00014c44
+
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE 0x00014c48
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK 0x000001ff
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT 0
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX(x) (((x) << VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT) & VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK)
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_UNK29 0x20000000
+
+#define VIVS_NTE_DESCRIPTOR(i0) (0x00000000 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR__ESIZE 0x00000004
+#define VIVS_NTE_DESCRIPTOR__LEN 0x00000080
+
+#define VIVS_NTE_DESCRIPTOR_ADDR_MIRROR(i0) (0x00015800 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_MIRROR(i0) (0x00015a00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_ADDR(i0) (0x00015c00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0) (0x00015e00 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK 0x00000003
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT 0
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK)
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK 0x0000001c
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT 2
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK)
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0) (0x00016000 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_MIRROR(i0) (0x00016200 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIRROR(i0) (0x00016400 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0) (0x00016600 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK17400_MIRROR(i0) (0x00016800 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0) (0x00016c00 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK 0x00000007
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT 0
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK 0x00000038
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT 3
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK 0x000001c0
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT 6
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK 0x00000600
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT 9
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK 0x00001800
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT 11
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK 0x00006000
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT 13
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK23 0x00800000
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0) (0x00016e00 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1 0x00000002
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_SRGB 0x00000004
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK3 0x00000008
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK 0x00000030
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT 4
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK)
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(i0) (0x00017000 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK 0x0000ffff
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT 0
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK 0xffff0000
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT 16
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK)
+
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(i0) (0x00017200 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK 0x0000ffff
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT 0
+#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK)
+
+#define VIVS_NTE_DESCRIPTOR_UNK17400(i0) (0x00017400 + 0x4*(i0))
+
#define VIVS_SH 0x00000000
#define VIVS_SH_UNK20000(i0) (0x00020000 + 0x4*(i0))
@@ -1351,5 +1673,13 @@
#define VIVS_SH_UNIFORMS__ESIZE 0x00000004
#define VIVS_SH_UNIFORMS__LEN 0x00000800
+#define VIVS_SH_HALTI5_UNIFORMS_MIRROR(i0) (0x00034000 + 0x4*(i0))
+#define VIVS_SH_HALTI5_UNIFORMS_MIRROR__ESIZE 0x00000004
+#define VIVS_SH_HALTI5_UNIFORMS_MIRROR__LEN 0x00000800
+
+#define VIVS_SH_HALTI5_UNIFORMS(i0) (0x00036000 + 0x4*(i0))
+#define VIVS_SH_HALTI5_UNIFORMS__ESIZE 0x00000004
+#define VIVS_SH_HALTI5_UNIFORMS__LEN 0x00000800
+
#endif /* STATE_3D_XML */
diff --git a/src/state_blt.xml.h b/src/state_blt.xml.h
new file mode 100644
index 0000000..4958b74
--- /dev/null
+++ b/src/state_blt.xml.h
@@ -0,0 +1,264 @@
+#ifndef STATE_BLT_XML
+#define STATE_BLT_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- state.xml ( 25532 bytes, from 2017-10-13 12:19:04)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
+- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
+- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
+- state_3d.xml ( 74317 bytes, from 2017-10-13 12:43:31)
+- state_blt.xml ( 11153 bytes, from 2017-10-13 12:39:38)
+- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
+
+Copyright (C) 2012-2017 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define BLT_TILING_LINEAR 0x00000000
+#define BLT_TILING_SUPERTILED 0x00000003
+#define BLT_FORMAT_A4R4G4B4 0x00000001
+#define BLT_FORMAT_A8R8G8B8 0x00000006
+#define BLT_FORMAT_A16R16G16B16 0x0000001c
+#define BLT_FORMAT_R8G8B8 0x00000022
+#define BLT_FORMAT_R8 0x00000023
+#define BLT_FORMAT_R8G8 0x00000024
+#define BLT_IMAGE_CONFIG_TS 0x00000001
+#define BLT_IMAGE_CONFIG_COMPRESSION 0x00000002
+#define BLT_IMAGE_CONFIG_COMPRESSION_FORMAT__MASK 0x000000f0
+#define BLT_IMAGE_CONFIG_COMPRESSION_FORMAT__SHIFT 4
+#define BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(x) (((x) << BLT_IMAGE_CONFIG_COMPRESSION_FORMAT__SHIFT) & BLT_IMAGE_CONFIG_COMPRESSION_FORMAT__MASK)
+#define BLT_IMAGE_CONFIG_UNK8 0x00000100
+#define BLT_IMAGE_CONFIG_SWIZ_R__MASK 0x00000600
+#define BLT_IMAGE_CONFIG_SWIZ_R__SHIFT 9
+#define BLT_IMAGE_CONFIG_SWIZ_R(x) (((x) << BLT_IMAGE_CONFIG_SWIZ_R__SHIFT) & BLT_IMAGE_CONFIG_SWIZ_R__MASK)
+#define BLT_IMAGE_CONFIG_SWIZ_G__MASK 0x00001800
+#define BLT_IMAGE_CONFIG_SWIZ_G__SHIFT 11
+#define BLT_IMAGE_CONFIG_SWIZ_G(x) (((x) << BLT_IMAGE_CONFIG_SWIZ_G__SHIFT) & BLT_IMAGE_CONFIG_SWIZ_G__MASK)
+#define BLT_IMAGE_CONFIG_SWIZ_B__MASK 0x00006000
+#define BLT_IMAGE_CONFIG_SWIZ_B__SHIFT 13
+#define BLT_IMAGE_CONFIG_SWIZ_B(x) (((x) << BLT_IMAGE_CONFIG_SWIZ_B__SHIFT) & BLT_IMAGE_CONFIG_SWIZ_B__MASK)
+#define BLT_IMAGE_CONFIG_SWIZ_A__MASK 0x00018000
+#define BLT_IMAGE_CONFIG_SWIZ_A__SHIFT 15
+#define BLT_IMAGE_CONFIG_SWIZ_A(x) (((x) << BLT_IMAGE_CONFIG_SWIZ_A__SHIFT) & BLT_IMAGE_CONFIG_SWIZ_A__MASK)
+#define BLT_IMAGE_CONFIG_CACHE_MODE__MASK 0x00020000
+#define BLT_IMAGE_CONFIG_CACHE_MODE__SHIFT 17
+#define BLT_IMAGE_CONFIG_CACHE_MODE_128 0x00000000
+#define BLT_IMAGE_CONFIG_CACHE_MODE_256 0x00020000
+#define BLT_IMAGE_CONFIG_FLIP_Y 0x00080000
+#define BLT_IMAGE_CONFIG_FROM_SUPERTILED 0x00200000
+#define BLT_IMAGE_CONFIG_UNK22 0x00400000
+#define BLT_IMAGE_CONFIG_TO_SUPERTILED 0x04000000
+#define VIVS_BLT 0x00000000
+
+#define VIVS_BLT_SRC_ADDR 0x00014000
+
+#define VIVS_BLT_SRC_STRIDE 0x00014008
+#define VIVS_BLT_SRC_STRIDE_STRIDE__MASK 0x000fffff
+#define VIVS_BLT_SRC_STRIDE_STRIDE__SHIFT 0
+#define VIVS_BLT_SRC_STRIDE_STRIDE(x) (((x) << VIVS_BLT_SRC_STRIDE_STRIDE__SHIFT) & VIVS_BLT_SRC_STRIDE_STRIDE__MASK)
+#define VIVS_BLT_SRC_STRIDE_FORMAT__MASK 0x1fe00000
+#define VIVS_BLT_SRC_STRIDE_FORMAT__SHIFT 21
+#define VIVS_BLT_SRC_STRIDE_FORMAT(x) (((x) << VIVS_BLT_SRC_STRIDE_FORMAT__SHIFT) & VIVS_BLT_SRC_STRIDE_FORMAT__MASK)
+#define VIVS_BLT_SRC_STRIDE_TILING__MASK 0x60000000
+#define VIVS_BLT_SRC_STRIDE_TILING__SHIFT 29
+#define VIVS_BLT_SRC_STRIDE_TILING(x) (((x) << VIVS_BLT_SRC_STRIDE_TILING__SHIFT) & VIVS_BLT_SRC_STRIDE_TILING__MASK)
+
+#define VIVS_BLT_SRC_CONFIG 0x0001400c
+
+#define VIVS_BLT_SRC_TS 0x00014010
+
+#define VIVS_BLT_SRC_POS 0x00014014
+#define VIVS_BLT_SRC_POS_X__MASK 0x0000ffff
+#define VIVS_BLT_SRC_POS_X__SHIFT 0
+#define VIVS_BLT_SRC_POS_X(x) (((x) << VIVS_BLT_SRC_POS_X__SHIFT) & VIVS_BLT_SRC_POS_X__MASK)
+#define VIVS_BLT_SRC_POS_Y__MASK 0xffff0000
+#define VIVS_BLT_SRC_POS_Y__SHIFT 16
+#define VIVS_BLT_SRC_POS_Y(x) (((x) << VIVS_BLT_SRC_POS_Y__SHIFT) & VIVS_BLT_SRC_POS_Y__MASK)
+
+#define VIVS_BLT_DEST_ADDR 0x00014018
+
+#define VIVS_BLT_DEST_TS 0x00014020
+
+#define VIVS_BLT_DEST_STRIDE 0x00014024
+#define VIVS_BLT_DEST_STRIDE_STRIDE__MASK 0x000fffff
+#define VIVS_BLT_DEST_STRIDE_STRIDE__SHIFT 0
+#define VIVS_BLT_DEST_STRIDE_STRIDE(x) (((x) << VIVS_BLT_DEST_STRIDE_STRIDE__SHIFT) & VIVS_BLT_DEST_STRIDE_STRIDE__MASK)
+#define VIVS_BLT_DEST_STRIDE_FORMAT__MASK 0x1fe00000
+#define VIVS_BLT_DEST_STRIDE_FORMAT__SHIFT 21
+#define VIVS_BLT_DEST_STRIDE_FORMAT(x) (((x) << VIVS_BLT_DEST_STRIDE_FORMAT__SHIFT) & VIVS_BLT_DEST_STRIDE_FORMAT__MASK)
+#define VIVS_BLT_DEST_STRIDE_TILING__MASK 0x60000000
+#define VIVS_BLT_DEST_STRIDE_TILING__SHIFT 29
+#define VIVS_BLT_DEST_STRIDE_TILING(x) (((x) << VIVS_BLT_DEST_STRIDE_TILING__SHIFT) & VIVS_BLT_DEST_STRIDE_TILING__MASK)
+
+#define VIVS_BLT_DEST_CONFIG 0x00014028
+
+#define VIVS_BLT_DEST_POS 0x0001402c
+#define VIVS_BLT_DEST_POS_X__MASK 0x0000ffff
+#define VIVS_BLT_DEST_POS_X__SHIFT 0
+#define VIVS_BLT_DEST_POS_X(x) (((x) << VIVS_BLT_DEST_POS_X__SHIFT) & VIVS_BLT_DEST_POS_X__MASK)
+#define VIVS_BLT_DEST_POS_Y__MASK 0xffff0000
+#define VIVS_BLT_DEST_POS_Y__SHIFT 16
+#define VIVS_BLT_DEST_POS_Y(x) (((x) << VIVS_BLT_DEST_POS_Y__SHIFT) & VIVS_BLT_DEST_POS_Y__MASK)
+
+#define VIVS_BLT_IMAGE_SIZE 0x00014030
+#define VIVS_BLT_IMAGE_SIZE_WIDTH__MASK 0x0000ffff
+#define VIVS_BLT_IMAGE_SIZE_WIDTH__SHIFT 0
+#define VIVS_BLT_IMAGE_SIZE_WIDTH(x) (((x) << VIVS_BLT_IMAGE_SIZE_WIDTH__SHIFT) & VIVS_BLT_IMAGE_SIZE_WIDTH__MASK)
+#define VIVS_BLT_IMAGE_SIZE_HEIGHT__MASK 0xffff0000
+#define VIVS_BLT_IMAGE_SIZE_HEIGHT__SHIFT 16
+#define VIVS_BLT_IMAGE_SIZE_HEIGHT(x) (((x) << VIVS_BLT_IMAGE_SIZE_HEIGHT__SHIFT) & VIVS_BLT_IMAGE_SIZE_HEIGHT__MASK)
+
+#define VIVS_BLT_SRC_TS_CLEAR_VALUE0 0x00014034
+
+#define VIVS_BLT_SRC_TS_CLEAR_VALUE1 0x00014038
+
+#define VIVS_BLT_DEST_TS_CLEAR_VALUE0 0x0001403c
+
+#define VIVS_BLT_DEST_TS_CLEAR_VALUE1 0x00014040
+
+#define VIVS_BLT_CLEAR_COLOR0 0x00014044
+
+#define VIVS_BLT_CLEAR_COLOR1 0x00014048
+
+#define VIVS_BLT_UNK1404C 0x0001404c
+
+#define VIVS_BLT_UNK14050 0x00014050
+
+#define VIVS_BLT_BUFFER_SIZE 0x00014054
+
+#define VIVS_BLT_UNK14058 0x00014058
+
+#define VIVS_BLT_UNK1405C 0x0001405c
+
+#define VIVS_BLT_COMMAND 0x00014060
+#define VIVS_BLT_COMMAND_COMMAND__MASK 0x0000000f
+#define VIVS_BLT_COMMAND_COMMAND__SHIFT 0
+#define VIVS_BLT_COMMAND_COMMAND_CLEAR_IMAGE 0x00000001
+#define VIVS_BLT_COMMAND_COMMAND_COPY_IMAGE 0x00000002
+#define VIVS_BLT_COMMAND_COMMAND_COPY_BUFFER 0x00000003
+#define VIVS_BLT_COMMAND_COMMAND_YUV_TILE 0x00000005
+#define VIVS_BLT_COMMAND_COMMAND_GEN_MIPMAPS 0x00000006
+
+#define VIVS_BLT_CONFIG 0x00014064
+#define VIVS_BLT_CONFIG_SRC_ENDIAN__MASK 0x00000006
+#define VIVS_BLT_CONFIG_SRC_ENDIAN__SHIFT 1
+#define VIVS_BLT_CONFIG_SRC_ENDIAN(x) (((x) << VIVS_BLT_CONFIG_SRC_ENDIAN__SHIFT) & VIVS_BLT_CONFIG_SRC_ENDIAN__MASK)
+#define VIVS_BLT_CONFIG_DEST_ENDIAN__MASK 0x00000018
+#define VIVS_BLT_CONFIG_DEST_ENDIAN__SHIFT 3
+#define VIVS_BLT_CONFIG_DEST_ENDIAN(x) (((x) << VIVS_BLT_CONFIG_DEST_ENDIAN__SHIFT) & VIVS_BLT_CONFIG_DEST_ENDIAN__MASK)
+#define VIVS_BLT_CONFIG_UNK5 0x00000020
+#define VIVS_BLT_CONFIG_UNK6 0x00000040
+#define VIVS_BLT_CONFIG_CLEAR_BPP__MASK 0x00000380
+#define VIVS_BLT_CONFIG_CLEAR_BPP__SHIFT 7
+#define VIVS_BLT_CONFIG_CLEAR_BPP(x) (((x) << VIVS_BLT_CONFIG_CLEAR_BPP__SHIFT) & VIVS_BLT_CONFIG_CLEAR_BPP__MASK)
+
+#define VIVS_BLT_YUV 0x00000000
+
+#define VIVS_BLT_YUV_CONFIG 0x0001406c
+
+#define VIVS_BLT_YUV_UNK14070 0x00014070
+
+#define VIVS_BLT_YUV_SRC_YADDR 0x00014074
+
+#define VIVS_BLT_YUV_SRC_YSTRIDE 0x00014078
+
+#define VIVS_BLT_YUV_SRC_UADDR 0x0001407c
+
+#define VIVS_BLT_YUV_SRC_USTRIDE 0x00014080
+
+#define VIVS_BLT_YUV_SRC_VADDR 0x00014084
+
+#define VIVS_BLT_YUV_SRC_VSTRIDE 0x00014088
+
+#define VIVS_BLT_YUV_DEST_ADDR 0x0001408c
+
+#define VIVS_BLT_YUV_DEST_STRIDE 0x00014090
+
+#define VIVS_BLT_UNK1409C 0x0001409c
+
+#define VIVS_BLT_UNK140A0 0x000140a0
+
+#define VIVS_BLT_FENCE_OUT_ADDRESS 0x000140a4
+
+#define VIVS_BLT_FENCE_OUT_DATA_LOW 0x000140a8
+
+#define VIVS_BLT_SET_COMMAND 0x000140ac
+
+#define VIVS_BLT_UNK140B0 0x000140b0
+
+#define VIVS_BLT_FENCE_OUT_DATA_HIGH 0x000140b4
+
+#define VIVS_BLT_ENABLE 0x000140b8
+#define VIVS_BLT_ENABLE_ENABLE 0x00000001
+
+#define VIVS_BLT_SWIZZLE 0x000140bc
+#define VIVS_BLT_SWIZZLE_SRC_R__MASK 0x00000007
+#define VIVS_BLT_SWIZZLE_SRC_R__SHIFT 0
+#define VIVS_BLT_SWIZZLE_SRC_R(x) (((x) << VIVS_BLT_SWIZZLE_SRC_R__SHIFT) & VIVS_BLT_SWIZZLE_SRC_R__MASK)
+#define VIVS_BLT_SWIZZLE_SRC_G__MASK 0x00000038
+#define VIVS_BLT_SWIZZLE_SRC_G__SHIFT 3
+#define VIVS_BLT_SWIZZLE_SRC_G(x) (((x) << VIVS_BLT_SWIZZLE_SRC_G__SHIFT) & VIVS_BLT_SWIZZLE_SRC_G__MASK)
+#define VIVS_BLT_SWIZZLE_SRC_B__MASK 0x000001c0
+#define VIVS_BLT_SWIZZLE_SRC_B__SHIFT 6
+#define VIVS_BLT_SWIZZLE_SRC_B(x) (((x) << VIVS_BLT_SWIZZLE_SRC_B__SHIFT) & VIVS_BLT_SWIZZLE_SRC_B__MASK)
+#define VIVS_BLT_SWIZZLE_SRC_A__MASK 0x00000e00
+#define VIVS_BLT_SWIZZLE_SRC_A__SHIFT 9
+#define VIVS_BLT_SWIZZLE_SRC_A(x) (((x) << VIVS_BLT_SWIZZLE_SRC_A__SHIFT) & VIVS_BLT_SWIZZLE_SRC_A__MASK)
+#define VIVS_BLT_SWIZZLE_DEST_R__MASK 0x00007000
+#define VIVS_BLT_SWIZZLE_DEST_R__SHIFT 12
+#define VIVS_BLT_SWIZZLE_DEST_R(x) (((x) << VIVS_BLT_SWIZZLE_DEST_R__SHIFT) & VIVS_BLT_SWIZZLE_DEST_R__MASK)
+#define VIVS_BLT_SWIZZLE_DEST_G__MASK 0x00038000
+#define VIVS_BLT_SWIZZLE_DEST_G__SHIFT 15
+#define VIVS_BLT_SWIZZLE_DEST_G(x) (((x) << VIVS_BLT_SWIZZLE_DEST_G__SHIFT) & VIVS_BLT_SWIZZLE_DEST_G__MASK)
+#define VIVS_BLT_SWIZZLE_DEST_B__MASK 0x001c0000
+#define VIVS_BLT_SWIZZLE_DEST_B__SHIFT 18
+#define VIVS_BLT_SWIZZLE_DEST_B(x) (((x) << VIVS_BLT_SWIZZLE_DEST_B__SHIFT) & VIVS_BLT_SWIZZLE_DEST_B__MASK)
+#define VIVS_BLT_SWIZZLE_DEST_A__MASK 0x00e00000
+#define VIVS_BLT_SWIZZLE_DEST_A__SHIFT 21
+#define VIVS_BLT_SWIZZLE_DEST_A(x) (((x) << VIVS_BLT_SWIZZLE_DEST_A__SHIFT) & VIVS_BLT_SWIZZLE_DEST_A__MASK)
+
+#define VIVS_BLT_MIP(i0) (0x00000000 + 0x4*(i0))
+#define VIVS_BLT_MIP__ESIZE 0x00000004
+#define VIVS_BLT_MIP__LEN 0x0000000d
+
+#define VIVS_BLT_MIP_ADDR(i0) (0x000140c0 + 0x4*(i0))
+
+#define VIVS_BLT_MIP_STRIDE(i0) (0x00014300 + 0x4*(i0))
+
+#define VIVS_BLT_SRC_END 0x000140f4
+
+#define VIVS_BLT_DEST_END 0x00014334
+
+
+#endif /* STATE_BLT_XML */
diff --git a/src/state_hi.xml.h b/src/state_hi.xml.h
index 0c19559..487bf63 100644
--- a/src/state_hi.xml.h
+++ b/src/state_hi.xml.h
@@ -8,12 +8,14 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 19930 bytes, from 2017-01-07 14:27:54)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
-- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54)
+- state.xml ( 25532 bytes, from 2017-10-13 12:19:04)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 67197 bytes, from 2017-07-23 10:53:21)
+- state_3d.xml ( 74317 bytes, from 2017-10-13 12:43:31)
+- state_blt.xml ( 11153 bytes, from 2017-10-13 12:39:38)
- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
Copyright (C) 2012-2017 by the following authors:
@@ -219,6 +221,9 @@
#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0
#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK)
+#define VIVS_HI_COMPRESSION_FLAGS 0x00000090
+#define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040
+
#define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094
#define VIVS_HI_CHIP_SPECS_4 0x0000009c
@@ -230,6 +235,10 @@
#define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8
+#define VIVS_HI_BLT_INTR 0x000000d4
+
+#define VIVS_HI_AUXBIT 0x000000ec
+
#define VIVS_PM 0x00000000
#define VIVS_PM_POWER_CONTROLS 0x00000100
@@ -318,6 +327,14 @@
#define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004
#define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004
+#define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4
+
+#define VIVS_MMUv2_UNK001AC 0x000001ac
+
+#define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0))
+#define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004
+#define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008
+
#define VIVS_MC 0x00000000
#define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400
@@ -457,6 +474,9 @@
#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100
#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200
#define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00
+#define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000
+#define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24
+#define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000
#define VIVS_MC_PROFILE_CONFIG3 0x0000047c
@@ -470,7 +490,13 @@
#define VIVS_MC_START_COMPOSITION 0x00000554
-#define VIVS_MC_128B_MERGE 0x00000558
+#define VIVS_MC_FLAGS 0x00000558
+#define VIVS_MC_FLAGS_128B_MERGE 0x00000001
+#define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000
+
+#define VIVS_MC_L2_CACHE_CONFIG 0x0000055c
+
+#define VIVS_MC_PROFILE_L2_READ 0x00000564
#endif /* STATE_HI_XML */
diff --git a/src/state_vg.xml.h b/src/state_vg.xml.h
index 24c4636..3f9aac7 100644
--- a/src/state_vg.xml.h
+++ b/src/state_vg.xml.h
@@ -8,12 +8,14 @@
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 19930 bytes, from 2017-01-07 14:27:54)
-- common.xml ( 23529 bytes, from 2017-05-10 12:36:01)
-- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54)
+- state.xml ( 25532 bytes, from 2017-10-13 12:19:04)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 67197 bytes, from 2017-07-23 10:53:21)
+- state_3d.xml ( 74317 bytes, from 2017-10-13 12:43:31)
+- state_blt.xml ( 11153 bytes, from 2017-10-13 12:39:38)
- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
Copyright (C) 2012-2016 by the following authors:
diff --git a/src/texdesc_3d.xml.h b/src/texdesc_3d.xml.h
new file mode 100644
index 0000000..1f80382
--- /dev/null
+++ b/src/texdesc_3d.xml.h
@@ -0,0 +1,182 @@
+#ifndef TEXDESC_3D_XML
+#define TEXDESC_3D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- texdesc_3d.xml ( 3146 bytes, from 2017-10-13 12:18:33)
+- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
+- common.xml ( 26193 bytes, from 2017-10-13 12:18:24)
+- common_3d.xml ( 12531 bytes, from 2017-10-13 11:04:24)
+
+Copyright (C) 2012-2017 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define TEXDESC_LOD_ADDR(i0) (0x00000000 + 0x4*(i0))
+#define TEXDESC_LOD_ADDR__ESIZE 0x00000004
+#define TEXDESC_LOD_ADDR__LEN 0x00000010
+
+#define TEXDESC_CONFIG0 0x00000040
+#define TEXDESC_CONFIG0_TYPE__MASK 0x00000007
+#define TEXDESC_CONFIG0_TYPE__SHIFT 0
+#define TEXDESC_CONFIG0_TYPE(x) (((x) << TEXDESC_CONFIG0_TYPE__SHIFT) & TEXDESC_CONFIG0_TYPE__MASK)
+#define TEXDESC_CONFIG0_UWRAP__MASK 0x00000018
+#define TEXDESC_CONFIG0_UWRAP__SHIFT 3
+#define TEXDESC_CONFIG0_UWRAP(x) (((x) << TEXDESC_CONFIG0_UWRAP__SHIFT) & TEXDESC_CONFIG0_UWRAP__MASK)
+#define TEXDESC_CONFIG0_VWRAP__MASK 0x00000060
+#define TEXDESC_CONFIG0_VWRAP__SHIFT 5
+#define TEXDESC_CONFIG0_VWRAP(x) (((x) << TEXDESC_CONFIG0_VWRAP__SHIFT) & TEXDESC_CONFIG0_VWRAP__MASK)
+#define TEXDESC_CONFIG0_MIN__MASK 0x00000180
+#define TEXDESC_CONFIG0_MIN__SHIFT 7
+#define TEXDESC_CONFIG0_MIN(x) (((x) << TEXDESC_CONFIG0_MIN__SHIFT) & TEXDESC_CONFIG0_MIN__MASK)
+#define TEXDESC_CONFIG0_MIP__MASK 0x00000600
+#define TEXDESC_CONFIG0_MIP__SHIFT 9
+#define TEXDESC_CONFIG0_MIP(x) (((x) << TEXDESC_CONFIG0_MIP__SHIFT) & TEXDESC_CONFIG0_MIP__MASK)
+#define TEXDESC_CONFIG0_MAG__MASK 0x00001800
+#define TEXDESC_CONFIG0_MAG__SHIFT 11
+#define TEXDESC_CONFIG0_MAG(x) (((x) << TEXDESC_CONFIG0_MAG__SHIFT) & TEXDESC_CONFIG0_MAG__MASK)
+#define TEXDESC_CONFIG0_FORMAT__MASK 0x0003e000
+#define TEXDESC_CONFIG0_FORMAT__SHIFT 13
+#define TEXDESC_CONFIG0_FORMAT(x) (((x) << TEXDESC_CONFIG0_FORMAT__SHIFT) & TEXDESC_CONFIG0_FORMAT__MASK)
+#define TEXDESC_CONFIG0_ROUND_UV 0x00080000
+#define TEXDESC_CONFIG0_ENDIAN__MASK 0x00c00000
+#define TEXDESC_CONFIG0_ENDIAN__SHIFT 22
+#define TEXDESC_CONFIG0_ENDIAN(x) (((x) << TEXDESC_CONFIG0_ENDIAN__SHIFT) & TEXDESC_CONFIG0_ENDIAN__MASK)
+#define TEXDESC_CONFIG0_ANISOTROPY__MASK 0xff000000
+#define TEXDESC_CONFIG0_ANISOTROPY__SHIFT 24
+#define TEXDESC_CONFIG0_ANISOTROPY(x) (((x) << TEXDESC_CONFIG0_ANISOTROPY__SHIFT) & TEXDESC_CONFIG0_ANISOTROPY__MASK)
+
+#define TEXDESC_SIZE 0x00000044
+#define TEXDESC_SIZE_WIDTH__MASK 0x0000ffff
+#define TEXDESC_SIZE_WIDTH__SHIFT 0
+#define TEXDESC_SIZE_WIDTH(x) (((x) << TEXDESC_SIZE_WIDTH__SHIFT) & TEXDESC_SIZE_WIDTH__MASK)
+#define TEXDESC_SIZE_HEIGHT__MASK 0xffff0000
+#define TEXDESC_SIZE_HEIGHT__SHIFT 16
+#define TEXDESC_SIZE_HEIGHT(x) (((x) << TEXDESC_SIZE_HEIGHT__SHIFT) & TEXDESC_SIZE_HEIGHT__MASK)
+
+#define TEXDESC_LINEAR_STRIDE 0x00000048
+
+#define TEXDESC_CONFIG1 0x0000004c
+#define TEXDESC_CONFIG1_FORMAT_EXT__MASK 0x0000003f
+#define TEXDESC_CONFIG1_FORMAT_EXT__SHIFT 0
+#define TEXDESC_CONFIG1_FORMAT_EXT(x) (((x) << TEXDESC_CONFIG1_FORMAT_EXT__SHIFT) & TEXDESC_CONFIG1_FORMAT_EXT__MASK)
+#define TEXDESC_CONFIG1_SWIZZLE_R__MASK 0x00000700
+#define TEXDESC_CONFIG1_SWIZZLE_R__SHIFT 8
+#define TEXDESC_CONFIG1_SWIZZLE_R(x) (((x) << TEXDESC_CONFIG1_SWIZZLE_R__SHIFT) & TEXDESC_CONFIG1_SWIZZLE_R__MASK)
+#define TEXDESC_CONFIG1_SWIZZLE_G__MASK 0x00007000
+#define TEXDESC_CONFIG1_SWIZZLE_G__SHIFT 12
+#define TEXDESC_CONFIG1_SWIZZLE_G(x) (((x) << TEXDESC_CONFIG1_SWIZZLE_G__SHIFT) & TEXDESC_CONFIG1_SWIZZLE_G__MASK)
+#define TEXDESC_CONFIG1_SWIZZLE_B__MASK 0x00070000
+#define TEXDESC_CONFIG1_SWIZZLE_B__SHIFT 16
+#define TEXDESC_CONFIG1_SWIZZLE_B(x) (((x) << TEXDESC_CONFIG1_SWIZZLE_B__SHIFT) & TEXDESC_CONFIG1_SWIZZLE_B__MASK)
+#define TEXDESC_CONFIG1_SWIZZLE_A__MASK 0x00700000
+#define TEXDESC_CONFIG1_SWIZZLE_A__SHIFT 20
+#define TEXDESC_CONFIG1_SWIZZLE_A(x) (((x) << TEXDESC_CONFIG1_SWIZZLE_A__SHIFT) & TEXDESC_CONFIG1_SWIZZLE_A__MASK)
+#define TEXDESC_CONFIG1_CACHE_MODE__MASK 0x00800000
+#define TEXDESC_CONFIG1_CACHE_MODE__SHIFT 23
+#define TEXDESC_CONFIG1_CACHE_MODE_128 0x00000000
+#define TEXDESC_CONFIG1_CACHE_MODE_256 0x00800000
+#define TEXDESC_CONFIG1_TEXTURE_ARRAY 0x01000000
+#define TEXDESC_CONFIG1_UNK25 0x02000000
+#define TEXDESC_CONFIG1_HALIGN__MASK 0x1c000000
+#define TEXDESC_CONFIG1_HALIGN__SHIFT 26
+#define TEXDESC_CONFIG1_HALIGN(x) (((x) << TEXDESC_CONFIG1_HALIGN__SHIFT) & TEXDESC_CONFIG1_HALIGN__MASK)
+
+#define TEXDESC_CONTROL_YUV 0x00000050
+
+#define TEXDESC_STRIDE_YUV 0x00000054
+
+#define TEXDESC_ASTC0 0x00000058
+
+#define TEXDESC_ASTC1 0x0000005c
+
+#define TEXDESC_ASTC2 0x00000060
+
+#define TEXDESC_ASTC3 0x00000064
+
+#define TEXDESC_BASELOD 0x00000068
+#define TEXDESC_BASELOD_UNK23 0x00800000
+#define TEXDESC_BASELOD_BASELOD__MASK 0x0000000f
+#define TEXDESC_BASELOD_BASELOD__SHIFT 0
+#define TEXDESC_BASELOD_BASELOD(x) (((x) << TEXDESC_BASELOD_BASELOD__SHIFT) & TEXDESC_BASELOD_BASELOD__MASK)
+#define TEXDESC_BASELOD_MAXLOD__MASK 0x00000f00
+#define TEXDESC_BASELOD_MAXLOD__SHIFT 8
+#define TEXDESC_BASELOD_MAXLOD(x) (((x) << TEXDESC_BASELOD_MAXLOD__SHIFT) & TEXDESC_BASELOD_MAXLOD__MASK)
+
+#define TEXDESC_CONFIG2 0x0000006c
+
+#define TEXDESC_CONFIG3 0x00000070
+
+#define TEXDESC_LOG_SIZE_EXT 0x00000074
+#define TEXDESC_LOG_SIZE_EXT_WIDTH__MASK 0x0000ffff
+#define TEXDESC_LOG_SIZE_EXT_WIDTH__SHIFT 0
+#define TEXDESC_LOG_SIZE_EXT_WIDTH(x) (((x) << TEXDESC_LOG_SIZE_EXT_WIDTH__SHIFT) & TEXDESC_LOG_SIZE_EXT_WIDTH__MASK)
+#define TEXDESC_LOG_SIZE_EXT_HEIGHT__MASK 0xffff0000
+#define TEXDESC_LOG_SIZE_EXT_HEIGHT__SHIFT 16
+#define TEXDESC_LOG_SIZE_EXT_HEIGHT(x) (((x) << TEXDESC_LOG_SIZE_EXT_HEIGHT__SHIFT) & TEXDESC_LOG_SIZE_EXT_HEIGHT__MASK)
+
+#define TEXDESC_VOLUME 0x00000078
+
+#define TEXDESC_SLICE 0x0000007c
+
+#define TEXDESC_BORDER_COLOR 0x00000080
+
+#define TEXDESC_3D_CONFIG 0x00000084
+#define TEXDESC_3D_CONFIG_DEPTH__MASK 0x00003fff
+#define TEXDESC_3D_CONFIG_DEPTH__SHIFT 0
+#define TEXDESC_3D_CONFIG_DEPTH(x) (((x) << TEXDESC_3D_CONFIG_DEPTH__SHIFT) & TEXDESC_3D_CONFIG_DEPTH__MASK)
+#define TEXDESC_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000
+#define TEXDESC_3D_CONFIG_LOG_DEPTH__SHIFT 16
+#define TEXDESC_3D_CONFIG_LOG_DEPTH(x) (((x) << TEXDESC_3D_CONFIG_LOG_DEPTH__SHIFT) & TEXDESC_3D_CONFIG_LOG_DEPTH__MASK)
+#define TEXDESC_3D_CONFIG_WRAP__MASK 0x30000000
+#define TEXDESC_3D_CONFIG_WRAP__SHIFT 28
+#define TEXDESC_3D_CONFIG_WRAP(x) (((x) << TEXDESC_3D_CONFIG_WRAP__SHIFT) & TEXDESC_3D_CONFIG_WRAP__MASK)
+
+#define TEXDESC_LOG_SIZE 0x00000088
+#define TEXDESC_LOG_SIZE_WIDTH__MASK 0x000003ff
+#define TEXDESC_LOG_SIZE_WIDTH__SHIFT 0
+#define TEXDESC_LOG_SIZE_WIDTH(x) (((x) << TEXDESC_LOG_SIZE_WIDTH__SHIFT) & TEXDESC_LOG_SIZE_WIDTH__MASK)
+#define TEXDESC_LOG_SIZE_HEIGHT__MASK 0x000ffc00
+#define TEXDESC_LOG_SIZE_HEIGHT__SHIFT 10
+#define TEXDESC_LOG_SIZE_HEIGHT(x) (((x) << TEXDESC_LOG_SIZE_HEIGHT__SHIFT) & TEXDESC_LOG_SIZE_HEIGHT__MASK)
+#define TEXDESC_LOG_SIZE_RGB 0x20000000
+#define TEXDESC_LOG_SIZE_SRGB 0x80000000
+
+#define TEXDESC_BORDER_COLOR_R 0x0000008c
+
+#define TEXDESC_BORDER_COLOR_G 0x00000090
+
+#define TEXDESC_BORDER_COLOR_B 0x00000094
+
+#define TEXDESC_BORDER_COLOR_A 0x00000098
+
+
+#endif /* TEXDESC_3D_XML */
diff --git a/src/triangle_gc3000.c b/src/triangle_gc3000.c
index 25444e6..d3a6fc6 100644
--- a/src/triangle_gc3000.c
+++ b/src/triangle_gc3000.c
@@ -155,7 +155,7 @@
etna_set_state_reloc(stream, VIVS_TS_COLOR_STATUS_BASE, &at->color_status_base);
etna_set_state_reloc(stream, VIVS_TS_COLOR_SURFACE_BASE, &at->color_surface_base);
etna_set_state(stream, VIVS_TS_COLOR_CLEAR_VALUE, 0xff808080);
- etna_set_state(stream, VIVS_RS_UNK016BC, 0xff808080);
+ etna_set_state(stream, VIVS_TS_COLOR_CLEAR_VALUE_EXT, 0xff808080);
etna_set_state(stream, VIVS_TS_MEM_CONFIG, 0x00000022);
etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000001);
etna_set_state(stream, VIVS_DUMMY_DUMMY, 0x00000000);
@@ -172,8 +172,8 @@
etna_set_state_reloc(stream, VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(0), &at->stream_base);
etna_set_state(stream, VIVS_NFE_VERTEX_STREAMS_CONTROL(0), 0x00000020);
etna_set_state(stream, VIVS_NFE_VERTEX_STREAMS_UNK14680(0), 0x00000000);
- etna_set_state(stream, VIVS_FE_UNK00780(0), 0x3f800000);
- etna_set_state(stream, VIVS_FE_UNK00780(1), 0x3f800000);
+ etna_set_state(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0), 0x3f800000);
+ etna_set_state(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(1), 0x3f800000);
// How to emit 0 address?
//etna_set_state_reloc(stream, VIVS_FE_INDEX_STREAM_BASE_ADDR, 0x00000000);
etna_set_state(stream, VIVS_FE_INDEX_STREAM_CONTROL, 0x00000000);
@@ -305,10 +305,10 @@
etna_set_state_reloc(stream, VIVS_TS_COLOR_STATUS_BASE, &at->color_status_base);
etna_set_state_reloc(stream, VIVS_TS_COLOR_SURFACE_BASE, &at->color_surface_base);
etna_set_state(stream, VIVS_TS_COLOR_CLEAR_VALUE, 0xff808080);
- etna_set_state(stream, VIVS_RS_UNK016BC, 0xff808080);
+ etna_set_state(stream, VIVS_TS_COLOR_CLEAR_VALUE_EXT, 0xff808080);
etna_set_state(stream, VIVS_RS_EXTRA_CONFIG, 0x10000000);
etna_set_state(stream, VIVS_RS_SOURCE_STRIDE, 0x80005000);
- etna_set_state(stream, VIVS_RS_UNK016B0, 0x00010400);
+ etna_set_state(stream, VIVS_RS_KICKER_INPLACE, 0x00010400);
etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000002);
etna_set_state(stream, VIVS_DUMMY_DUMMY, 0x00000000);
etna_set_state(stream, VIVS_TS_MEM_CONFIG, 0x00000041);
