commit 8bcddbcce2fa9eaa2e2e1ee2bb469189f76b7cbd
author Sami Mujawar <sami.mujawar@arm.com> Thu May 18 11:00:54 2023 +0100
committer mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Thu Jun 01 15:52:01 2023 +0000
tree 7bc95f4654972028547f67f7eaf70152391e3a98
parent 8da2b97392f245f3e3f6bb5b1b0d05c670b82bca

ArmPkg: Adjust variable type and cast for RegShift & RegOffset

According to the GIC architecture version 3 and 4 specification, the
maximum number of INTID bits supported in the CPU interface is 24.

Considering this the RegShift variable is not required to be more than 8
bits. Therefore, make the RegShift variable type to UINT8.  Also add
necessary typecasts when calculating the RegOffset and RegShift values.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

ArmPkg/Drivers/ArmGic/ArmGicLib.c

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 0127cca..8f3315d 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -228,13 +228,13 @@
   )

 {

   UINT32                 RegOffset;

-  UINTN                  RegShift;

+  UINT8                  RegShift;

   ARM_GIC_ARCH_REVISION  Revision;

   UINTN                  GicCpuRedistributorBase;

 

   // Calculate register offset and bit position

-  RegOffset = Source / 4;

-  RegShift  = (Source % 4) * 8;

+  RegOffset = (UINT32)(Source / 4);

+  RegShift  = (UINT8)((Source % 4) * 8);

 

   Revision = ArmGicGetSupportedArchRevision ();

   if ((Revision == ARM_GIC_ARCH_REVISION_2) ||

@@ -272,13 +272,13 @@
   )

 {

   UINT32                 RegOffset;

-  UINTN                  RegShift;

+  UINT8                  RegShift;

   ARM_GIC_ARCH_REVISION  Revision;

   UINTN                  GicCpuRedistributorBase;

 

   // Calculate enable register offset and bit position

-  RegOffset = Source / 32;

-  RegShift  = Source % 32;

+  RegOffset = (UINT32)(Source / 32);

+  RegShift  = (UINT8)(Source % 32);

 

   Revision = ArmGicGetSupportedArchRevision ();

   if ((Revision == ARM_GIC_ARCH_REVISION_2) ||

@@ -317,13 +317,13 @@
   )

 {

   UINT32                 RegOffset;

-  UINTN                  RegShift;

+  UINT8                  RegShift;

   ARM_GIC_ARCH_REVISION  Revision;

   UINTN                  GicCpuRedistributorBase;

 

   // Calculate enable register offset and bit position

-  RegOffset = Source / 32;

-  RegShift  = Source % 32;

+  RegOffset = (UINT32)(Source / 32);

+  RegShift  = (UINT8)(Source % 32);

 

   Revision = ArmGicGetSupportedArchRevision ();

   if ((Revision == ARM_GIC_ARCH_REVISION_2) ||

@@ -361,14 +361,14 @@
   )

 {

   UINT32                 RegOffset;

-  UINTN                  RegShift;

+  UINT8                  RegShift;

   ARM_GIC_ARCH_REVISION  Revision;

   UINTN                  GicCpuRedistributorBase;

   UINT32                 Interrupts;

 

   // Calculate enable register offset and bit position

-  RegOffset = Source / 32;

-  RegShift  = Source % 32;

+  RegOffset = (UINT32)(Source / 32);

+  RegShift  = (UINT8)(Source % 32);

 

   Revision = ArmGicGetSupportedArchRevision ();

   if ((Revision == ARM_GIC_ARCH_REVISION_2) ||

ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c

diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
index a7970e5..cd65cf0 100644
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
@@ -393,7 +393,7 @@
   EFI_STATUS  Status;

   UINTN       Index;

   UINT32      RegOffset;

-  UINTN       RegShift;

+  UINT8       RegShift;

   UINT32      CpuTarget;

 

   // Make sure the Interrupt Controller Protocol is not already installed in

@@ -411,8 +411,8 @@
     GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);

 

     // Set Priority

-    RegOffset = Index / 4;

-    RegShift  = (Index % 4) * 8;

+    RegOffset = (UINT32)(Index / 4);

+    RegShift  = (UINT8)((Index % 4) * 8);

     MmioAndThenOr32 (

       mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),

       ~(0xff << RegShift),