commit 31e97bdae2c66e28c5c7df1340757304e1b76d41
author Cosmo Lai <cosmo.lai@intel.com> Thu Oct 22 10:51:27 2020 +0800
committer mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Tue Oct 27 06:06:03 2020 +0000
tree a3948d998f9422623764c57b69828c6a2c8f7622
parent a3212009d95bbcba7d08076aba2eee51eb1f8e7c

IntelFsp2Pkg/FspSecCore: LoadMicrocodeDefault() failed with padding in FV.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3017

Platform microcode FV may have padding between each version of microcode
binary, and current FSP-T/LoadMicrocodeDefault() cannot handle this case
and return not_found unexpectedly.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Cosmo Lai <cosmo.lai@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7934eab..7fd3d6d 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -307,10 +307,6 @@
    add   esi, dword  1024

 

 CheckAddress:

-   ; Is valid Microcode start point ?

-   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh

-   jz    Done

-

    ; Check UPD header revision

    cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2

    jae    Fsp22UpdHeader1

@@ -341,6 +337,10 @@
    jmp   CheckMainHeader

 

 LoadMicrocodeDefault4:

+   ; Is valid Microcode start point ?

+   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh

+   jz    Done

+

 LoadCheck:

    ; Get the revision of the current microcode update loaded

    mov   ecx, MSR_IA32_BIOS_SIGN_ID