veyron: add new board emile
This is a copy of mickey and renamed.
Emile used usb-hosts while mickey not, add it respectively.
CQ-DEPEND=CL:306967
BUG=chrome-os-partner:46658
TEST=build and boot on emile
BRANCH=veyron
Change-Id: I52495a8f28e286648716f8356360406984c70a23
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/307017
Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
diff --git a/board/veyron_emile/defconfig b/board/veyron_emile/defconfig
new file mode 100644
index 0000000..a0568c8
--- /dev/null
+++ b/board/veyron_emile/defconfig
@@ -0,0 +1,39 @@
+# Arch
+CONFIG_ARCH_ARM=y
+
+# Board
+CONFIG_BOARD="veyron_emile"
+
+# Image
+CONFIG_BASE_ADDRESS=0x43000000
+CONFIG_FMAP_OFFSET=0x00100000
+CONFIG_HEAP_SIZE=0x01000000
+CONFIG_KERNEL_START=0x2000000
+
+# Vboot
+CONFIG_VIRTUAL_DEV_SWITCH=y
+
+CONFIG_CROSSYSTEM_FDT=y
+CONFIG_NV_STORAGE_FLASH=y
+
+
+#CONFIG_MOCK_TPM=y
+
+# Kernel format
+CONFIG_KERNEL_FIT=y
+CONFIG_KERNEL_FIT_FDT_ADDR=0x6400000
+
+# Drivers
+CONFIG_DRIVER_GPIO_ROCKCHIP=y
+CONFIG_DRIVER_BUS_I2C_ROCKCHIP=y
+CONFIG_DRIVER_BUS_SPI_ROCKCHIP=y
+CONFIG_DRIVER_BUS_I2S_ROCKCHIP=y
+CONFIG_DRIVER_FLASH_SPI=y
+CONFIG_DRIVER_POWER_RK808=y
+CONFIG_DRIVER_INPUT_USB=y
+CONFIG_DRIVER_SOUND_I2S=y
+CONFIG_DRIVER_SOUND_ROUTE=y
+CONFIG_DRIVER_STORAGE_MMC=y
+CONFIG_DRIVER_STORAGE_MMC_ROCKCHIP=y
+CONFIG_DRIVER_TPM_SLB9635_I2C=y
+CONFIG_DRIVER_VIDEO_ROCKCHIP=y
diff --git a/board/veyron_emile/fmap.dts b/board/veyron_emile/fmap.dts
new file mode 100644
index 0000000..a99e92a
--- /dev/null
+++ b/board/veyron_emile/fmap.dts
@@ -0,0 +1,209 @@
+/dts-v1/;
+
+/ {
+ model = "Google Veyron_Emile";
+ config {
+ hwid = "EMILE TEST A-A 0992";
+ };
+ chromeos-config {
+ /* Enable factory-friendly features. */
+ gbb-flag-dev-screen-short-delay;
+ gbb-flag-force-dev-switch-on;
+ gbb-flag-force-dev-boot-usb;
+ gbb-flag-disable-fw-rollback-check;
+ };
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "chromeos,flashmap";
+ reg = <0x00000000 0x00400000>;
+
+ /* ---- Section: Read-only ---- */
+ wp-ro {
+ label = "wp-ro";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+
+ ro-section {
+ label = "ro-section";
+ reg = <0x00000000 0x001f0000>;
+ read-only;
+ };
+ ro-boot {
+ label = "coreboot";
+ size = <0x00100000>;
+ read-only;
+ type = "blob coreboot";
+ required;
+ };
+
+ ro-fmap {
+ label = "fmap";
+
+ /* We encourage to align FMAP partition in as large
+ * block as possible so that flashrom can find it soon.
+ * For example, aligning to 512KB is better than to
+ * 256KB. */
+
+ reg = <0x00100000 0x00001000>;
+ read-only;
+ type = "fmap";
+ ver-major = <1>;
+ ver-minor = <0>;
+ };
+
+ ro-gbb {
+ label = "gbb";
+
+ /* GBB offset must be aligned to 4K bytes */
+ reg = <0x00101000 0x000eef00>;
+ read-only;
+ type = "blob gbb";
+ };
+
+ ro-firmware-id {
+ label = "ro-frid";
+ reg = <0x001eff00 0x00000100>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /* ---- Section: Vital-product data (VPD) ---- */
+ ro-vpd {
+ label = "ro-vpd";
+
+ /* VPD offset must be aligned to 4K bytes */
+ reg = <0x001f0000 0x00010000>;
+ read-only;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /* ---- Section: Rewritable slot A ---- */
+ rw-a {
+ label = "rw-section-a";
+ /* Alignment: 4k (for updating) */
+ reg = <0x00200000 0x00078000>;
+ };
+ rw-a-vblock {
+ label = "vblock-a";
+ /*
+ * Alignment: 4k (for updating) and must be in start of
+ * each RW_SECTION.
+ */
+ reg = <0x00200000 0x00002000>;
+ type = "keyblock boot,romstage,ramstage";
+ with_index;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <0>;
+ };
+ rw-a-boot {
+ /* Alignment: no requirement (yet). */
+ label = "fw-main-a";
+ reg = <0x00202000 0x00075f00>;
+ type = "blob boot,romstage,ramstage";
+ with_index;
+ };
+ rw-a-firmware-id {
+ /* Alignment: no requirement. */
+ label = "rw-fwid-a";
+ reg = <0x00277f00 0x00000100>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /* ---- Section: Rewritable shared 8 KB ---- */
+ shared-section {
+ /*
+ * Alignment: 4k (for updating).
+ * Anything in this range may be updated in recovery.
+ */
+ label = "rw-shared";
+ reg = <0x00278000 0x00002000>;
+ };
+ shared-data {
+ label = "shared-data";
+ /*
+ * Alignment: 4k (for random read/write).
+ * RW firmware can put calibration data here.
+ */
+ reg = <0x00278000 0x00002000>;
+ type = "wiped";
+ wipe-value = [00];
+ };
+
+ /* ---- Section: Storage to simulate NVRAM 8 KB ---- */
+ rw-nvram {
+ label = "rw-nvram";
+ reg = <0x0027a000 0x00002000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+
+ /* ---- Section: Rewritable Event Log 16 KB ---- */
+ rw-elog {
+ label = "rw-elog";
+ /* Alignment: 4K (for updating) */
+ reg = <0x0027c000 0x00004000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ /* ---- Section: Rewritable slot B ---- */
+ rw-b {
+ label = "rw-section-b";
+ /* Alignment: 4k (for updating) */
+ reg = <0x00280000 0x00078000>;
+ };
+ rw-b-vblock {
+ label = "vblock-b";
+ /*
+ * Alignment: 4k (for updating) and must be in start of
+ * each RW_SECTION.
+ */
+ reg = <0x00280000 0x00002000>;
+ type = "keyblock boot,romstage,ramstage";
+ with_index;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <0>;
+ };
+ rw-b-boot {
+ label = "fw-main-b";
+ /* Alignment: no requirement (yet). */
+ reg = <0x00282000 0x00075f00>;
+ type = "blob boot,romstage,ramstage";
+ with_index;
+ };
+ rw-b-firmware-id {
+ label = "rw-fwid-b";
+ /* Alignment: no requirement. */
+ reg = <0x002f7f00 0x00000100>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /* ---- Section: Rewritable VPD 32 KB ---- */
+ rw-vpd {
+ label = "rw-vpd";
+ /* Alignment: 4k (for updating) */
+ reg = <0x002f8000 0x00008000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ rw-legacy {
+ label = "rw-legacy";
+ reg = <0x00300000 0x00100000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+ };
+};
diff --git a/src/board/veyron_emile/Kconfig b/src/board/veyron_emile/Kconfig
new file mode 100644
index 0000000..a34c328
--- /dev/null
+++ b/src/board/veyron_emile/Kconfig
@@ -0,0 +1,17 @@
+
+##
+## Copyright 2014 Rockchip Electronics. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
diff --git a/src/board/veyron_emile/Makefile.inc b/src/board/veyron_emile/Makefile.inc
new file mode 100644
index 0000000..dd36ecc
--- /dev/null
+++ b/src/board/veyron_emile/Makefile.inc
@@ -0,0 +1,19 @@
+##
+##
+## Copyright 2014 Rockchip Electronics Co., Ltd.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+depthcharge-y += board.c
diff --git a/src/board/veyron_emile/board.c b/src/board/veyron_emile/board.c
new file mode 100644
index 0000000..c7d2965
--- /dev/null
+++ b/src/board/veyron_emile/board.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2014 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <arch/io.h>
+
+#include "base/init_funcs.h"
+#include "boot/fit.h"
+#include "boot/ramoops.h"
+#include "drivers/bus/i2c/rockchip.h"
+#include "drivers/bus/i2s/rockchip.h"
+#include "drivers/bus/spi/rockchip.h"
+#include "drivers/bus/usb/usb.h"
+#include "drivers/flash/spi.h"
+#include "drivers/gpio/rockchip.h"
+#include "drivers/gpio/sysinfo.h"
+#include "drivers/power/rk808.h"
+#include "drivers/power/sysinfo.h"
+#include "drivers/sound/i2s.h"
+#include "drivers/sound/route.h"
+#include "drivers/storage/dw_mmc.h"
+#include "drivers/storage/rk_mmc.h"
+#include "drivers/tpm/slb9635_i2c.h"
+#include "drivers/tpm/tpm.h"
+#include "drivers/video/display.h"
+#include "drivers/video/rockchip.h"
+#include "vboot/util/flag.h"
+
+static int board_setup(void)
+{
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
+ flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
+
+ sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
+
+ RkI2c *i2c1 = new_rockchip_i2c((void *)0xff140000);
+ tpm_set_ops(&new_slb9635_i2c(&i2c1->ops, 0x20)->base.ops);
+
+ RockchipI2s *i2s0 = new_rockchip_i2s(0xff890000, 16, 2, 256);
+ I2sSource *i2s_source = new_i2s_source(&i2s0->ops, 48000, 2, 16000);
+ SoundRoute *sound_route = new_sound_route(&i2s_source->ops);
+ sound_set_ops(&sound_route->ops);
+
+ RkI2c *i2c0 = new_rockchip_i2c((void *)0xff650000);
+ Rk808Pmic *pmic = new_rk808_pmic(&i2c0->ops, 0x1b);
+ SysinfoResetPowerOps *power = new_sysinfo_reset_power_ops(&pmic->ops,
+ new_rk_gpio_output_from_coreboot);
+ power_set_ops(&power->ops);
+
+ DwmciHost *emmc = new_rkdwmci_host(0xff0f0000, 594000000, 8, 0, NULL);
+ list_insert_after(&emmc->mmc.ctrlr.list_node,
+ &fixed_block_dev_controllers);
+
+ // This is actually an OTG port and is labeled as such in the schematic,
+ // though in reality we use it as a regular host mode port and leave
+ // the OTG_ID pin disconnected.
+ UsbHostController *usb_otg = new_usb_hc(DWC2, 0xff580000);
+ list_insert_after(&usb_otg->list_node, &usb_host_controllers);
+
+ UsbHostController *usb_host1 = new_usb_hc(DWC2, 0xff540000);
+ list_insert_after(&usb_host1->list_node, &usb_host_controllers);
+
+ // Claim that we have an open lid to satisfy vboot.
+ flag_replace(FLAG_LIDSW, new_gpio_high());
+
+ // Claim that we have an power key to satisfy vboot.
+ flag_replace(FLAG_PWRSW, new_gpio_low());
+
+ // Read the current value of the recovery button for confirmation
+ // when transitioning between normal and dev mode.
+ flag_replace(FLAG_RECSW, sysinfo_lookup_gpio("recovery",
+ 1, new_rk_gpio_input_from_coreboot));
+
+ ramoops_buffer(0x31f00000, 0x100000, 0x20000);
+
+ if (lib_sysinfo.framebuffer != NULL)
+ display_set_ops(NULL);
+
+ return 0;
+}
+
+INIT_FUNC(board_setup);
