rockchip: Remove unnecessary settings from spi_start()
The Rockchip SPI driver currently reinitializes CTRLR0, even though it
should have already been set up by coreboot. This is unnecessary and
dangerous because settings might go out of sync. spi_start() is also
invoked on every transfer (not just once), and writing this register
over and over again is excessive.
This patch removes those lines so that spi_start() will only perform the
one purpose it's supposed to, asserting CS. It also removes the
appropriate arguments from new_rockchip_spi() which concern parameters
that should've already been configured by coreboot. This even includes
the CS parameter, since the code currently doesn't even use it right...
(it ignores it and always writes a '1' to the SER register). We can add
it back in if we ever want to fix this, but for now it's better to leave
it out than to have it non-functional.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted Jerry.
Change-Id: I4cee7f81f6bff8339c33a36ade4e3c6d667f9b50
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/262311
Reviewed-by: David Hendricks <dhendrix@chromium.org>
diff --git a/src/board/veyron_brain/board.c b/src/board/veyron_brain/board.c
index 52de374..8e7c74c 100644
--- a/src/board/veyron_brain/board.c
+++ b/src/board/veyron_brain/board.c
@@ -47,7 +47,7 @@
fit_set_compat_by_rev("google,veyron-brain-rev%d",
lib_sysinfo.board_id);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/board/veyron_danger/board.c b/src/board/veyron_danger/board.c
index ee2cd41..f2a8b19 100644
--- a/src/board/veyron_danger/board.c
+++ b/src/board/veyron_danger/board.c
@@ -47,7 +47,7 @@
fit_set_compat_by_rev("google,veyron-danger-rev%d",
lib_sysinfo.board_id);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/board/veyron_jerry/board.c b/src/board/veyron_jerry/board.c
index b7feacf..adda29e 100644
--- a/src/board/veyron_jerry/board.c
+++ b/src/board/veyron_jerry/board.c
@@ -48,10 +48,10 @@
fit_set_compat_by_rev("google,veyron-jerry-rev%d",
lib_sysinfo.board_id);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
- RkSpi *spi0 = new_rockchip_spi(0xff110000, 0, 0, 0);
+ RkSpi *spi0 = new_rockchip_spi(0xff110000);
cros_ec_set_bus(&new_cros_ec_spi_bus(&spi0->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/board/veyron_mighty/board.c b/src/board/veyron_mighty/board.c
index bcbab4d..a0c35f8 100644
--- a/src/board/veyron_mighty/board.c
+++ b/src/board/veyron_mighty/board.c
@@ -48,10 +48,10 @@
fit_set_compat_by_rev("google,veyron-mighty-rev%d",
lib_sysinfo.board_id);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
- RkSpi *spi0 = new_rockchip_spi(0xff110000, 0, 0, 0);
+ RkSpi *spi0 = new_rockchip_spi(0xff110000);
cros_ec_set_bus(&new_cros_ec_spi_bus(&spi0->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/board/veyron_pinky/board.c b/src/board/veyron_pinky/board.c
index eb9f872..7735853 100644
--- a/src/board/veyron_pinky/board.c
+++ b/src/board/veyron_pinky/board.c
@@ -49,10 +49,10 @@
fit_set_compat_by_rev("google,veyron-pinky-rev%d",
lib_sysinfo.board_id + 1);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
- RkSpi *spi0 = new_rockchip_spi(0xff110000, 0, 0, 0);
+ RkSpi *spi0 = new_rockchip_spi(0xff110000);
cros_ec_set_bus(&new_cros_ec_spi_bus(&spi0->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/board/veyron_rialto/board.c b/src/board/veyron_rialto/board.c
index 011d118..04d01ac 100644
--- a/src/board/veyron_rialto/board.c
+++ b/src/board/veyron_rialto/board.c
@@ -59,7 +59,7 @@
fit_set_compat_by_rev("google,veyron-rialto-rev%d",
lib_sysinfo.board_id);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/board/veyron_speedy/board.c b/src/board/veyron_speedy/board.c
index a52b822..38ff088 100644
--- a/src/board/veyron_speedy/board.c
+++ b/src/board/veyron_speedy/board.c
@@ -48,10 +48,10 @@
fit_set_compat_by_rev("google,veyron-speedy-rev%d",
lib_sysinfo.board_id);
- RkSpi *spi2 = new_rockchip_spi(0xff130000, 0, 0, 0);
+ RkSpi *spi2 = new_rockchip_spi(0xff130000);
flash_set_ops(&new_spi_flash(&spi2->ops)->ops);
- RkSpi *spi0 = new_rockchip_spi(0xff110000, 0, 0, 0);
+ RkSpi *spi0 = new_rockchip_spi(0xff110000);
cros_ec_set_bus(&new_cros_ec_spi_bus(&spi0->ops)->ops);
sysinfo_install_flags(new_rk_gpio_input_from_coreboot);
diff --git a/src/drivers/bus/spi/rockchip.c b/src/drivers/bus/spi/rockchip.c
index ec85824..1e0f22e 100644
--- a/src/drivers/bus/spi/rockchip.c
+++ b/src/drivers/bus/spi/rockchip.c
@@ -213,20 +213,10 @@
static int spi_start(SpiOps *me)
{
int res = 0;
- unsigned int cr0 = 0;
RkSpi *bus = container_of(me, RkSpi, ops);
RkSpiRegs *regs = bus->reg_addr;
spi_info("spi:: start\n");
- cr0 |= 1 << CR0_HALFWORD_TS_BIT;
- cr0 |= 1 << CR0_SSN_DELAY_BIT;
- cr0 |= (bus->polarity << CR0_CLOCK_POLARITY_BIT);
- cr0 |= (bus->phase << CR0_CLOCK_PHASE_BIT);
- cr0 |= FRAME_SIZE_8BIT << CR0_FRAME_SIZE_BIT;
- writel(cr0, ®s->ctrlr0);
-
- writel(FIFO_DEPTH / 2 - 1, ®s->txflr);
- writel(FIFO_DEPTH / 2 - 1, ®s->rxflr);
writel(1, ®s->ser);
return res;
}
@@ -242,18 +232,12 @@
return res;
}
-RkSpi *new_rockchip_spi(uintptr_t reg_addr, unsigned int polarity,
- unsigned int cs, unsigned int phase)
+RkSpi *new_rockchip_spi(uintptr_t reg_addr)
{
RkSpi *bus = NULL;
- die_if(cs >= MAX_SLAVE, "spi cs exceed max slave\n");
-
bus = xzalloc(sizeof(*bus));
bus->reg_addr = (void *)reg_addr;
- bus->cs = cs;
- bus->polarity = polarity;
- bus->phase = phase;
bus->ops.start = &spi_start;
bus->ops.stop = &spi_stop;
bus->ops.transfer = &spi_transfer;
diff --git a/src/drivers/bus/spi/rockchip.h b/src/drivers/bus/spi/rockchip.h
index 708c856..cdff107 100644
--- a/src/drivers/bus/spi/rockchip.h
+++ b/src/drivers/bus/spi/rockchip.h
@@ -26,14 +26,9 @@
typedef struct RkSpi {
SpiOps ops;
void *reg_addr;
- unsigned int cs;
- unsigned int div;
- unsigned int polarity;
- unsigned int phase;
} RkSpi;
-RkSpi *new_rockchip_spi(uintptr_t reg_addr, unsigned int polarity,
- unsigned int cs, unsigned int phase);
+RkSpi *new_rockchip_spi(uintptr_t reg_addr);
#endif /* __DRIVERS_BUS_SPI_RK3288_H__ */
