| /* |
| * Copyright 2011 Google Inc. |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but without any warranty; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| /* This file is derived from the flashrom project. */ |
| #ifndef __DRIVERS_FLASH_ICH_SHARED_H__ |
| #define __DRIVERS_FLASH_ICH_SHARED_H__ |
| |
| #include <stdint.h> |
| |
| #include "drivers/flash/ich.h" |
| |
| enum { |
| SPIS_SCIP = 0x0001, |
| SPIS_GRANT = 0x0002, |
| SPIS_CDS = 0x0004, |
| SPIS_FCERR = 0x0008, |
| SSFS_AEL = 0x0010, |
| SPIS_LOCK = 0x8000, |
| SPIS_RESERVED_MASK = 0x7ff0, |
| SSFS_RESERVED_MASK = 0x7fe2 |
| }; |
| |
| enum { |
| SPIC_SCGO = 0x000002, |
| SPIC_ACS = 0x000004, |
| SPIC_SPOP = 0x000008, |
| SPIC_DBC = 0x003f00, |
| SPIC_DS = 0x004000, |
| SPIC_SME = 0x008000, |
| SSFC_SCF_MASK = 0x070000, |
| SSFC_RESERVED = 0xf80000 |
| }; |
| |
| enum { |
| HSFS_FDONE = 0x0001, |
| HSFS_FCERR = 0x0002, |
| HSFS_AEL = 0x0004, |
| HSFS_BERASE_MASK = 0x0018, |
| HSFS_BERASE_SHIFT = 3, |
| HSFS_SCIP = 0x0020, |
| HSFS_FDOPSS = 0x2000, |
| HSFS_FDV = 0x4000, |
| HSFS_FLOCKDN = 0x8000 |
| }; |
| |
| enum { |
| HSFC_FGO = 0x0001, |
| HSFC_FCYCLE_MASK = 0x0006, |
| HSFC_FCYCLE_SHIFT = 1, |
| HSFC_FDBC_MASK = 0x3f00, |
| HSFC_FDBC_SHIFT = 8, |
| HSFC_FSMIE = 0x8000 |
| }; |
| |
| enum { |
| SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| }; |
| |
| // Root Complex Register Block |
| uint8_t *ich_spi_get_rcrb(void); |
| void *ich_spi_flash_read(FlashOps *me, uint32_t offset, uint32_t size); |
| |
| #endif /* __DRIVERS_FLASH_ICH_SHARED_H__ */ |