depthcharge: correct SD controller base clock frequency
Added clock_base which saves base clock frequency read out from
CAP register. So frequency divider can be calculated correctly.
This also fixes min and max SD clock settings for their intended
purpose.
BUG=chrome-os-partner:42065
BRANCH=None
TEST=Built and booted glados from SD card.
Change-Id: I81ceed89f59b4a79976d5da594b3780fb379b6cb
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290419
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c
index dc6a3fe..3f2a50c 100644
--- a/src/drivers/storage/sdhci.c
+++ b/src/drivers/storage/sdhci.c
@@ -399,18 +399,18 @@
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */
- if (host->mmc_ctrlr.f_max <= clock)
+ if (host->clock_base <= clock)
div = 1;
else {
for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
- if ((host->mmc_ctrlr.f_max / div) <= clock)
+ if ((host->clock_base / div) <= clock)
break;
}
}
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
- if ((host->mmc_ctrlr.f_max / div) <= clock)
+ if ((host->clock_base / div) <= clock)
break;
}
}
@@ -579,33 +579,34 @@
if (caps & SDHCI_CAN_DO_ADMA2)
host->host_caps |= MMC_AUTO_CMD12;
- if (host->clock_f_max) {
- host->mmc_ctrlr.f_max = host->clock_f_max;
- } else {
- if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
- host->mmc_ctrlr.f_max = (caps &
- SDHCI_CLOCK_V3_BASE_MASK)
- >> SDHCI_CLOCK_BASE_SHIFT;
- else
- host->mmc_ctrlr.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
- >> SDHCI_CLOCK_BASE_SHIFT;
+ /* get base clock frequency from CAP register */
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
+ host->clock_base = (caps & SDHCI_CLOCK_V3_BASE_MASK)
+ >> SDHCI_CLOCK_BASE_SHIFT;
+ else
+ host->clock_base = (caps & SDHCI_CLOCK_BASE_MASK)
+ >> SDHCI_CLOCK_BASE_SHIFT;
- if (host->mmc_ctrlr.f_max == 0) {
- printf("Hardware doesn't specify base clock frequency\n");
- return -1;
- }
- host->mmc_ctrlr.f_max *= 1000000;
+ if (host->clock_base == 0) {
+ printf("Hardware doesn't specify base clock frequency\n");
+ return -1;
}
+ host->clock_base *= 1000000;
+
+ if (host->clock_f_max)
+ host->mmc_ctrlr.f_max = host->clock_f_max;
+ else
+ host->mmc_ctrlr.f_max = host->clock_base;
if (host->clock_f_min) {
host->mmc_ctrlr.f_min = host->clock_f_min;
} else {
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
host->mmc_ctrlr.f_min =
- host->mmc_ctrlr.f_max / SDHCI_MAX_DIV_SPEC_300;
+ host->clock_base / SDHCI_MAX_DIV_SPEC_300;
else
host->mmc_ctrlr.f_min =
- host->mmc_ctrlr.f_max / SDHCI_MAX_DIV_SPEC_200;
+ host->clock_base / SDHCI_MAX_DIV_SPEC_200;
}
if (caps & SDHCI_CAN_VDD_330)
diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h
index 03c2451..e7e2007 100644
--- a/src/drivers/storage/sdhci.h
+++ b/src/drivers/storage/sdhci.h
@@ -296,6 +296,7 @@
unsigned clock; /* current, min and max interface clocks */
unsigned clock_f_min;
unsigned clock_f_max;
+ unsigned clock_base; /* controller base clock */
int removable;
unsigned voltages;
