src/drivers/blockdev/dw_mmc.h - third_party/depthcharge - Git at Google

 /*
  * (C) Copyright 2012 SAMSUNG Electronics
  * Jaehoon Chung <jh80.chung@samsung.com>
  * Copyright 2013 Google Inc.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,  MA 02111-1307 USA
  *
  */

 #ifndef __DRIVERS_BLOCKDEV_DW_MMC_H__
 #define __DRIVERS_BLOCKDEV_DW_MMC_H__

 #include "base/io.h"
 #include "drivers/gpio/gpio.h"
 #include "drivers/blockdev/blockdev.h"
 #include "drivers/blockdev/mmc.h"

 #define DWMCI_CTRL		0x000
 #define	DWMCI_PWREN		0x004
 #define DWMCI_CLKDIV		0x008
 #define DWMCI_CLKSRC		0x00C
 #define DWMCI_CLKENA		0x010
 #define DWMCI_TMOUT		0x014
 #define DWMCI_CTYPE		0x018
 #define DWMCI_BLKSIZ		0x01C
 #define DWMCI_BYTCNT		0x020
 #define DWMCI_INTMASK		0x024
 #define DWMCI_CMDARG		0x028
 #define DWMCI_CMD		0x02C
 #define DWMCI_RESP0		0x030
 #define DWMCI_RESP1		0x034
 #define DWMCI_RESP2		0x038
 #define DWMCI_RESP3		0x03C
 #define DWMCI_MINTSTS		0x040
 #define DWMCI_RINTSTS		0x044
 #define DWMCI_STATUS		0x048
 #define DWMCI_FIFOTH		0x04C
 #define DWMCI_CDETECT		0x050
 #define DWMCI_WRTPRT		0x054
 #define DWMCI_GPIO		0x058
 #define DWMCI_TCMCNT		0x05C
 #define DWMCI_TBBCNT		0x060
 #define DWMCI_DEBNCE		0x064
 #define DWMCI_USRID		0x068
 #define DWMCI_VERID		0x06C
 #define DWMCI_HCON		0x070
 #define DWMCI_UHS_REG		0x074
 #define DWMCI_BMOD		0x080
 #define DWMCI_PLDMND		0x084
 #define DWMCI_DBADDR		0x088
 #define DWMCI_IDSTS		0x08C
 #define DWMCI_IDINTEN		0x090
 #define DWMCI_DSCADDR		0x094
 #define DWMCI_BUFADDR		0x098
 #define DWMCI_CLKSEL		0x09C
 #define DWMCI_DATA		0x200
 #define EMMCP_MPSBEGIN0		0x1200
 #define EMMCP_SEND0		0x1204
 #define EMMCP_CTRL0		0x120C

 /* Interrupt Mask register */
 #define DWMCI_INTMSK_ALL	0xffffffff
 #define DWMCI_INTMSK_RE		(1 << 1)
 #define DWMCI_INTMSK_CDONE	(1 << 2)
 #define DWMCI_INTMSK_DTO	(1 << 3)
 #define DWMCI_INTMSK_TXDR	(1 << 4)
 #define DWMCI_INTMSK_RXDR	(1 << 5)
 #define DWMCI_INTMSK_DCRC	(1 << 7)
 #define DWMCI_INTMSK_RTO	(1 << 8)
 #define DWMCI_INTMSK_DRTO	(1 << 9)
 #define DWMCI_INTMSK_HTO	(1 << 10)
 #define DWMCI_INTMSK_FRUN	(1 << 11)
 #define DWMCI_INTMSK_HLE	(1 << 12)
 #define DWMCI_INTMSK_SBE	(1 << 13)
 #define DWMCI_INTMSK_ACD	(1 << 14)
 #define DWMCI_INTMSK_EBE	(1 << 15)

 /* Raw interrupt Regsiter */
 #define DWMCI_DATA_ERR	(DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
 			DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
 #define DWMCI_DATA_TOUT	(DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
 /* CTRL register */
 #define DWMCI_CTRL_RESET	(1 << 0)
 #define DWMCI_CTRL_FIFO_RESET	(1 << 1)
 #define DWMCI_CTRL_DMA_RESET	(1 << 2)
 #define DWMCI_DMA_EN		(1 << 5)
 #define DWMCI_CTRL_SEND_AS_CCSD	(1 << 10)
 #define DWMCI_IDMAC_EN		(1 << 25)
 #define DWMCI_RESET_ALL		(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
 				DWMCI_CTRL_DMA_RESET)

 /* CMD register */
 #define DWMCI_CMD_RESP_EXP	(1 << 6)
 #define DWMCI_CMD_RESP_LENGTH	(1 << 7)
 #define DWMCI_CMD_CHECK_CRC	(1 << 8)
 #define DWMCI_CMD_DATA_EXP	(1 << 9)
 #define DWMCI_CMD_RW		(1 << 10)
 #define DWMCI_CMD_SEND_STOP	(1 << 12)
 #define DWMCI_CMD_ABORT_STOP	(1 << 14)
 #define DWMCI_CMD_PRV_DAT_WAIT	(1 << 13)
 #define DWMCI_CMD_UPD_CLK	(1 << 21)
 #define DWMCI_CMD_USE_HOLD_REG	(1 << 29)
 #define DWMCI_CMD_START		(1 << 31)

 /* CLKENA register */
 #define DWMCI_CLKEN_ENABLE	(1 << 0)
 #define DWMCI_CLKEN_LOW_PWR	(1 << 16)

 /* Card-type registe */
 #define DWMCI_CTYPE_1BIT	0
 #define DWMCI_CTYPE_4BIT	(1 << 0)
 #define DWMCI_CTYPE_8BIT	(1 << 16)

 /* Status Register */
 #define DWMCI_BUSY		(1 << 9)
 #define DWMCI_MC_BUSY		(1 << 10)

 /* FIFOTH Register */
 #define MSIZE(x)		((x) << 28)
 #define RX_WMARK(x)		((x) << 16)
 #define TX_WMARK(x)		(x)
 #define RX_WMARK_SHIFT		16
 #define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)

 #define DWMCI_IDMAC_OWN		(1 << 31)
 #define DWMCI_IDMAC_CH		(1 << 4)
 #define DWMCI_IDMAC_FS		(1 << 3)
 #define DWMCI_IDMAC_LD		(1 << 2)

 /*  Bus Mode Register */
 #define DWMCI_BMOD_IDMAC_RESET	(1 << 0)
 #define DWMCI_BMOD_IDMAC_FB	(1 << 1)
 #define DWMCI_BMOD_IDMAC_EN	(1 << 7)

 #define MPSCTRL_SECURE_READ_BIT		(0x1 << 7)
 #define MPSCTRL_SECURE_WRITE_BIT	(0x1 << 6)
 #define MPSCTRL_NON_SECURE_READ_BIT	(0x1 << 5)
 #define MPSCTRL_NON_SECURE_WRITE_BIT	(0x1 << 4)
 #define MPSCTRL_USE_FUSE_KEY		(0x1 << 3)
 #define MPSCTRL_ECB_MODE		(0x1 << 2)
 #define MPSCTRL_ENCRYPTION		(0x1 << 1)
 #define MPSCTRL_VALID			(0x1 << 0)

 /* CLKSEL register */
 #define DWMCI_SET_SAMPLE_CLK(x)	(x)
 #define DWMCI_SET_DRV_CLK(x)	((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
 #define DWMCI_GET_DIV_RATIO(x)	(((x) >> 24) & 0x7)

 typedef struct DwmciHost {
 	MmcCtrlr mmc;

 	void *ioaddr;
 	uint32_t clock;
 	uint32_t src_hz;
 	uint32_t clksel_val;
 	uint32_t fifoth_val;

 	int initialized;
 	int removable;

 	// If NULL use internal card detect, else use gpio detect.
 	GpioOps *cd_gpio;

 	// By default uses the CLKDIV register.
 	void (*set_clk)(struct DwmciHost *me, unsigned int freq);
 } DwmciHost;

 typedef struct {
 	uint32_t flags;
 	uint32_t cnt;
 	uint32_t addr;
 	uint32_t next_addr;
 } DwmciIdmac;

 static inline void dwmci_write32(DwmciHost *host, int reg, uint32_t val)
 {
 	write32(host->ioaddr + reg, val);
 }

 static inline void dwmci_write16(DwmciHost *host, int reg, uint16_t val)
 {
 	write16(host->ioaddr + reg, val);
 }

 static inline void dwmci_write8(DwmciHost *host, int reg, uint8_t val)
 {
 	write8(host->ioaddr + reg, val);
 }
 static inline uint32_t dwmci_read32(DwmciHost *host, int reg)
 {
 	return read32(host->ioaddr + reg);
 }

 static inline uint16_t dwmci_read16(DwmciHost *host, int reg)
 {
 	return read16(host->ioaddr + reg);
 }

 static inline uint8_t dwmci_read8(DwmciHost *host, int reg)
 {
 	return read8(host->ioaddr + reg);
 }

 static inline void *dwmci_get_ioaddr(DwmciHost *host, int reg)
 {
 	return (void *)((uint8_t *)host->ioaddr + reg);
 }

 DwmciHost *new_dwmci_host(uintptr_t ioaddr, uint32_t src_hz,
 				int bus_width, int removable,
 				GpioOps *card_detect, uint32_t clksel_val);
 #endif /* __DRIVERS_BLOCKDEV_DW_MMC_H__ */
	/*
	* (C) Copyright 2012 SAMSUNG Electronics
	* Jaehoon Chung <jh80.chung@samsung.com>
	* Copyright 2013 Google Inc. All rights reserved.
	*
	* This program is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	*
	*/

	#ifndef __DRIVERS_BLOCKDEV_DW_MMC_H__
	#define __DRIVERS_BLOCKDEV_DW_MMC_H__

	#include "base/io.h"
	#include "drivers/gpio/gpio.h"
	#include "drivers/blockdev/blockdev.h"
	#include "drivers/blockdev/mmc.h"

	#define DWMCI_CTRL 0x000
	#define DWMCI_PWREN 0x004
	#define DWMCI_CLKDIV 0x008
	#define DWMCI_CLKSRC 0x00C
	#define DWMCI_CLKENA 0x010
	#define DWMCI_TMOUT 0x014
	#define DWMCI_CTYPE 0x018
	#define DWMCI_BLKSIZ 0x01C
	#define DWMCI_BYTCNT 0x020
	#define DWMCI_INTMASK 0x024
	#define DWMCI_CMDARG 0x028
	#define DWMCI_CMD 0x02C
	#define DWMCI_RESP0 0x030
	#define DWMCI_RESP1 0x034
	#define DWMCI_RESP2 0x038
	#define DWMCI_RESP3 0x03C
	#define DWMCI_MINTSTS 0x040
	#define DWMCI_RINTSTS 0x044
	#define DWMCI_STATUS 0x048
	#define DWMCI_FIFOTH 0x04C
	#define DWMCI_CDETECT 0x050
	#define DWMCI_WRTPRT 0x054
	#define DWMCI_GPIO 0x058
	#define DWMCI_TCMCNT 0x05C
	#define DWMCI_TBBCNT 0x060
	#define DWMCI_DEBNCE 0x064
	#define DWMCI_USRID 0x068
	#define DWMCI_VERID 0x06C
	#define DWMCI_HCON 0x070
	#define DWMCI_UHS_REG 0x074
	#define DWMCI_BMOD 0x080
	#define DWMCI_PLDMND 0x084
	#define DWMCI_DBADDR 0x088
	#define DWMCI_IDSTS 0x08C
	#define DWMCI_IDINTEN 0x090
	#define DWMCI_DSCADDR 0x094
	#define DWMCI_BUFADDR 0x098
	#define DWMCI_CLKSEL 0x09C
	#define DWMCI_DATA 0x200
	#define EMMCP_MPSBEGIN0 0x1200
	#define EMMCP_SEND0 0x1204
	#define EMMCP_CTRL0 0x120C

	/* Interrupt Mask register */
	#define DWMCI_INTMSK_ALL 0xffffffff
	#define DWMCI_INTMSK_RE (1 << 1)
	#define DWMCI_INTMSK_CDONE (1 << 2)
	#define DWMCI_INTMSK_DTO (1 << 3)
	#define DWMCI_INTMSK_TXDR (1 << 4)
	#define DWMCI_INTMSK_RXDR (1 << 5)
	#define DWMCI_INTMSK_DCRC (1 << 7)
	#define DWMCI_INTMSK_RTO (1 << 8)
	#define DWMCI_INTMSK_DRTO (1 << 9)
	#define DWMCI_INTMSK_HTO (1 << 10)
	#define DWMCI_INTMSK_FRUN (1 << 11)
	#define DWMCI_INTMSK_HLE (1 << 12)
	#define DWMCI_INTMSK_SBE (1 << 13)
	#define DWMCI_INTMSK_ACD (1 << 14)
	#define DWMCI_INTMSK_EBE (1 << 15)

	/* Raw interrupt Regsiter */
	#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE \| DWMCI_INTMSK_SBE \| DWMCI_INTMSK_HLE \|\
	DWMCI_INTMSK_FRUN \| DWMCI_INTMSK_EBE \| DWMCI_INTMSK_DCRC)
	#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO \| DWMCI_INTMSK_DRTO)
	/* CTRL register */
	#define DWMCI_CTRL_RESET (1 << 0)
	#define DWMCI_CTRL_FIFO_RESET (1 << 1)
	#define DWMCI_CTRL_DMA_RESET (1 << 2)
	#define DWMCI_DMA_EN (1 << 5)
	#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
	#define DWMCI_IDMAC_EN (1 << 25)
	#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET \| DWMCI_CTRL_FIFO_RESET \|\
	DWMCI_CTRL_DMA_RESET)

	/* CMD register */
	#define DWMCI_CMD_RESP_EXP (1 << 6)
	#define DWMCI_CMD_RESP_LENGTH (1 << 7)
	#define DWMCI_CMD_CHECK_CRC (1 << 8)
	#define DWMCI_CMD_DATA_EXP (1 << 9)
	#define DWMCI_CMD_RW (1 << 10)
	#define DWMCI_CMD_SEND_STOP (1 << 12)
	#define DWMCI_CMD_ABORT_STOP (1 << 14)
	#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
	#define DWMCI_CMD_UPD_CLK (1 << 21)
	#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
	#define DWMCI_CMD_START (1 << 31)

	/* CLKENA register */
	#define DWMCI_CLKEN_ENABLE (1 << 0)
	#define DWMCI_CLKEN_LOW_PWR (1 << 16)

	/* Card-type registe */
	#define DWMCI_CTYPE_1BIT 0
	#define DWMCI_CTYPE_4BIT (1 << 0)
	#define DWMCI_CTYPE_8BIT (1 << 16)

	/* Status Register */
	#define DWMCI_BUSY (1 << 9)
	#define DWMCI_MC_BUSY (1 << 10)

	/* FIFOTH Register */
	#define MSIZE(x) ((x) << 28)
	#define RX_WMARK(x) ((x) << 16)
	#define TX_WMARK(x) (x)
	#define RX_WMARK_SHIFT 16
	#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)

	#define DWMCI_IDMAC_OWN (1 << 31)
	#define DWMCI_IDMAC_CH (1 << 4)
	#define DWMCI_IDMAC_FS (1 << 3)
	#define DWMCI_IDMAC_LD (1 << 2)

	/* Bus Mode Register */
	#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
	#define DWMCI_BMOD_IDMAC_FB (1 << 1)
	#define DWMCI_BMOD_IDMAC_EN (1 << 7)

	#define MPSCTRL_SECURE_READ_BIT (0x1 << 7)
	#define MPSCTRL_SECURE_WRITE_BIT (0x1 << 6)
	#define MPSCTRL_NON_SECURE_READ_BIT (0x1 << 5)
	#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1 << 4)
	#define MPSCTRL_USE_FUSE_KEY (0x1 << 3)
	#define MPSCTRL_ECB_MODE (0x1 << 2)
	#define MPSCTRL_ENCRYPTION (0x1 << 1)
	#define MPSCTRL_VALID (0x1 << 0)

	/* CLKSEL register */
	#define DWMCI_SET_SAMPLE_CLK(x) (x)
	#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
	#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
	#define DWMCI_GET_DIV_RATIO(x) (((x) >> 24) & 0x7)

	typedef struct DwmciHost {
	MmcCtrlr mmc;

	void *ioaddr;
	uint32_t clock;
	uint32_t src_hz;
	uint32_t clksel_val;
	uint32_t fifoth_val;

	int initialized;
	int removable;

	// If NULL use internal card detect, else use gpio detect.
	GpioOps *cd_gpio;

	// By default uses the CLKDIV register.
	void (set_clk)(struct DwmciHost me, unsigned int freq);
	} DwmciHost;

	typedef struct {
	uint32_t flags;
	uint32_t cnt;
	uint32_t addr;
	uint32_t next_addr;
	} DwmciIdmac;

	static inline void dwmci_write32(DwmciHost *host, int reg, uint32_t val)
	{
	write32(host->ioaddr + reg, val);
	}

	static inline void dwmci_write16(DwmciHost *host, int reg, uint16_t val)
	{
	write16(host->ioaddr + reg, val);
	}

	static inline void dwmci_write8(DwmciHost *host, int reg, uint8_t val)
	{
	write8(host->ioaddr + reg, val);
	}
	static inline uint32_t dwmci_read32(DwmciHost *host, int reg)
	{
	return read32(host->ioaddr + reg);
	}

	static inline uint16_t dwmci_read16(DwmciHost *host, int reg)
	{
	return read16(host->ioaddr + reg);
	}

	static inline uint8_t dwmci_read8(DwmciHost *host, int reg)
	{
	return read8(host->ioaddr + reg);
	}

	static inline void dwmci_get_ioaddr(DwmciHost host, int reg)
	{
	return (void )((uint8_t )host->ioaddr + reg);
	}

	DwmciHost *new_dwmci_host(uintptr_t ioaddr, uint32_t src_hz,
	int bus_width, int removable,
	GpioOps *card_detect, uint32_t clksel_val);
	#endif /* __DRIVERS_BLOCKDEV_DW_MMC_H__ */