commit dcbec535eaaf753239d5e1fcee8133284db3e17b
author Catena cyber <35799796+catenacyber@users.noreply.github.com> Wed Jun 06 00:09:53 2018 +0200
committer Nguyen Anh Quynh <aquynh@gmail.com> Wed Jun 06 06:09:53 2018 +0800
tree c2ab926d0b451134e70e389b81fee429472408c1
parent 6e4c59d9973b78d0b6868fe8d98214c46be18677

Fixes shift for ARM memory operand (#1162)

Shift is for same operand as index register

arch/ARM/ARMInstPrinter.c

diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index 655b2ee..1baf1de 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -2111,8 +2111,8 @@
 		SStream_concat0(O, ", lsl ");
 		SStream_concat(O, "#%d", ShAmt);
 		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;
+			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
+			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt;
 		}
 	}