arm: BX & BLX write to PC. see #1126
diff --git a/arch/ARM/ARMMappingInsn.inc b/arch/ARM/ARMMappingInsn.inc
index eccda5e..7bb9c26 100644
--- a/arch/ARM/ARMMappingInsn.inc
+++ b/arch/ARM/ARMMappingInsn.inc
@@ -154,49 +154,49 @@
{
ARM_BLX, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1
#endif
},
{
ARM_BLX_pred, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1
#endif
},
{
ARM_BLXi, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0
#endif
},
{
ARM_BL_pred, ARM_INS_BL,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0
#endif
},
{
ARM_BX, ARM_INS_BX,
#ifndef CAPSTONE_DIET
- { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1
#endif
},
{
ARM_BXJ, ARM_INS_BXJ,
#ifndef CAPSTONE_DIET
- { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 1
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1
#endif
},
{
ARM_BX_RET, ARM_INS_BX,
#ifndef CAPSTONE_DIET
- { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1
#endif
},
{
ARM_BX_pred, ARM_INS_BX,
#ifndef CAPSTONE_DIET
- { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1
#endif
},
{
@@ -12922,31 +12922,31 @@
{
ARM_tBL, ARM_INS_BL,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0
#endif
},
{
ARM_tBLXi, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0
#endif
},
{
ARM_tBLXr, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
- { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, 0, 1
+ { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, 0, 1
#endif
},
{
ARM_tBX, ARM_INS_BX,
#ifndef CAPSTONE_DIET
- { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 1
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB, ARM_REG_PC, 0 }, 0, 1
#endif
},
{
ARM_tBcc, ARM_INS_B,
#ifndef CAPSTONE_DIET
- { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
#endif
},
{
