merge next to master
diff --git a/.gitignore b/.gitignore
index ec5bc8d..868739d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -69,6 +69,9 @@
tests/test_m680x
tests/test_evm
+# regress binaries
+suite/regress/invalid_read_in_print_operand
+
# vim tmp file
*.swp
*~
@@ -95,6 +98,9 @@
*.VC.db
*.VC.opendb
+# CMake build directories
+build*/
+
# Xcode
xcode/Capstone.xcodeproj/xcuserdata
xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
@@ -107,5 +113,6 @@
*.s
+.DS_Store
cstool/cstool
diff --git a/CMakeLists.txt b/CMakeLists.txt
index b4a961f..1932ffd 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -102,6 +102,7 @@
include/capstone/arm64.h
include/capstone/arm.h
include/capstone/capstone.h
+ include/capstone/evm.h
include/capstone/mips.h
include/capstone/ppc.h
include/capstone/x86.h
@@ -114,7 +115,6 @@
include/capstone/platform.h
)
-
set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
## architecture support
@@ -140,6 +140,18 @@
arch/ARM/ARMMappingInsn.inc
arch/ARM/ARMMappingInsnOp.inc
)
+ set(HEADERS_ARM
+ arch/ARM/ARMAddressingModes.h
+ arch/ARM/ARMBaseInfo.h
+ arch/ARM/ARMDisassembler.h
+ arch/ARM/ARMGenAsmWriter.inc
+ arch/ARM/ARMGenDisassemblerTables.inc
+ arch/ARM/ARMGenInstrInfo.inc
+ arch/ARM/ARMGenRegisterInfo.inc
+ arch/ARM/ARMGenSubtargetInfo.inc
+ arch/ARM/ARMInstPrinter.h
+ arch/ARM/ARMMapping.h
+ )
set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
endif ()
@@ -165,6 +177,18 @@
arch/AArch64/AArch64Mapping.h
arch/AArch64/AArch64MappingInsn.inc
)
+ set(HEADERS_ARM64
+ arch/AArch64/AArch64AddressingModes.h
+ arch/AArch64/AArch64BaseInfo.h
+ arch/AArch64/AArch64Disassembler.h
+ arch/AArch64/AArch64GenAsmWriter.inc
+ arch/AArch64/AArch64GenDisassemblerTables.inc
+ arch/AArch64/AArch64GenInstrInfo.inc
+ arch/AArch64/AArch64GenRegisterInfo.inc
+ arch/AArch64/AArch64GenSubtargetInfo.inc
+ arch/AArch64/AArch64InstPrinter.h
+ arch/AArch64/AArch64Mapping.h
+ )
set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
endif ()
@@ -187,6 +211,16 @@
arch/Mips/MipsMapping.h
arch/Mips/MipsMappingInsn.inc
)
+ set(HEADERS_MIPS
+ arch/Mips/MipsDisassembler.h
+ arch/Mips/MipsGenAsmWriter.inc
+ arch/Mips/MipsGenDisassemblerTables.inc
+ arch/Mips/MipsGenInstrInfo.inc
+ arch/Mips/MipsGenRegisterInfo.inc
+ arch/Mips/MipsGenSubtargetInfo.inc
+ arch/Mips/MipsInstPrinter.h
+ arch/Mips/MipsMapping.h
+ )
set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
endif ()
@@ -210,6 +244,17 @@
arch/PowerPC/PPCMappingInsn.inc
arch/PowerPC/PPCPredicates.h
)
+ set(HEADERS_PPC
+ arch/PowerPC/PPCDisassembler.h
+ arch/PowerPC/PPCGenAsmWriter.inc
+ arch/PowerPC/PPCGenDisassemblerTables.inc
+ arch/PowerPC/PPCGenInstrInfo.inc
+ arch/PowerPC/PPCGenRegisterInfo.inc
+ arch/PowerPC/PPCGenSubtargetInfo.inc
+ arch/PowerPC/PPCInstPrinter.h
+ arch/PowerPC/PPCMapping.h
+ arch/PowerPC/PPCPredicates.h
+ )
set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
endif ()
@@ -243,6 +288,23 @@
arch/X86/X86MappingInsnOp_reduce.inc
arch/X86/X86MappingInsn_reduce.inc
)
+ set(HEADERS_X86
+ arch/X86/X86BaseInfo.h
+ arch/X86/X86Disassembler.h
+ arch/X86/X86DisassemblerDecoder.h
+ arch/X86/X86DisassemblerDecoderCommon.h
+ arch/X86/X86GenAsmWriter.inc
+ arch/X86/X86GenAsmWriter1.inc
+ arch/X86/X86GenAsmWriter1_reduce.inc
+ arch/X86/X86GenAsmWriter_reduce.inc
+ arch/X86/X86GenDisassemblerTables.inc
+ arch/X86/X86GenDisassemblerTables_reduce.inc
+ arch/X86/X86GenInstrInfo.inc
+ arch/X86/X86GenInstrInfo_reduce.inc
+ arch/X86/X86GenRegisterInfo.inc
+ arch/X86/X86InstPrinter.h
+ arch/X86/X86Mapping.h
+ )
if (NOT CAPSTONE_BUILD_DIET)
set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
endif ()
@@ -256,7 +318,7 @@
arch/Sparc/SparcInstPrinter.c
arch/Sparc/SparcMapping.c
arch/Sparc/SparcModule.c
- )
+ )
set(HEADERS_SPARC
arch/Sparc/Sparc.h
arch/Sparc/SparcDisassembler.h
@@ -278,9 +340,9 @@
arch/SystemZ/SystemZDisassembler.c
arch/SystemZ/SystemZInstPrinter.c
arch/SystemZ/SystemZMapping.c
- arch/SystemZ/SystemZMCTargetDesc.c
arch/SystemZ/SystemZModule.c
- )
+ arch/SystemZ/SystemZMCTargetDesc.c
+ )
set(HEADERS_SYSZ
arch/SystemZ/SystemZDisassembler.h
arch/SystemZ/SystemZGenAsmWriter.inc
@@ -303,7 +365,7 @@
arch/XCore/XCoreInstPrinter.c
arch/XCore/XCoreMapping.c
arch/XCore/XCoreModule.c
- )
+ )
set(HEADERS_XCORE
arch/XCore/XCoreDisassembler.h
arch/XCore/XCoreGenAsmWriter.inc
@@ -460,8 +522,8 @@
endif ()
if(NOT DEFINED default-target) # honor `capstone-static` for tests first.
- set(default-target capstone-shared)
- add_definitions(-DCAPSTONE_SHARED)
+ set(default-target capstone-shared)
+ add_definitions(-DCAPSTONE_SHARED)
endif ()
endif ()
diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT
index 24705ed..8441306 100644
--- a/COMPILE_MSVC.TXT
+++ b/COMPILE_MSVC.TXT
@@ -23,8 +23,8 @@
Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose
the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
then directly editing the projects "capstone_static" & "capstone_dll" for static
- and dynamic libraries, respectively. This must be done before going to the
- next steps.
+ and dynamic libraries, respectively. This must be done before going to the next
+ steps.
In VisualStudio interface, modify the preprocessor definitions via
"Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor"
diff --git a/CREDITS.TXT b/CREDITS.TXT
index 669c4a1..f2581f3 100644
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@@ -55,6 +55,15 @@
Benoit Lecocq: OpenBSD package.
Christophe Avoinne (Hlide): Improve memory management for better performance.
Michael Cohen & Nguyen Tan Cong: Python module installer.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Tang Yuhang: cstool.
+Andrew Dutcher: better Python setup.
+Ruben Boonen: PowerShell binding.
+David Zimmer: VB6 binding.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
Bui Dinh Cuong: Explicit registers accessed for Arm64.
Vincent Bénony: Explicit registers accessed for X86.
Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
@@ -68,4 +77,3 @@
Wolfgang Schwotzer: M680X architecture.
Philippe Antoine: Integration with oss-fuzz and various fixes.
Stephen Eckels (stevemk14ebr): x86 encoding features
-
diff --git a/ChangeLog b/ChangeLog
index 1094cff..6c14478 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -102,6 +102,364 @@
- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
---------------------------------
+Version 3.0.5: July 1xth, 2018
+
+
+[ Core ]
+
+- Fix the include path for Android builds when building cstool.
+- Add posibility to disable universal build for Mac OS.
+- cstool: Separate instruction bytes by spaces.
+- Fix code path of pkg-config in Cmake.
+- Update XCode project for XCode 9.1.
+- Add Cortex-M support to cstool.
+- Cmake forces to be build using MT with MSVC.
+- Better support for Mac OS kernel.
+
+
+[ X86 ]
+
+- Fix some issues in handling EVEX & VEX3 instructions.
+- Fix immediate operand for AND instruction in ATT mode.
+- Fix ATT syntax when imm operand is 0.
+- Better handle XACQUIRE/XRELEASE.
+- Fix imm operand of RETF.
+
+
+[ ARM ]
+
+- Fix an integer overlow bug.
+
+
+[ ARM64 ]
+
+- Bug fix for incorrect operand type in certain load/store instructions.
+
+
+[ Mips ]
+
+- Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32
+
+
+[ PPC ]
+
+- Fix endian check.
+
+
+[ Sparc ]
+
+- Fix an integer overlow bug.
+
+
+[ SystemZ ]
+
+- Fix an integer overlow bug.
+
+
+[ Python binding ]
+
+- Raise error on accessing irrelevant data fields if skipdata & detail modes are enable.
+
+
+---------------------------------
+Version 3.0.5-rc3: July 31st, 2017
+
+
+[ Core ]
+
+- Fix compilation for MacOS kernel extension
+- cstool to support armbe and arm64be modes
+- Add nmake.bat for Windows build
+- Fix an integer overflow for Windows kernel driver
+- Support to embedded Capstone into MacOS kernel
+- cstool: fix mips64 mode
+- Fix a compiling error in MS Visual Studio 2015
+- Install pkgconfig file with CMake build
+- Fix SOVERSION property of CMake build
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+- Fix MingW build
+- Better handle CMake installation for Linux 64bit
+
+
+[ X86 ]
+
+- Support BND prefix of Intel MPX extension
+- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66
+- LOCK NOP is a valid instruction
+- Fix ATT syntax for instruction with zero offset segment register
+- LES/LDS are invalid in 64bit mode
+- Fix number of operands for some MOV instructions
+
+
+[ ARM ]
+
+- Fix POP reg to update SP register
+- Update flags for UADD8 instruction
+
+
+[ ARM64 ]
+
+- Better performance with new lookup table
+- Handle system registers added in ARMv8.1/2
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ Visual Basic binding ]
+
+- New binding
+
+---------------------------------
+Version 3.0.5-rc2: March 2nd, 2017
+
+
+[ Core ]
+
+- Fix build for Visual Studio 2012
+- Fix X86_REL_ADDR macro
+- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA
+- Better support for embedding Capstone into Windows kernel drivers
+- Support to embedded Capstone into MacOS kernel
+- Support MacOS 10.11 and up
+- Better support for Cygwin
+- Support build packages for FreeBSD & DragonflyBSD
+- Add a command-line tool "cstool"
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+
+
+[ X86 ]
+
+- Some random 16-bit code can be handled wrongly.
+- Remove abundant operand type X86_OP_FP
+- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL
+- Add X86_REG_EFLAGS for STC and STD
+- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT
+- Rename registers ST0-ST7 to be consistent with asm output
+
+
+[ ARM ]
+
+- Properly handle IT instruction
+- Fix LDRSB
+- Fix writeback for LDR
+- Fix Thumb BigEndian setup
+
+
+[ ARM64 ]
+
+- Fix arith extender
+- Fix writeback for LDR
+- Rename enum arm64_mrs_reg to arm64_sysreg
+
+
+[ PowerPC ]
+
+- Print 0 offset for memory operand
+
+
+[ Sparc ]
+
+- Fix POPC instruction
+
+
+[ Python binding ]
+
+- Better PyPy support
+- Add __version__
+- Better support for Python 3
+- Fix CS_SKIPDATA_CALLBACK prototype
+- Cast skipdata function inside binding to simplify the API
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ PowerShell ]
+
+- New binding
+
+---------------------------------
+Version 3.0.4: July 15th, 2015
+
+
+[ Library ]
+
+- Improve cross-compile for Android using Android NDK.
+- Support cross-compile for AArch64 Android (with Linux GCC).
+- Removed osxkernel_inttypes.h that is incompatible with BSD license.
+- Make it possible to compile with CC having a space inside (like "ccache gcc").
+
+
+[ X86 ]
+
+- Fix a null pointer dereference bug on handling code with special prefixes.
+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
+- Print immediate operand in positive form in some algorithm instructions.
+- Properly decode some SSE instructions.
+
+
+[ PowerPC ]
+
+- Fixed a memory corruption bug.
+- Fixed a memory corruption bug for the engine built in DIET mode.
+
+
+[ Mips ]
+
+- Fixed instruction ID of SUBU instruction.
+- Fixed a memory corruption bug.
+
+
+[ Arm ]
+
+- Fixed a memory corruption bug on IT instruction.
+
+
+[ XCore ]
+
+- Fixed a memory corruption bug when instruction has a memory operand.
+
+
+[ Python ]
+
+- Support Virtualenv.
+- setup.py supports option --user if not in a virtualenv to allow for local usage.
+- Properly handle the destruction of Cs object in the case the shared library
+ was already unloaded.
+
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+ GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+ $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+ "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
+
+---------------------------------
+Version 3.0.2: March 11th, 2015
+
+
+[ Library ]
+
+- On *nix, only export symbols that are part of the API (instead of all
+ the internal symbols).
+
+
+[ X86 ]
+
+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
+- Fix implicit registers read/written & instruction groups of some instructions.
+- More flexible on the order of prefixes, so better handle some tricky
+ instructions.
+- REPNE prefix can go with STOS & MOVS instructions.
+- Fix a compilation bug for X86_REDUCE mode.
+- Fix operand size of instructions with operand PTR []
+
+
+[ Arm ]
+
+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
+- Fix a bug on handling the If-Then block.
+
+
+[ Mips ]
+
+- Sanity check for the input size for MIPS64 mode.
+
+
+[ MSVC ]
+
+- Compile capstone.dll with static runtime MSVCR built in.
+
+
+[ Python binding ]
+
+- Fix a compiling issue of Cython binding with gcc 4.9.
+
+---------------------------------
+Version 3.0.1: February 03rd, 2015
+
+[ X86 ]
+
+- Properly handle LOCK, REP, REPE & REPNE prefixes.
+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
+- Print LJUMP/LCALL without * as prefix for Intel syntax.
+- Handle REX prefix properly for segment/MMX related instructions (x86_64).
+- Instruction with length > 15 is consider invalid.
+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
+ FSTP, FSTPNCE, NOP.
+- Handle some tricky code for some X86_64 instructions with REX prefix.
+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
+- MOV32ms & MOV32sm should reference word rather than dword.
+
+
+[ Arm64 ]
+
+- BL & BLR instructions do not read SP register.
+- Print absolute (rather than relative) address for instructions B, BL,
+ CBNZ, ADR.
+
+
+[ Arm ]
+
+- Instructions ADC & SBC do not update flags.
+- BL & BLX do not read SP, but PC register.
+- Alias LDR instruction with operands [sp], 4 to POP.
+- Print immediate operand of MVN instruction in positive hexadecimal form.
+
+
+[ PowerPC ]
+
+- Fix some compilation bugs when DIET mode is enable.
+- Populate SLWI/SRWI instruction details with SH operand.
+
+
+[ Python binding ]
+
+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
+- Fixed a memory leak for Cython disasm functions when we immaturely quit
+ the enumeration of disassembled instructions.
+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
+ at the same time.
+- Fix a memory leaking bug when when we stop enumeration over the disassembled
+ instructions prematurely.
+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
+
+---------------------------------
Version 3.0: November 19th, 2014
[ API ]
diff --git a/MCInst.h b/MCInst.h
index 6a70741..6e95c3a 100644
--- a/MCInst.h
+++ b/MCInst.h
@@ -53,8 +53,6 @@
bool MCOperand_isInst(const MCOperand *op);
-void MCInst_clear(MCInst *m);
-
/// getReg - Returns the register number.
unsigned MCOperand_getReg(const MCOperand *op);
diff --git a/MCInstrDesc.c b/MCInstrDesc.c
index 8186e1a..1f70d86 100644
--- a/MCInstrDesc.c
+++ b/MCInstrDesc.c
@@ -5,14 +5,14 @@
/// isPredicate - Set if this is one of the operands that made up of
/// the predicate operand that controls an isPredicable() instruction.
-bool MCOperandInfo_isPredicate(MCOperandInfo *m)
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m)
{
return m->Flags & (1 << MCOI_Predicate);
}
/// isOptionalDef - Set if this operand is a optional def.
///
-bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m)
{
return m->Flags & (1 << MCOI_OptionalDef);
}
diff --git a/MCInstrDesc.h b/MCInstrDesc.h
index 275ae77..a71ec57 100644
--- a/MCInstrDesc.h
+++ b/MCInstrDesc.h
@@ -121,24 +121,24 @@
/// this struct directly to describe itself.
typedef struct MCInstrDesc {
unsigned short Opcode; // The opcode number
- unsigned short NumOperands; // Num of args (may be more if variable_ops)
- unsigned short NumDefs; // Num of args that are definitions
+ unsigned char NumOperands; // Num of args (may be more if variable_ops)
+ unsigned char NumDefs; // Num of args that are definitions
unsigned short SchedClass; // enum identifying instr sched class
- unsigned short Size; // Number of bytes in encoding.
+ unsigned char Size; // Number of bytes in encoding.
unsigned Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
- uint16_t *ImplicitUses; // Registers implicitly read by this instr
- uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
- MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
+ char ImplicitUses; // Registers implicitly read by this instr
+ char ImplicitDefs; // Registers implicitly defined by this instr
+ const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
// A complex method to determine is a certain is deprecated or not, and return
// the reason for deprecation.
//bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
- unsigned ComplexDeprecationInfo; // dummy field, just to satisfy initializer
+ unsigned char ComplexDeprecationInfo; // dummy field, just to satisfy initializer
} MCInstrDesc;
-bool MCOperandInfo_isPredicate(MCOperandInfo *m);
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
-bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
#endif
diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c
index 026272b..66db2f8 100644
--- a/MCRegisterInfo.c
+++ b/MCRegisterInfo.c
@@ -22,18 +22,18 @@
/// defined below.
typedef struct DiffListIterator {
uint16_t Val;
- MCPhysReg *List;
+ const MCPhysReg *List;
} DiffListIterator;
void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
- MCRegisterDesc *D, unsigned NR,
+ const MCRegisterDesc *D, unsigned NR,
unsigned RA, unsigned PC,
- MCRegisterClass *C, unsigned NC,
+ const MCRegisterClass *C, unsigned NC,
uint16_t (*RURoots)[2], unsigned NRU,
- MCPhysReg *DL,
- char *Strings,
- uint16_t *SubIndices, unsigned NumIndices,
- uint16_t *RET)
+ const MCPhysReg *DL,
+ const char *Strings,
+ const uint16_t *SubIndices, unsigned NumIndices,
+ const uint16_t *RET)
{
RI->Desc = D;
RI->NumRegs = NR;
@@ -50,7 +50,7 @@
RI->RegEncodingTable = RET;
}
-static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList)
{
d->Val = InitVal;
d->List = DiffList;
@@ -83,7 +83,7 @@
return (d->List != 0);
}
-unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC)
{
DiffListIterator iter;
@@ -105,10 +105,10 @@
return 0;
}
-unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
{
DiffListIterator iter;
- uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+ const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
DiffListIterator_next(&iter);
@@ -123,7 +123,7 @@
return 0;
}
-MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
{
//assert(i < getNumRegClasses() && "Register Class ID out of range");
if (i >= RI->NumClasses)
@@ -131,7 +131,7 @@
return &(RI->Classes[i]);
}
-bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
{
unsigned InByte = Reg % 8;
unsigned Byte = Reg / 8;
diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h
index 6d51e19..3744ef7 100644
--- a/MCRegisterInfo.h
+++ b/MCRegisterInfo.h
@@ -24,11 +24,11 @@
/// An unsigned integer type large enough to represent all physical registers,
/// but not necessarily virtual registers.
typedef uint16_t MCPhysReg;
-typedef MCPhysReg* iterator;
+typedef const MCPhysReg* iterator;
typedef struct MCRegisterClass {
iterator RegsBegin;
- uint8_t *RegSet;
+ const uint8_t *RegSet;
uint32_t NameIdx;
uint16_t RegsSize;
uint16_t RegSetSize;
@@ -76,41 +76,41 @@
/// virtual methods.
///
typedef struct MCRegisterInfo {
- MCRegisterDesc *Desc; // Pointer to the descriptor array
+ const MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the array
unsigned RAReg; // Return address register
unsigned PCReg; // Program counter register
- MCRegisterClass *Classes; // Pointer to the regclass array
+ const MCRegisterClass *Classes; // Pointer to the regclass array
unsigned NumClasses; // Number of entries in the array
unsigned NumRegUnits; // Number of regunits.
uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
- MCPhysReg *DiffLists; // Pointer to the difflists array
- char *RegStrings; // Pointer to the string table.
- uint16_t *SubRegIndices; // Pointer to the subreg lookup
+ const MCPhysReg *DiffLists; // Pointer to the difflists array
+ const char *RegStrings; // Pointer to the string table.
+ const uint16_t *SubRegIndices; // Pointer to the subreg lookup
// array.
unsigned NumSubRegIndices; // Number of subreg indices.
- uint16_t *RegEncodingTable; // Pointer to array of register
+ const uint16_t *RegEncodingTable; // Pointer to array of register
// encodings.
} MCRegisterInfo;
void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
- MCRegisterDesc *D, unsigned NR, unsigned RA,
+ const MCRegisterDesc *D, unsigned NR, unsigned RA,
unsigned PC,
- MCRegisterClass *C, unsigned NC,
+ const MCRegisterClass *C, unsigned NC,
uint16_t (*RURoots)[2],
unsigned NRU,
- MCPhysReg *DL,
- char *Strings,
- uint16_t *SubIndices,
+ const MCPhysReg *DL,
+ const char *Strings,
+ const uint16_t *SubIndices,
unsigned NumIndices,
- uint16_t *RET);
+ const uint16_t *RET);
-unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);
-unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
-MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i);
-bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
#endif
diff --git a/Makefile b/Makefile
index 0118122..377d110 100644
--- a/Makefile
+++ b/Makefile
@@ -40,7 +40,7 @@
CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
endif
-CFLAGS += -fPIC -Wall -Iinclude
+CFLAGS += -fPIC -Wall -Wwrite-strings -Iinclude
ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
@@ -73,10 +73,10 @@
# Uncomment the below line to installs x86_64 libs to lib64/ directory.
# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
#LIBDIRARCH ?= lib64
-LIBDIR ?= $(PREFIX)/$(LIBDIRARCH)
-BINDIR = $(PREFIX)/bin
+LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
+BINDIR = $(DESTDIR)$(PREFIX)/bin
-LIBDATADIR ?= $(LIBDIR)
+LIBDATADIR = $(LIBDIR)
# Don't redefine $LIBDATADIR when global environment variable
# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
@@ -453,11 +453,11 @@
TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc
-TESTS += test_systemz test_x86 test_xcore test_iter
+TESTS += test_systemz test_x86 test_xcore test_iter test_evm
TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
-TESTS += test_skipdata test_skipdata.static test_iter.static
+TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static
check: $(TESTS)
test_%:
./tests/$@ > /dev/null && echo OK || echo FAILED
diff --git a/README.md b/README.md
index e25acef..7b9b22e 100644
--- a/README.md
+++ b/README.md
@@ -20,13 +20,13 @@
- Provide semantics of the disassembled instruction, such as list of implicit
registers read & written.
-- Implemented in pure C language, with lightweight bindings for PHP, PowerShell,
+- Implemented in pure C language, with lightweight bindings for Visual Basic, PHP, PowerShell,
Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua,
Rust, Delphi, Free Pascal & Vala ready either in main code, or provided
externally by the community).
- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
- Linux, *BSD, Solaris, etc.
+ Linux, \*BSD, Solaris, etc.
- Thread-safe by design.
diff --git a/SStream.c b/SStream.c
index 90cef53..5ae237f 100644
--- a/SStream.c
+++ b/SStream.c
@@ -28,7 +28,7 @@
ss->buffer[0] = '\0';
}
-void SStream_concat0(SStream *ss, char *s)
+void SStream_concat0(SStream *ss, const char *s)
{
#ifndef CAPSTONE_DIET
unsigned int len = (unsigned int) strlen(s);
@@ -106,7 +106,10 @@
if (val >= 0)
SStream_concat(O, "#%u", val);
else
- SStream_concat(O, "#-%u", (uint32_t)-val);
+ if (val == INT_MIN)
+ SStream_concat(O, "#-%u", val);
+ else
+ SStream_concat(O, "#-%u", (uint32_t)-val);
}
void printInt32Bang(SStream *O, int32_t val)
diff --git a/SStream.h b/SStream.h
index 9ccd351..3473085 100644
--- a/SStream.h
+++ b/SStream.h
@@ -15,7 +15,7 @@
void SStream_concat(SStream *ss, const char *fmt, ...);
-void SStream_concat0(SStream *ss, char *s);
+void SStream_concat0(SStream *ss, const char *s);
void printInt64Bang(SStream *O, int64_t val);
diff --git a/arch/AArch64/AArch64AddressingModes.h b/arch/AArch64/AArch64AddressingModes.h
index 4de6f10..2d714e8 100644
--- a/arch/AArch64/AArch64AddressingModes.h
+++ b/arch/AArch64/AArch64AddressingModes.h
@@ -198,7 +198,7 @@
// where B = NOT(b);
FPUnion.I = 0;
- FPUnion.I |= (uint32_t) Sign << 31;
+ FPUnion.I |= ((uint32_t)Sign) << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
index 5afb924..4478f48 100644
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -28,7 +28,7 @@
#include "AArch64BaseInfo.h"
-char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid)
+const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
{
unsigned i;
for (i = 0; i < N->NumPairs; ++i) {
@@ -44,7 +44,7 @@
// compare s1 with lower(s2)
// return true if s1 == lower(f2), and false otherwise
-static bool compare_lower_str(char *s1, char *s2)
+static bool compare_lower_str(const char *s1, const char *s2)
{
bool res;
char *lower = cs_strdup(s2), *c;
@@ -57,7 +57,7 @@
return res;
}
-uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid)
+uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid)
{
unsigned i;
for (i = 0; i < N->NumPairs; ++i) {
@@ -71,7 +71,7 @@
return (uint32_t)-1;
}
-bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value)
+bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value)
{
return Value < N->TooBigImm;
}
@@ -98,7 +98,9 @@
return result;
}
-static A64NamedImmMapper_Mapping SysRegPairs[] = {
+static const A64NamedImmMapper_Mapping SysRegPairs[] = {
+ {"pan", A64SysReg_PAN},
+ {"uao", A64SysReg_UAO},
{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
{"osdtrtx_el1", A64SysReg_OSDTRTX_EL1},
{"teecr32_el1", A64SysReg_TEECR32_EL1},
@@ -180,12 +182,14 @@
{"vpidr_el2", A64SysReg_VPIDR_EL2},
{"vmpidr_el2", A64SysReg_VMPIDR_EL2},
{"sctlr_el1", A64SysReg_SCTLR_EL1},
+ {"sctlr_el12", A64SysReg_SCTLR_EL12},
{"sctlr_el2", A64SysReg_SCTLR_EL2},
{"sctlr_el3", A64SysReg_SCTLR_EL3},
{"actlr_el1", A64SysReg_ACTLR_EL1},
{"actlr_el2", A64SysReg_ACTLR_EL2},
{"actlr_el3", A64SysReg_ACTLR_EL3},
{"cpacr_el1", A64SysReg_CPACR_EL1},
+ {"cpacr_el12", A64SysReg_CPACR_EL12},
{"hcr_el2", A64SysReg_HCR_EL2},
{"scr_el3", A64SysReg_SCR_EL3},
{"mdcr_el2", A64SysReg_MDCR_EL2},
@@ -196,19 +200,25 @@
{"hacr_el2", A64SysReg_HACR_EL2},
{"mdcr_el3", A64SysReg_MDCR_EL3},
{"ttbr0_el1", A64SysReg_TTBR0_EL1},
+ {"ttbr0_el12", A64SysReg_TTBR0_EL12},
{"ttbr0_el2", A64SysReg_TTBR0_EL2},
{"ttbr0_el3", A64SysReg_TTBR0_EL3},
{"ttbr1_el1", A64SysReg_TTBR1_EL1},
+ {"ttbr1_el12", A64SysReg_TTBR1_EL12},
+ {"ttbr1_el2", A64SysReg_TTBR1_EL2},
{"tcr_el1", A64SysReg_TCR_EL1},
+ {"tcr_el12", A64SysReg_TCR_EL12},
{"tcr_el2", A64SysReg_TCR_EL2},
{"tcr_el3", A64SysReg_TCR_EL3},
{"vttbr_el2", A64SysReg_VTTBR_EL2},
{"vtcr_el2", A64SysReg_VTCR_EL2},
{"dacr32_el2", A64SysReg_DACR32_EL2},
{"spsr_el1", A64SysReg_SPSR_EL1},
+ {"spsr_el12", A64SysReg_SPSR_EL12},
{"spsr_el2", A64SysReg_SPSR_EL2},
{"spsr_el3", A64SysReg_SPSR_EL3},
{"elr_el1", A64SysReg_ELR_EL1},
+ {"elr_el12", A64SysReg_ELR_EL12},
{"elr_el2", A64SysReg_ELR_EL2},
{"elr_el3", A64SysReg_ELR_EL3},
{"sp_el0", A64SysReg_SP_EL0},
@@ -228,16 +238,20 @@
{"dlr_el0", A64SysReg_DLR_EL0},
{"ifsr32_el2", A64SysReg_IFSR32_EL2},
{"afsr0_el1", A64SysReg_AFSR0_EL1},
+ {"afsr0_el12", A64SysReg_AFSR0_EL12},
{"afsr0_el2", A64SysReg_AFSR0_EL2},
{"afsr0_el3", A64SysReg_AFSR0_EL3},
{"afsr1_el1", A64SysReg_AFSR1_EL1},
+ {"afsr1_el12", A64SysReg_AFSR1_EL12},
{"afsr1_el2", A64SysReg_AFSR1_EL2},
{"afsr1_el3", A64SysReg_AFSR1_EL3},
{"esr_el1", A64SysReg_ESR_EL1},
+ {"esr_el12", A64SysReg_ESR_EL12},
{"esr_el2", A64SysReg_ESR_EL2},
{"esr_el3", A64SysReg_ESR_EL3},
{"fpexc32_el2", A64SysReg_FPEXC32_EL2},
{"far_el1", A64SysReg_FAR_EL1},
+ {"far_el12", A64SysReg_FAR_EL12},
{"far_el2", A64SysReg_FAR_EL2},
{"far_el3", A64SysReg_FAR_EL3},
{"hpfar_el2", A64SysReg_HPFAR_EL2},
@@ -255,18 +269,23 @@
{"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
{"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
{"mair_el1", A64SysReg_MAIR_EL1},
+ {"mair_el12", A64SysReg_MAIR_EL12},
{"mair_el2", A64SysReg_MAIR_EL2},
{"mair_el3", A64SysReg_MAIR_EL3},
{"amair_el1", A64SysReg_AMAIR_EL1},
+ {"amair_el12", A64SysReg_AMAIR_EL12},
{"amair_el2", A64SysReg_AMAIR_EL2},
{"amair_el3", A64SysReg_AMAIR_EL3},
{"vbar_el1", A64SysReg_VBAR_EL1},
+ {"vbar_el12", A64SysReg_VBAR_EL12},
{"vbar_el2", A64SysReg_VBAR_EL2},
{"vbar_el3", A64SysReg_VBAR_EL3},
{"rmr_el1", A64SysReg_RMR_EL1},
{"rmr_el2", A64SysReg_RMR_EL2},
{"rmr_el3", A64SysReg_RMR_EL3},
{"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
+ {"contextidr_el12", A64SysReg_CONTEXTIDR_EL12},
+ {"contextidr_el2", A64SysReg_CONTEXTIDR_EL2},
{"tpidr_el0", A64SysReg_TPIDR_EL0},
{"tpidr_el2", A64SysReg_TPIDR_EL2},
{"tpidr_el3", A64SysReg_TPIDR_EL3},
@@ -275,19 +294,28 @@
{"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
{"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
{"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
+ {"cntkctl_el12", A64SysReg_CNTKCTL_EL12},
{"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
{"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
+ {"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02},
{"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
{"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
{"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
{"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
+ {"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2},
+ {"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2},
+ {"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2},
{"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
{"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
+ {"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02},
{"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
{"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
{"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
+ {"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02},
{"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
+ {"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02},
{"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
+ {"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02},
{"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
{"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
{"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
@@ -351,6 +379,10 @@
{"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
{"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
{"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
+ {"lorc_el1", A64SysReg_LORC_EL1},
+ {"lorea_el1", A64SysReg_LOREA_EL1},
+ {"lorn_el1", A64SysReg_LORN_EL1},
+ {"lorsa_el1", A64SysReg_LORSA_EL1},
// Trace registers
{"trcprgctlr", A64SysReg_TRCPRGCTLR},
@@ -574,15 +606,28 @@
{"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
{"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
{"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
- {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}
+ {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2},
+
+ // Statistical profiling registers
+ {"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1},
+ {"pmbptr_el1", A64SysReg_PMBPTR_EL1},
+ {"pmbsr_el1", A64SysReg_PMBSR_EL1},
+ {"pmscr_el1", A64SysReg_PMSCR_EL1},
+ {"pmscr_el12", A64SysReg_PMSCR_EL12},
+ {"pmscr_el2", A64SysReg_PMSCR_EL2},
+ {"pmsicr_el1", A64SysReg_PMSICR_EL1},
+ {"pmsirr_el1", A64SysReg_PMSIRR_EL1},
+ {"pmsfcr_el1", A64SysReg_PMSFCR_EL1},
+ {"pmsevfr_el1", A64SysReg_PMSEVFR_EL1},
+ {"pmslatfr_el1", A64SysReg_PMSLATFR_EL1}
};
-static A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
+static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
};
// result must be a big enough buffer: 128 bytes is more than enough
-void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, char *result)
+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result)
{
int dummy;
uint32_t Op0, Op1, CRn, CRm, Op2;
@@ -640,7 +685,7 @@
cs_mem_free(Op2S);
}
-static A64NamedImmMapper_Mapping TLBIPairs[] = {
+static const A64NamedImmMapper_Mapping TLBIPairs[] = {
{"ipas2e1is", A64TLBI_IPAS2E1IS},
{"ipas2le1is", A64TLBI_IPAS2LE1IS},
{"vmalle1is", A64TLBI_VMALLE1IS},
@@ -675,13 +720,13 @@
{"vaale1", A64TLBI_VAALE1}
};
-A64NamedImmMapper A64TLBI_TLBIMapper = {
+const A64NamedImmMapper A64TLBI_TLBIMapper = {
TLBIPairs,
ARR_SIZE(TLBIPairs),
0,
};
-static A64NamedImmMapper_Mapping ATPairs[] = {
+static const A64NamedImmMapper_Mapping ATPairs[] = {
{"s1e1r", A64AT_S1E1R},
{"s1e2r", A64AT_S1E2R},
{"s1e3r", A64AT_S1E3R},
@@ -693,16 +738,16 @@
{"s12e1r", A64AT_S12E1R},
{"s12e1w", A64AT_S12E1W},
{"s12e0r", A64AT_S12E0R},
- {"s12e0w", A64AT_S12E0W},
+ {"s12e0w", A64AT_S12E0W}
};
-A64NamedImmMapper A64AT_ATMapper = {
+const A64NamedImmMapper A64AT_ATMapper = {
ATPairs,
ARR_SIZE(ATPairs),
0,
};
-static A64NamedImmMapper_Mapping DBarrierPairs[] = {
+static const A64NamedImmMapper_Mapping DBarrierPairs[] = {
{"oshld", A64DB_OSHLD},
{"oshst", A64DB_OSHST},
{"osh", A64DB_OSH},
@@ -717,13 +762,13 @@
{"sy", A64DB_SY}
};
-A64NamedImmMapper A64DB_DBarrierMapper = {
+const A64NamedImmMapper A64DB_DBarrierMapper = {
DBarrierPairs,
ARR_SIZE(DBarrierPairs),
16,
};
-static A64NamedImmMapper_Mapping DCPairs[] = {
+static const A64NamedImmMapper_Mapping DCPairs[] = {
{"zva", A64DC_ZVA},
{"ivac", A64DC_IVAC},
{"isw", A64DC_ISW},
@@ -734,35 +779,35 @@
{"cisw", A64DC_CISW}
};
-A64NamedImmMapper A64DC_DCMapper = {
+const A64NamedImmMapper A64DC_DCMapper = {
DCPairs,
ARR_SIZE(DCPairs),
0,
};
-static A64NamedImmMapper_Mapping ICPairs[] = {
+static const A64NamedImmMapper_Mapping ICPairs[] = {
{"ialluis", A64IC_IALLUIS},
{"iallu", A64IC_IALLU},
{"ivau", A64IC_IVAU}
};
-A64NamedImmMapper A64IC_ICMapper = {
+const A64NamedImmMapper A64IC_ICMapper = {
ICPairs,
ARR_SIZE(ICPairs),
0,
};
-static A64NamedImmMapper_Mapping ISBPairs[] = {
+static const A64NamedImmMapper_Mapping ISBPairs[] = {
{"sy", A64DB_SY},
};
-A64NamedImmMapper A64ISB_ISBMapper = {
+const A64NamedImmMapper A64ISB_ISBMapper = {
ISBPairs,
ARR_SIZE(ISBPairs),
16,
};
-static A64NamedImmMapper_Mapping PRFMPairs[] = {
+static const A64NamedImmMapper_Mapping PRFMPairs[] = {
{"pldl1keep", A64PRFM_PLDL1KEEP},
{"pldl1strm", A64PRFM_PLDL1STRM},
{"pldl2keep", A64PRFM_PLDL2KEEP},
@@ -783,25 +828,27 @@
{"pstl3strm", A64PRFM_PSTL3STRM}
};
-A64NamedImmMapper A64PRFM_PRFMMapper = {
+const A64NamedImmMapper A64PRFM_PRFMMapper = {
PRFMPairs,
ARR_SIZE(PRFMPairs),
32,
};
-static A64NamedImmMapper_Mapping PStatePairs[] = {
+static const A64NamedImmMapper_Mapping PStatePairs[] = {
{"spsel", A64PState_SPSel},
{"daifset", A64PState_DAIFSet},
- {"daifclr", A64PState_DAIFClr}
+ {"daifclr", A64PState_DAIFClr},
+ {"pan", A64PState_PAN},
+ {"uao", A64PState_UAO}
};
-A64NamedImmMapper A64PState_PStateMapper = {
+const A64NamedImmMapper A64PState_PStateMapper = {
PStatePairs,
ARR_SIZE(PStatePairs),
0,
};
-static A64NamedImmMapper_Mapping MRSPairs[] = {
+static const A64NamedImmMapper_Mapping MRSPairs[] = {
{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
{"mdrar_el1", A64SysReg_MDRAR_EL1},
@@ -825,6 +872,7 @@
{"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
{"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
{"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
+ {"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1},
{"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
{"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
{"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
@@ -841,6 +889,8 @@
{"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
{"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
{"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
+ {"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1},
+ {"lorid_el1", A64SysReg_LORID_EL1},
{"mvfr0_el1", A64SysReg_MVFR0_EL1},
{"mvfr1_el1", A64SysReg_MVFR1_EL1},
{"mvfr2_el1", A64SysReg_MVFR2_EL1},
@@ -897,16 +947,20 @@
{"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
{"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
{"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
- {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}
+ {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2},
+
+ // Statistical profiling registers
+ {"pmsidr_el1", A64SysReg_PMSIDR_EL1},
+ {"pmbidr_el1", A64SysReg_PMBIDR_EL1}
};
-A64SysRegMapper AArch64_MRSMapper = {
+const A64SysRegMapper AArch64_MRSMapper = {
NULL,
MRSPairs,
ARR_SIZE(MRSPairs),
};
-static A64NamedImmMapper_Mapping MSRPairs[] = {
+static const A64NamedImmMapper_Mapping MSRPairs[] = {
{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
{"oslar_el1", A64SysReg_OSLAR_EL1},
{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
@@ -924,7 +978,7 @@
{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
};
-A64SysRegMapper AArch64_MSRMapper = {
+const A64SysRegMapper AArch64_MSRMapper = {
NULL,
MSRPairs,
ARR_SIZE(MSRPairs),
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
index 214cfc3..3c082a1 100644
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -95,7 +95,7 @@
A64CC_Invalid
} A64CC_CondCode;
-inline static char *getCondCodeName(A64CC_CondCode CC)
+inline static const char *getCondCodeName(A64CC_CondCode CC)
{
switch (CC) {
default: return NULL; // never reach
@@ -136,33 +136,33 @@
/// might even be optimal to just reorder the tables for the common instructions
/// rather than changing the algorithm.
typedef struct A64NamedImmMapper_Mapping {
- char *Name;
+ const char *Name;
uint32_t Value;
} A64NamedImmMapper_Mapping;
typedef struct A64NamedImmMapper {
- A64NamedImmMapper_Mapping *Pairs;
+ const A64NamedImmMapper_Mapping *Pairs;
size_t NumPairs;
uint32_t TooBigImm;
} A64NamedImmMapper;
typedef struct A64SysRegMapper {
- A64NamedImmMapper_Mapping *SysRegPairs;
- A64NamedImmMapper_Mapping *InstPairs;
+ const A64NamedImmMapper_Mapping *SysRegPairs;
+ const A64NamedImmMapper_Mapping *InstPairs;
size_t NumInstPairs;
} A64SysRegMapper;
-extern A64SysRegMapper AArch64_MSRMapper;
-extern A64SysRegMapper AArch64_MRSMapper;
+extern const A64SysRegMapper AArch64_MSRMapper;
+extern const A64SysRegMapper AArch64_MRSMapper;
-extern A64NamedImmMapper A64DB_DBarrierMapper;
-extern A64NamedImmMapper A64AT_ATMapper;
-extern A64NamedImmMapper A64DC_DCMapper;
-extern A64NamedImmMapper A64IC_ICMapper;
-extern A64NamedImmMapper A64ISB_ISBMapper;
-extern A64NamedImmMapper A64PRFM_PRFMMapper;
-extern A64NamedImmMapper A64PState_PStateMapper;
-extern A64NamedImmMapper A64TLBI_TLBIMapper;
+extern const A64NamedImmMapper A64DB_DBarrierMapper;
+extern const A64NamedImmMapper A64AT_ATMapper;
+extern const A64NamedImmMapper A64DC_DCMapper;
+extern const A64NamedImmMapper A64IC_ICMapper;
+extern const A64NamedImmMapper A64ISB_ISBMapper;
+extern const A64NamedImmMapper A64PRFM_PRFMMapper;
+extern const A64NamedImmMapper A64PState_PStateMapper;
+extern const A64NamedImmMapper A64TLBI_TLBIMapper;
enum {
A64AT_Invalid = -1, // Op0 Op1 CRn CRm Op2
@@ -246,7 +246,9 @@
A64PState_Invalid = -1,
A64PState_SPSel = 0x05,
A64PState_DAIFSet = 0x1e,
- A64PState_DAIFClr = 0x1f
+ A64PState_DAIFClr = 0x1f,
+ A64PState_PAN = 0x4,
+ A64PState_UAO = 0x3
};
typedef enum A64SE_ShiftExtSpecifiers {
@@ -288,7 +290,7 @@
A64Layout_VL_D
} A64Layout_VectorLayout;
-inline static char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
+inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
{
switch (Layout) {
case A64Layout_VL_8B: return ".8b";
@@ -331,6 +333,7 @@
A64SysReg_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
A64SysReg_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
A64SysReg_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
+ A64SysReg_ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110
A64SysReg_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
A64SysReg_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
A64SysReg_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
@@ -347,6 +350,12 @@
A64SysReg_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
A64SysReg_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
A64SysReg_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
+ A64SysReg_ID_A64MMFR2_EL1 = 0xC03A, // 11 000 0000 0111 010
+ A64SysReg_LORC_EL1 = 0xc523, // 11 000 1010 0100 011
+ A64SysReg_LOREA_EL1 = 0xc521, // 11 000 1010 0100 001
+ A64SysReg_LORID_EL1 = 0xc527, // 11 000 1010 0100 111
+ A64SysReg_LORN_EL1 = 0xc522, // 11 000 1010 0100 010
+ A64SysReg_LORSA_EL1 = 0xc520, // 11 000 1010 0100 000
A64SysReg_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
A64SysReg_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
A64SysReg_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
@@ -426,6 +435,8 @@
enum A64SysRegValues {
A64SysReg_Invalid = -1, // Op0 Op1 CRn CRm Op2
+ A64SysReg_PAN = 0xc213, // 11 000 0100 0010 011
+ A64SysReg_UAO = 0xc214, // 11 000 0100 0010 100
A64SysReg_OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
A64SysReg_OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
A64SysReg_TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
@@ -507,7 +518,9 @@
A64SysReg_VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
A64SysReg_VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
A64SysReg_CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
+ A64SysReg_CPACR_EL12 = 0xe882, // 11 101 0001 0000 010
A64SysReg_SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
+ A64SysReg_SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000
A64SysReg_SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
A64SysReg_SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
A64SysReg_ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
@@ -523,19 +536,25 @@
A64SysReg_HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
A64SysReg_MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
A64SysReg_TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
+ A64SysReg_TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000
A64SysReg_TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
A64SysReg_TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
A64SysReg_TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
+ A64SysReg_TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001
+ A64SysReg_TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001
A64SysReg_TCR_EL1 = 0xc102, // 11 000 0010 0000 010
+ A64SysReg_TCR_EL12 = 0xe902, // 11 101 0010 0000 010
A64SysReg_TCR_EL2 = 0xe102, // 11 100 0010 0000 010
A64SysReg_TCR_EL3 = 0xf102, // 11 110 0010 0000 010
A64SysReg_VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
A64SysReg_VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
A64SysReg_DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
A64SysReg_SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
+ A64SysReg_SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
A64SysReg_SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
A64SysReg_SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
A64SysReg_ELR_EL1 = 0xc201, // 11 000 0100 0000 001
+ A64SysReg_ELR_EL12 = 0xea01, // 11 101 0100 0000 001
A64SysReg_ELR_EL2 = 0xe201, // 11 100 0100 0000 001
A64SysReg_ELR_EL3 = 0xf201, // 11 110 0100 0000 001
A64SysReg_SP_EL0 = 0xc208, // 11 000 0100 0001 000
@@ -555,16 +574,20 @@
A64SysReg_DLR_EL0 = 0xda29, // 11 011 0100 0101 001
A64SysReg_IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
A64SysReg_AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
+ A64SysReg_AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000
A64SysReg_AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
A64SysReg_AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
A64SysReg_AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
+ A64SysReg_AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001
A64SysReg_AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
A64SysReg_AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
A64SysReg_ESR_EL1 = 0xc290, // 11 000 0101 0010 000
+ A64SysReg_ESR_EL12 = 0xea90, // 11 101 0101 0010 000
A64SysReg_ESR_EL2 = 0xe290, // 11 100 0101 0010 000
A64SysReg_ESR_EL3 = 0xf290, // 11 110 0101 0010 000
A64SysReg_FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
A64SysReg_FAR_EL1 = 0xc300, // 11 000 0110 0000 000
+ A64SysReg_FAR_EL12 = 0xeb00, // 11 101 0110 0000 000
A64SysReg_FAR_EL2 = 0xe300, // 11 100 0110 0000 000
A64SysReg_FAR_EL3 = 0xf300, // 11 110 0110 0000 000
A64SysReg_HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
@@ -582,18 +605,23 @@
A64SysReg_PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
A64SysReg_PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
A64SysReg_MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
+ A64SysReg_MAIR_EL12 = 0xed10, // 11 101 1010 0010 000
A64SysReg_MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
A64SysReg_MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
A64SysReg_AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
+ A64SysReg_AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000
A64SysReg_AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
A64SysReg_AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
A64SysReg_VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
+ A64SysReg_VBAR_EL12 = 0xee00, // 11 101 1100 0000 000
A64SysReg_VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
A64SysReg_VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
A64SysReg_RMR_EL1 = 0xc602, // 11 000 1100 0000 010
A64SysReg_RMR_EL2 = 0xe602, // 11 100 1100 0000 010
A64SysReg_RMR_EL3 = 0xf602, // 11 110 1100 0000 010
A64SysReg_CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
+ A64SysReg_CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001
+ A64SysReg_CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001
A64SysReg_TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
A64SysReg_TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
A64SysReg_TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
@@ -602,19 +630,28 @@
A64SysReg_CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
A64SysReg_CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
A64SysReg_CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
+ A64SysReg_CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000
A64SysReg_CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
+ A64SysReg_CNTHVCTL_EL2 = 0xe719, // 11 100 1110 0011 001
+ A64SysReg_CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010
+ A64SysReg_CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000
A64SysReg_CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
+ A64SysReg_CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000
A64SysReg_CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
A64SysReg_CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
A64SysReg_CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
A64SysReg_CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
A64SysReg_CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
A64SysReg_CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
+ A64SysReg_CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010
A64SysReg_CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
A64SysReg_CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
A64SysReg_CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
+ A64SysReg_CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000
A64SysReg_CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
+ A64SysReg_CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001
A64SysReg_CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
+ A64SysReg_CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010
A64SysReg_PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
A64SysReg_PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
A64SysReg_PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
@@ -901,7 +938,22 @@
A64SysReg_ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
A64SysReg_ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
A64SysReg_ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
- A64SysReg_ICH_LR15_EL2 = 0xe66f // 11 100 1100 1101 111
+ A64SysReg_ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
+
+ // Statistical profiling registers
+ A64SysReg_PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111
+ A64SysReg_PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111
+ A64SysReg_PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000
+ A64SysReg_PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001
+ A64SysReg_PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011
+ A64SysReg_PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000
+ A64SysReg_PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000
+ A64SysReg_PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000
+ A64SysReg_PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010
+ A64SysReg_PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011
+ A64SysReg_PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100
+ A64SysReg_PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101
+ A64SysReg_PMSLATFR_EL1 = 0xc4ce // 11 000 1001 1001 110
};
// Cyclone specific system registers
@@ -947,12 +999,12 @@
bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
-char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid);
+const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid);
-uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid);
+uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid);
-bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value);
+bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value);
-void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, char *result);
+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result);
#endif
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index e6e0ef1..6f9bdae 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -38,143 +38,143 @@
// Definitions are further down.
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst,
unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder);
+ const void *Decoder);
static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder);
+ uint64_t Addr, const void *Decoder);
static bool Check(DecodeStatus *Out, DecodeStatus In)
{
@@ -280,7 +280,7 @@
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
if (RegNo > 31)
@@ -293,7 +293,7 @@
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
if (RegNo > 15)
return Fail;
@@ -313,7 +313,7 @@
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -337,7 +337,7 @@
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -361,7 +361,7 @@
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -385,7 +385,7 @@
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -409,7 +409,7 @@
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -423,7 +423,7 @@
static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -451,7 +451,7 @@
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -465,7 +465,7 @@
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -492,7 +492,7 @@
static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -516,7 +516,7 @@
};
static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
unsigned Register;
@@ -543,7 +543,7 @@
};
static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
unsigned Register;
@@ -571,7 +571,7 @@
static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
if (RegNo > 31)
@@ -594,7 +594,7 @@
};
static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
unsigned Register;
@@ -621,7 +621,7 @@
};
static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
unsigned Register;
@@ -649,7 +649,7 @@
static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Register;
@@ -663,7 +663,7 @@
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
// scale{5} is asserted as 1 in tblgen.
Imm |= 0x20;
@@ -673,14 +673,14 @@
static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
MCOperand_CreateImm0(Inst, 64 - Imm);
return Success;
}
static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
int64_t ImmVal = Imm;
@@ -693,7 +693,7 @@
}
static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
- uint64_t Address, void *Decoder)
+ uint64_t Address, const void *Decoder)
{
MCOperand_CreateImm0(Inst, (Imm >> 1) & 1);
MCOperand_CreateImm0(Inst, Imm & 1);
@@ -701,7 +701,7 @@
}
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
- uint64_t Address, void *Decoder)
+ uint64_t Address, const void *Decoder)
{
MCOperand_CreateImm0(Inst, Imm);
@@ -712,7 +712,7 @@
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
MCOperand_CreateImm0(Inst, Imm);
@@ -721,7 +721,7 @@
static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
// This decoder exists to add the dummy Lane operand to the MCInst, which must
// be 1 in assembly but has no other real manifestation.
@@ -758,77 +758,77 @@
}
static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 64);
}
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
}
static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 32);
}
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
}
static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 16);
}
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
}
static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 8);
}
static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 64);
}
static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 32);
}
static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 16);
}
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 8);
}
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
@@ -892,7 +892,7 @@
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned imm = fieldFromInstruction(insn, 5, 16);
@@ -928,7 +928,7 @@
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
@@ -989,14 +989,14 @@
static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
bool IsLoad;
bool IsIndexed;
bool IsFP;
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
- int32_t offset = fieldFromInstruction(insn, 12, 9);
+ int64_t offset = fieldFromInstruction(insn, 12, 9);
// offset is a 9-bit signed immediate, so sign extend it to
// fill the unsigned.
@@ -1178,7 +1178,7 @@
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
@@ -1254,7 +1254,7 @@
static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
@@ -1383,7 +1383,7 @@
static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rd, Rn, Rm;
unsigned extend = fieldFromInstruction(insn, 10, 6);
@@ -1443,7 +1443,7 @@
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
@@ -1476,7 +1476,7 @@
static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4);
@@ -1516,7 +1516,7 @@
static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4);
@@ -1534,11 +1534,10 @@
}
static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
- int32_t imm = fieldFromInstruction(insn, 5, 19) << 2;
-
+ int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
imm |= fieldFromInstruction(insn, 29, 2);
// Sign-extend the 21-bit immediate.
@@ -1553,7 +1552,7 @@
}
static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
@@ -1589,9 +1588,9 @@
static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
- int32_t imm = fieldFromInstruction(insn, 0, 26);
+ int64_t imm = fieldFromInstruction(insn, 0, 26);
// Sign-extend the 26-bit immediate.
if (imm & (1 << (26 - 1)))
@@ -1605,7 +1604,7 @@
static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
- void *Decoder)
+ const void *Decoder)
{
uint32_t op1 = fieldFromInstruction(insn, 16, 3);
uint32_t op2 = fieldFromInstruction(insn, 5, 3);
@@ -1622,7 +1621,7 @@
}
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
- uint64_t Addr, void *Decoder)
+ uint64_t Addr, const void *Decoder)
{
uint32_t Rt = fieldFromInstruction(insn, 0, 5);
uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5;
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
index 1933450..69dea43 100644
--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -4802,7 +4802,7 @@
};
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0,
/* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0,
/* 20 */ 'l', 'd', '1', 9, 0,
@@ -6554,12 +6554,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo, int AltIdx)
+static const char *getRegisterName(unsigned RegNo, int AltIdx)
{
// assert(RegNo && RegNo < 420 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrsNoRegAltName[] = {
+ static const char AsmStrsNoRegAltName[] = {
/* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
/* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
/* 26 */ 'b', '1', '0', 0,
@@ -6885,7 +6885,7 @@
301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411,
};
- static char AsmStrsvreg[] = {
+ static const char AsmStrsvreg[] = {
/* 0 */ 'v', '1', '0', 0,
/* 4 */ 'v', '2', '0', 0,
/* 8 */ 'v', '3', '0', 0,
@@ -6954,7 +6954,7 @@
};
const uint16_t *RegAsmOffset;
- char *AsmStrs;
+ const char *AsmStrs;
switch(AltIdx) {
default: // llvm_unreachable("Invalid register alt name index!");
diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc
index 3bddde0..ac4ca8d 100644
--- a/arch/AArch64/AArch64GenDisassemblerTables.inc
+++ b/arch/AArch64/AArch64GenDisassemblerTables.inc
@@ -24,7 +24,7 @@
return (insn & fieldMask) >> startBit; \
}
-static uint8_t DecoderTable32[] = {
+static const uint8_t DecoderTable32[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ...
/* 3 */ MCD_OPC_FilterValue, 2, 86, 4, // Skip to: 1117
/* 7 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
@@ -9602,7 +9602,7 @@
#define DecodeToMCInst(fname,fieldname, InsnType) \
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
- uint64_t Address, void *Decoder) \
+ uint64_t Address, const void *Decoder) \
{ \
InsnType tmp; \
switch (Idx) { \
@@ -12659,11 +12659,11 @@
}
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
- InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
{ \
uint64_t Bits = getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
+ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0, ExpectedValue; \
DecodeStatus S = MCDisassembler_Success; \
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
diff --git a/arch/AArch64/AArch64GenRegisterInfo.inc b/arch/AArch64/AArch64GenRegisterInfo.inc
index 7e82bb5..57eb693 100644
--- a/arch/AArch64/AArch64GenRegisterInfo.inc
+++ b/arch/AArch64/AArch64GenRegisterInfo.inc
@@ -567,7 +567,7 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg AArch64RegDiffLists[] = {
+static const MCPhysReg AArch64RegDiffLists[] = {
/* 0 */ 65185, 1, 1, 1, 0,
/* 5 */ 65281, 1, 1, 1, 0,
/* 10 */ 5, 29, 1, 1, 0,
@@ -627,7 +627,7 @@
/* 625 */ 65535, 0,
};
-static uint16_t AArch64SubRegIdxLists[] = {
+static const uint16_t AArch64SubRegIdxLists[] = {
/* 0 */ 2, 14, 7, 1, 0,
/* 5 */ 15, 0,
/* 7 */ 3, 14, 7, 1, 4, 18, 17, 16, 0,
@@ -1062,432 +1062,432 @@
};
// FPR8 Register Class...
- static MCPhysReg FPR8[] = {
+ static const MCPhysReg FPR8[] = {
AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31,
};
// FPR8 Bit set.
- static uint8_t FPR8Bits[] = {
+ static const uint8_t FPR8Bits[] = {
0x00, 0xff, 0xff, 0xff, 0xff,
};
// FPR16 Register Class...
- static MCPhysReg FPR16[] = {
+ static const MCPhysReg FPR16[] = {
AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31,
};
// FPR16 Bit set.
- static uint8_t FPR16Bits[] = {
+ static const uint8_t FPR16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// GPR32all Register Class...
- static MCPhysReg GPR32all[] = {
+ static const MCPhysReg GPR32all[] = {
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP,
};
// GPR32all Bit set.
- static uint8_t GPR32allBits[] = {
+ static const uint8_t GPR32allBits[] = {
0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
};
// FPR32 Register Class...
- static MCPhysReg FPR32[] = {
+ static const MCPhysReg FPR32[] = {
AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31,
};
// FPR32 Bit set.
- static uint8_t FPR32Bits[] = {
+ static const uint8_t FPR32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// GPR32 Register Class...
- static MCPhysReg GPR32[] = {
+ static const MCPhysReg GPR32[] = {
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR,
};
// GPR32 Bit set.
- static uint8_t GPR32Bits[] = {
+ static const uint8_t GPR32Bits[] = {
0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
};
// GPR32sp Register Class...
- static MCPhysReg GPR32sp[] = {
+ static const MCPhysReg GPR32sp[] = {
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP,
};
// GPR32sp Bit set.
- static uint8_t GPR32spBits[] = {
+ static const uint8_t GPR32spBits[] = {
0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
};
// GPR32common Register Class...
- static MCPhysReg GPR32common[] = {
+ static const MCPhysReg GPR32common[] = {
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30,
};
// GPR32common Bit set.
- static uint8_t GPR32commonBits[] = {
+ static const uint8_t GPR32commonBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
};
// CCR Register Class...
- static MCPhysReg CCR[] = {
+ static const MCPhysReg CCR[] = {
AArch64_NZCV,
};
// CCR Bit set.
- static uint8_t CCRBits[] = {
+ static const uint8_t CCRBits[] = {
0x08,
};
// GPR32sponly Register Class...
- static MCPhysReg GPR32sponly[] = {
+ static const MCPhysReg GPR32sponly[] = {
AArch64_WSP,
};
// GPR32sponly Bit set.
- static uint8_t GPR32sponlyBits[] = {
+ static const uint8_t GPR32sponlyBits[] = {
0x20,
};
// GPR64all Register Class...
- static MCPhysReg GPR64all[] = {
+ static const MCPhysReg GPR64all[] = {
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP,
};
// GPR64all Bit set.
- static uint8_t GPR64allBits[] = {
+ static const uint8_t GPR64allBits[] = {
0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
};
// FPR64 Register Class...
- static MCPhysReg FPR64[] = {
+ static const MCPhysReg FPR64[] = {
AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31,
};
// FPR64 Bit set.
- static uint8_t FPR64Bits[] = {
+ static const uint8_t FPR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// GPR64 Register Class...
- static MCPhysReg GPR64[] = {
+ static const MCPhysReg GPR64[] = {
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR,
};
// GPR64 Bit set.
- static uint8_t GPR64Bits[] = {
+ static const uint8_t GPR64Bits[] = {
0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
};
// GPR64sp Register Class...
- static MCPhysReg GPR64sp[] = {
+ static const MCPhysReg GPR64sp[] = {
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP,
};
// GPR64sp Bit set.
- static uint8_t GPR64spBits[] = {
+ static const uint8_t GPR64spBits[] = {
0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
};
// GPR64common Register Class...
- static MCPhysReg GPR64common[] = {
+ static const MCPhysReg GPR64common[] = {
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR,
};
// GPR64common Bit set.
- static uint8_t GPR64commonBits[] = {
+ static const uint8_t GPR64commonBits[] = {
0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
};
// tcGPR64 Register Class...
- static MCPhysReg tcGPR64[] = {
+ static const MCPhysReg tcGPR64[] = {
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18,
};
// tcGPR64 Bit set.
- static uint8_t tcGPR64Bits[] = {
+ static const uint8_t tcGPR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03,
};
// GPR64sponly Register Class...
- static MCPhysReg GPR64sponly[] = {
+ static const MCPhysReg GPR64sponly[] = {
AArch64_SP,
};
// GPR64sponly Bit set.
- static uint8_t GPR64sponlyBits[] = {
+ static const uint8_t GPR64sponlyBits[] = {
0x10,
};
// DD Register Class...
- static MCPhysReg DD[] = {
+ static const MCPhysReg DD[] = {
AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0,
};
// DD Bit set.
- static uint8_t DDBits[] = {
+ static const uint8_t DDBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// FPR128 Register Class...
- static MCPhysReg FPR128[] = {
+ static const MCPhysReg FPR128[] = {
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31,
};
// FPR128 Bit set.
- static uint8_t FPR128Bits[] = {
+ static const uint8_t FPR128Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// FPR128_lo Register Class...
- static MCPhysReg FPR128_lo[] = {
+ static const MCPhysReg FPR128_lo[] = {
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15,
};
// FPR128_lo Bit set.
- static uint8_t FPR128_loBits[] = {
+ static const uint8_t FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// DDD Register Class...
- static MCPhysReg DDD[] = {
+ static const MCPhysReg DDD[] = {
AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1,
};
// DDD Bit set.
- static uint8_t DDDBits[] = {
+ static const uint8_t DDDBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// DDDD Register Class...
- static MCPhysReg DDDD[] = {
+ static const MCPhysReg DDDD[] = {
AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2,
};
// DDDD Bit set.
- static uint8_t DDDDBits[] = {
+ static const uint8_t DDDDBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// QQ Register Class...
- static MCPhysReg QQ[] = {
+ static const MCPhysReg QQ[] = {
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0,
};
// QQ Bit set.
- static uint8_t QQBits[] = {
+ static const uint8_t QQBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// QQ_with_qsub0_in_FPR128_lo Register Class...
- static MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
+ static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
};
// QQ_with_qsub0_in_FPR128_lo Bit set.
- static uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
+ static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
};
// QQ_with_qsub1_in_FPR128_lo Register Class...
- static MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
+ static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0,
};
// QQ_with_qsub1_in_FPR128_lo Bit set.
- static uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
+ static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
};
// QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
- static MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
+ static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15,
};
// QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
- static uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
+ static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
};
// QQQ Register Class...
- static MCPhysReg QQQ[] = {
+ static const MCPhysReg QQQ[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
};
// QQQ Bit set.
- static uint8_t QQQBits[] = {
+ static const uint8_t QQQBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// QQQ_with_qsub0_in_FPR128_lo Register Class...
- static MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
+ static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17,
};
// QQQ_with_qsub0_in_FPR128_lo Bit set.
- static uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
+ static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
};
// QQQ_with_qsub1_in_FPR128_lo Register Class...
- static MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
+ static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1,
};
// QQQ_with_qsub1_in_FPR128_lo Bit set.
- static uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
+ static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
};
// QQQ_with_qsub2_in_FPR128_lo Register Class...
- static MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
+ static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
};
// QQQ_with_qsub2_in_FPR128_lo Bit set.
- static uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
+ static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c,
};
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
- static MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
+ static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
};
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
- static uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
+ static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
};
// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
- static MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
+ static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1,
};
// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
- static uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
+ static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08,
};
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
- static MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
+ static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15,
};
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
- static uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
+ static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03,
};
// QQQQ Register Class...
- static MCPhysReg QQQQ[] = {
+ static const MCPhysReg QQQQ[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ Bit set.
- static uint8_t QQQQBits[] = {
+ static const uint8_t QQQQBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// QQQQ_with_qsub0_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18,
};
// QQQQ_with_qsub0_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
};
// QQQQ_with_qsub1_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ_with_qsub1_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
};
// QQQQ_with_qsub2_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ_with_qsub2_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c,
};
// QQQQ_with_qsub3_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ_with_qsub3_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e,
};
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
};
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
};
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08,
};
// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c,
};
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16,
};
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03,
};
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2,
};
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08,
};
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
- static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15,
};
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
- static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
+ static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
};
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index f65a113..26d482f 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -38,7 +38,7 @@
#include "AArch64GenInstrInfo.inc"
-static char *getRegisterName(unsigned RegNo, int AltIdx);
+static const char *getRegisterName(unsigned RegNo, int AltIdx);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static bool printSysAlias(MCInst *MI, SStream *O);
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
@@ -106,7 +106,7 @@
bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);
if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) {
- char *AsmMnemonic = NULL;
+ const char *AsmMnemonic = NULL;
switch (MCOperand_getImm(Op3)) {
default:
@@ -165,7 +165,7 @@
// instruction. In all cases the immediate shift amount shift must be in
// the range 0 to (reg.size -1).
if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
- char *AsmMnemonic = NULL;
+ const char *AsmMnemonic = NULL;
int shift = 0;
int immr = (int)MCOperand_getImm(Op2);
int imms = (int)MCOperand_getImm(Op3);
@@ -275,7 +275,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op3) + 1;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1;
MI->flat_insn->detail->arm64.op_count++;
}
@@ -316,7 +316,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op2);
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2);
MI->flat_insn->detail->arm64.op_count++;
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
@@ -324,7 +324,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1;
MI->flat_insn->detail->arm64.op_count++;
}
@@ -454,7 +454,7 @@
// unsigned Opcode = MCInst_getOpcode(MI);
//assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!");
- char *Asm = NULL;
+ const char *Asm = NULL;
MCOperand *Op1 = MCInst_getOperand(MI, 0);
MCOperand *Cn = MCInst_getOperand(MI, 1);
MCOperand *Cm = MCInst_getOperand(MI, 2);
@@ -797,7 +797,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op);
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -877,7 +877,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op);
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -911,7 +911,7 @@
static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
{
- int64_t Val = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Val = AArch64_AM_decodeLogicalImmediate(Val, 32);
printUInt32Bang(O, (int)Val);
@@ -924,7 +924,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)Val;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -1203,7 +1203,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -1243,7 +1243,7 @@
{
unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
bool Valid;
- char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid);
+ const char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid);
if (Valid) {
SStream_concat0(O, Name);
@@ -1370,7 +1370,7 @@
// If it's a D-reg, we need to promote it to the equivalent Q-reg before
// printing (otherwise getRegisterName fails).
if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
- MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
+ const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
}
@@ -1523,11 +1523,7 @@
// ADRP sign extends a 21-bit offset, shifts it left by 12
// and adds it to the value of the PC with its bottom 12 bits cleared
uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff);
-
- if (imm > HEX_THRESHOLD)
- SStream_concat(O, "#0x%"PRIx64, imm);
- else
- SStream_concat(O, "#%"PRIu64, imm);
+ printUInt64Bang(O, imm);
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
@@ -1549,7 +1545,7 @@
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
unsigned Opcode = MCInst_getOpcode(MI);
bool Valid;
- char *Name;
+ const char *Name;
if (Opcode == AArch64_ISB)
Name = A64NamedImmMapper_toString(&A64ISB_ISBMapper, Val, &Valid);
@@ -1631,7 +1627,7 @@
{
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
bool Valid;
- char *Name;
+ const char *Name;
Name = A64NamedImmMapper_toString(&A64PState_PStateMapper, Val, &Valid);
if (Valid) {
@@ -1676,7 +1672,7 @@
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)Val;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
MI->flat_insn->detail->arm64.op_count++;
}
}
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index a08b75f..6f5bbd7 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -14,7 +14,7 @@
#include "AArch64GenInstrInfo.inc"
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ ARM64_REG_INVALID, NULL },
{ ARM64_REG_X29, "x29"},
@@ -292,7 +292,7 @@
#endif
}
-static insn_map insns[] = {
+static const insn_map insns[] = {
// dummy item
{
0, 0,
@@ -331,7 +331,7 @@
}
}
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ ARM64_INS_INVALID, NULL },
{ ARM64_INS_ABS, "abs" },
@@ -753,7 +753,7 @@
};
// map *S & alias instructions back to original id
-static name_map alias_insn_name_maps[] = {
+static const name_map alias_insn_name_maps[] = {
{ ARM64_INS_ADC, "adcs" },
{ ARM64_INS_AND, "ands" },
{ ARM64_INS_ADD, "adds" },
@@ -828,7 +828,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ ARM64_GRP_INVALID, NULL },
{ ARM64_GRP_JUMP, "jump" },
@@ -874,7 +874,7 @@
// for some reasons different Arm64 can map different register number to
// the same register. this function handles the issue for exposing Mips
// operands by mapping internal registers to 'public' register.
- unsigned int map[] = { 0,
+ static const unsigned int map[] = { 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h
index f61bead..8a2a1dd 100644
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@@ -35,12 +35,12 @@
ARM_AM_add
} ARM_AM_AddrOpc;
-static inline char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
+static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
{
return Op == ARM_AM_sub ? "-" : "";
}
-static inline char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
+static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
{
switch (Op) {
default: return ""; //llvm_unreachable("Unknown shift opc!");
@@ -658,7 +658,7 @@
// where B = NOT(b);
FPUnion.I = 0;
- FPUnion.I |= (uint32_t) Sign << 31;
+ FPUnion.I |= ((uint32_t) Sign) << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
diff --git a/arch/ARM/ARMBaseInfo.h b/arch/ARM/ARMBaseInfo.h
index 9fc4979..b4b0d36 100644
--- a/arch/ARM/ARMBaseInfo.h
+++ b/arch/ARM/ARMBaseInfo.h
@@ -70,7 +70,7 @@
}
}
-inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
+inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
{
switch (CC) {
case ARMCC_EQ: return "eq";
@@ -92,7 +92,7 @@
}
}
-inline static char *ARM_PROC_IFlagsToString(unsigned val)
+inline static const char *ARM_PROC_IFlagsToString(unsigned val)
{
switch (val) {
case ARM_CPSFLAG_F: return "f";
@@ -102,7 +102,7 @@
}
}
-inline static char *ARM_PROC_IModToString(unsigned val)
+inline static const char *ARM_PROC_IModToString(unsigned val)
{
switch (val) {
case ARM_CPSMODE_IE: return "ie";
@@ -111,7 +111,7 @@
}
}
-inline static char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
+inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
{
switch (val) {
default: return "BUGBUG";
@@ -153,7 +153,7 @@
ARM_ISB_SY = 15
};
-inline static char *ARM_ISB_InstSyncBOptToString(unsigned val)
+inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
{
switch (val) {
default: // never reach
@@ -222,7 +222,7 @@
ARMII_AddrMode_i12 = 16
} ARMII_AddrMode;
-inline static char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
+inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
{
switch (addrmode) {
case ARMII_AddrModeNone: return "AddrModeNone";
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index 08b25f3..ce714fc 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -576,7 +576,7 @@
// that as a post-pass.
static void AddThumb1SBit(MCInst *MI, bool InITBlock)
{
- MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+ const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
unsigned i;
@@ -600,7 +600,7 @@
static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
{
DecodeStatus S = MCDisassembler_Success;
- MCOperandInfo *OpInfo;
+ const MCOperandInfo *OpInfo;
unsigned short NumOps;
unsigned int i;
unsigned CC;
@@ -680,7 +680,7 @@
{
unsigned CC;
unsigned short NumOps;
- MCOperandInfo *OpInfo;
+ const MCOperandInfo *OpInfo;
unsigned i;
CC = ITStatus_getITCC(&(ud->ITBlock));
diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
index a22d754..ad9e4aa 100644
--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
@@ -5622,7 +5622,7 @@
};
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0,
/* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0,
/* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0,
@@ -8213,12 +8213,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 289 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
@@ -8445,12 +8445,12 @@
}
// get registers with number only
-static char *getRegisterName2(unsigned RegNo)
+static const char *getRegisterName2(unsigned RegNo)
{
// assert(RegNo && RegNo < 289 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
diff --git a/arch/ARM/ARMGenDisassemblerTables.inc b/arch/ARM/ARMGenDisassemblerTables.inc
index 38ba2d8..471e57e 100644
--- a/arch/ARM/ARMGenDisassemblerTables.inc
+++ b/arch/ARM/ARMGenDisassemblerTables.inc
@@ -24,7 +24,7 @@
return (insn & fieldMask) >> startBit; \
}
-static uint8_t DecoderTableARM32[] = {
+static const uint8_t DecoderTableARM32[] = {
/* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ...
/* 3 */ MCD_OPC_FilterValue, 0, 12, 12, // Skip to: 3091
/* 7 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
@@ -1893,7 +1893,7 @@
0
};
-static uint8_t DecoderTableNEONData32[] = {
+static const uint8_t DecoderTableNEONData32[] = {
/* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
/* 3 */ MCD_OPC_FilterValue, 0, 230, 30, // Skip to: 7917
/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
@@ -5436,7 +5436,7 @@
0
};
-static uint8_t DecoderTableNEONDup32[] = {
+static const uint8_t DecoderTableNEONDup32[] = {
/* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ...
/* 3 */ MCD_OPC_FilterValue, 56, 105, 0, // Skip to: 112
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
@@ -5529,7 +5529,7 @@
0
};
-static uint8_t DecoderTableNEONLoadStore32[] = {
+static const uint8_t DecoderTableNEONLoadStore32[] = {
/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ...
/* 3 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 280
/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
@@ -6916,7 +6916,7 @@
0
};
-static uint8_t DecoderTableThumb16[] = {
+static const uint8_t DecoderTableThumb16[] = {
/* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
/* 3 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 22
/* 7 */ MCD_OPC_CheckPredicate, 21, 210, 3, // Skip to: 989
@@ -7153,7 +7153,7 @@
0
};
-static uint8_t DecoderTableThumb32[] = {
+static const uint8_t DecoderTableThumb32[] = {
/* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
/* 3 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 34
/* 7 */ MCD_OPC_CheckPredicate, 28, 48, 0, // Skip to: 59
@@ -7178,7 +7178,7 @@
0
};
-static uint8_t DecoderTableThumb232[] = {
+static const uint8_t DecoderTableThumb232[] = {
/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
/* 3 */ MCD_OPC_FilterValue, 29, 25, 8, // Skip to: 2080
/* 7 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ...
@@ -8765,7 +8765,7 @@
0
};
-static uint8_t DecoderTableThumbSBit16[] = {
+static const uint8_t DecoderTableThumbSBit16[] = {
/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
/* 3 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 16
/* 7 */ MCD_OPC_CheckPredicate, 21, 49, 1, // Skip to: 316
@@ -8844,7 +8844,7 @@
0
};
-static uint8_t DecoderTableVFP32[] = {
+static const uint8_t DecoderTableVFP32[] = {
/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
/* 3 */ MCD_OPC_FilterValue, 0, 83, 1, // Skip to: 346
/* 7 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ...
@@ -9473,7 +9473,7 @@
0
};
-static uint8_t DecoderTableVFPV832[] = {
+static const uint8_t DecoderTableVFPV832[] = {
/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
/* 3 */ MCD_OPC_FilterValue, 0, 160, 0, // Skip to: 167
/* 7 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ...
@@ -9695,7 +9695,7 @@
0
};
-static uint8_t DecoderTablev8Crypto32[] = {
+static const uint8_t DecoderTablev8Crypto32[] = {
/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
/* 3 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 72
/* 7 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ...
@@ -9796,7 +9796,7 @@
0
};
-static uint8_t DecoderTablev8NEON32[] = {
+static const uint8_t DecoderTablev8NEON32[] = {
/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ...
/* 3 */ MCD_OPC_FilterValue, 0, 127, 0, // Skip to: 134
/* 7 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ...
@@ -10134,7 +10134,7 @@
#define DecodeToMCInst(fname,fieldname, InsnType) \
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
- uint64_t Address, void *Decoder) \
+ uint64_t Address, const void *Decoder) \
{ \
InsnType tmp; \
switch (Idx) { \
@@ -13540,11 +13540,11 @@
}
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
- InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
{ \
uint64_t Bits = ARM_getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
+ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0, ExpectedValue; \
DecodeStatus S = MCDisassembler_Success; \
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
diff --git a/arch/ARM/ARMGenInstrInfo.inc b/arch/ARM/ARMGenInstrInfo.inc
index a2d3959..78576d5 100644
--- a/arch/ARM/ARMGenInstrInfo.inc
+++ b/arch/ARM/ARMGenInstrInfo.inc
@@ -2825,21 +2825,21 @@
#define nullptr 0
-#define ImplicitList1 NULL
-#define ImplicitList2 NULL
-#define ImplicitList3 NULL
-#define ImplicitList4 NULL
-#define ImplicitList5 NULL
-#define ImplicitList6 NULL
-#define ImplicitList7 NULL
-#define ImplicitList8 NULL
-#define ImplicitList9 NULL
-#define ImplicitList10 NULL
-#define ImplicitList11 NULL
-#define ImplicitList12 NULL
-#define ImplicitList13 NULL
-#define ImplicitList14 NULL
-#define ImplicitList15 NULL
+#define ImplicitList1 0
+#define ImplicitList2 0
+#define ImplicitList3 0
+#define ImplicitList4 0
+#define ImplicitList5 0
+#define ImplicitList6 0
+#define ImplicitList7 0
+#define ImplicitList8 0
+#define ImplicitList9 0
+#define ImplicitList10 0
+#define ImplicitList11 0
+#define ImplicitList12 0
+#define ImplicitList13 0
+#define ImplicitList14 0
+#define ImplicitList15 0
static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
@@ -3204,7 +3204,7 @@
static MCOperandInfo OperandInfo361[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static MCInstrDesc ARMInsts[] = {
+static const MCInstrDesc ARMInsts[] = {
{ 0, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #0 = PHI
{ 1, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #1 = INLINEASM
{ 2, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #2 = CFI_INSTRUCTION
diff --git a/arch/ARM/ARMGenRegisterInfo.inc b/arch/ARM/ARMGenRegisterInfo.inc
index 1045bb2..9df5ef0 100644
--- a/arch/ARM/ARMGenRegisterInfo.inc
+++ b/arch/ARM/ARMGenRegisterInfo.inc
@@ -489,7 +489,7 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg ARMRegDiffLists[] = {
+static const MCPhysReg ARMRegDiffLists[] = {
/* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
@@ -847,7 +847,7 @@
/* 4184 */ 65535, 0,
};
-static uint16_t ARMSubRegIdxLists[] = {
+static const uint16_t ARMSubRegIdxLists[] = {
/* 0 */ 1, 2, 0,
/* 3 */ 1, 17, 18, 2, 0,
/* 8 */ 1, 3, 0,
@@ -1182,7 +1182,7 @@
};
// SPR Bit set.
- static uint8_t SPRBits[] = {
+ static const uint8_t SPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
};
@@ -1192,7 +1192,7 @@
};
// GPR Bit set.
- static uint8_t GPRBits[] = {
+ static const uint8_t GPRBits[] = {
0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
};
@@ -1202,7 +1202,7 @@
};
// GPRwithAPSR Bit set.
- static uint8_t GPRwithAPSRBits[] = {
+ static const uint8_t GPRwithAPSRBits[] = {
0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
};
@@ -1212,7 +1212,7 @@
};
// SPR_8 Bit set.
- static uint8_t SPR_8Bits[] = {
+ static const uint8_t SPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
@@ -1222,7 +1222,7 @@
};
// GPRnopc Bit set.
- static uint8_t GPRnopcBits[] = {
+ static const uint8_t GPRnopcBits[] = {
0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
};
@@ -1232,7 +1232,7 @@
};
// rGPR Bit set.
- static uint8_t rGPRBits[] = {
+ static const uint8_t rGPRBits[] = {
0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
};
@@ -1242,7 +1242,7 @@
};
// hGPR Bit set.
- static uint8_t hGPRBits[] = {
+ static const uint8_t hGPRBits[] = {
0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
};
@@ -1252,7 +1252,7 @@
};
// tGPR Bit set.
- static uint8_t tGPRBits[] = {
+ static const uint8_t tGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
};
@@ -1262,7 +1262,7 @@
};
// GPRnopc_and_hGPR Bit set.
- static uint8_t GPRnopc_and_hGPRBits[] = {
+ static const uint8_t GPRnopc_and_hGPRBits[] = {
0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
};
@@ -1272,7 +1272,7 @@
};
// hGPR_and_rGPR Bit set.
- static uint8_t hGPR_and_rGPRBits[] = {
+ static const uint8_t hGPR_and_rGPRBits[] = {
0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
};
@@ -1282,7 +1282,7 @@
};
// tcGPR Bit set.
- static uint8_t tcGPRBits[] = {
+ static const uint8_t tcGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
};
@@ -1292,7 +1292,7 @@
};
// tGPR_and_tcGPR Bit set.
- static uint8_t tGPR_and_tcGPRBits[] = {
+ static const uint8_t tGPR_and_tcGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
};
@@ -1302,7 +1302,7 @@
};
// CCR Bit set.
- static uint8_t CCRBits[] = {
+ static const uint8_t CCRBits[] = {
0x08,
};
@@ -1312,7 +1312,7 @@
};
// GPRsp Bit set.
- static uint8_t GPRspBits[] = {
+ static const uint8_t GPRspBits[] = {
0x00, 0x10,
};
@@ -1322,7 +1322,7 @@
};
// hGPR_and_tcGPR Bit set.
- static uint8_t hGPR_and_tcGPRBits[] = {
+ static const uint8_t hGPR_and_tcGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
};
@@ -1332,7 +1332,7 @@
};
// DPR Bit set.
- static uint8_t DPRBits[] = {
+ static const uint8_t DPRBits[] = {
0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
};
@@ -1342,7 +1342,7 @@
};
// DPR_VFP2 Bit set.
- static uint8_t DPR_VFP2Bits[] = {
+ static const uint8_t DPR_VFP2Bits[] = {
0x00, 0xc0, 0xff, 0x3f,
};
@@ -1352,7 +1352,7 @@
};
// DPR_8 Bit set.
- static uint8_t DPR_8Bits[] = {
+ static const uint8_t DPR_8Bits[] = {
0x00, 0xc0, 0x3f,
};
@@ -1362,7 +1362,7 @@
};
// GPRPair Bit set.
- static uint8_t GPRPairBits[] = {
+ static const uint8_t GPRPairBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
@@ -1372,7 +1372,7 @@
};
// GPRPair_with_gsub_1_in_rGPR Bit set.
- static uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
+ static const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
};
@@ -1382,7 +1382,7 @@
};
// GPRPair_with_gsub_0_in_tGPR Bit set.
- static uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
+ static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
};
@@ -1392,7 +1392,7 @@
};
// GPRPair_with_gsub_0_in_hGPR Bit set.
- static uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
+ static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2,
};
@@ -1402,7 +1402,7 @@
};
// GPRPair_with_gsub_0_in_tcGPR Bit set.
- static uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
+ static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
};
@@ -1412,7 +1412,7 @@
};
// GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
- static uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
+ static const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
};
@@ -1422,7 +1422,7 @@
};
// GPRPair_with_gsub_1_in_tcGPR Bit set.
- static uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
+ static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
};
@@ -1432,7 +1432,7 @@
};
// GPRPair_with_gsub_1_in_GPRsp Bit set.
- static uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
+ static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
};
@@ -1442,7 +1442,7 @@
};
// DPairSpc Bit set.
- static uint8_t DPairSpcBits[] = {
+ static const uint8_t DPairSpcBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
};
@@ -1452,7 +1452,7 @@
};
// DPairSpc_with_ssub_0 Bit set.
- static uint8_t DPairSpc_with_ssub_0Bits[] = {
+ static const uint8_t DPairSpc_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
@@ -1462,7 +1462,7 @@
};
// DPairSpc_with_dsub_2_then_ssub_0 Bit set.
- static uint8_t DPairSpc_with_dsub_2_then_ssub_0Bits[] = {
+ static const uint8_t DPairSpc_with_dsub_2_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
};
@@ -1472,7 +1472,7 @@
};
// DPairSpc_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
@@ -1482,7 +1482,7 @@
};
// DPairSpc_with_dsub_2_in_DPR_8 Bit set.
- static uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
+ static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
};
@@ -1492,7 +1492,7 @@
};
// DPair Bit set.
- static uint8_t DPairBits[] = {
+ static const uint8_t DPairBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
};
@@ -1502,7 +1502,7 @@
};
// DPair_with_ssub_0 Bit set.
- static uint8_t DPair_with_ssub_0Bits[] = {
+ static const uint8_t DPair_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
};
@@ -1512,7 +1512,7 @@
};
// QPR Bit set.
- static uint8_t QPRBits[] = {
+ static const uint8_t QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
@@ -1522,7 +1522,7 @@
};
// DPair_with_ssub_2 Bit set.
- static uint8_t DPair_with_ssub_2Bits[] = {
+ static const uint8_t DPair_with_ssub_2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
};
@@ -1532,7 +1532,7 @@
};
// DPair_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
};
@@ -1542,7 +1542,7 @@
};
// QPR_VFP2 Bit set.
- static uint8_t QPR_VFP2Bits[] = {
+ static const uint8_t QPR_VFP2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
};
@@ -1552,7 +1552,7 @@
};
// DPair_with_dsub_1_in_DPR_8 Bit set.
- static uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
+ static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
};
@@ -1562,7 +1562,7 @@
};
// QPR_8 Bit set.
- static uint8_t QPR_8Bits[] = {
+ static const uint8_t QPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
};
@@ -1572,7 +1572,7 @@
};
// DTriple Bit set.
- static uint8_t DTripleBits[] = {
+ static const uint8_t DTripleBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
};
@@ -1582,7 +1582,7 @@
};
// DTripleSpc Bit set.
- static uint8_t DTripleSpcBits[] = {
+ static const uint8_t DTripleSpcBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
};
@@ -1592,7 +1592,7 @@
};
// DTripleSpc_with_ssub_0 Bit set.
- static uint8_t DTripleSpc_with_ssub_0Bits[] = {
+ static const uint8_t DTripleSpc_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
};
@@ -1602,7 +1602,7 @@
};
// DTriple_with_ssub_0 Bit set.
- static uint8_t DTriple_with_ssub_0Bits[] = {
+ static const uint8_t DTriple_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
@@ -1612,7 +1612,7 @@
};
// DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
};
@@ -1622,7 +1622,7 @@
};
// DTriple_with_qsub_0_in_QPR Bit set.
- static uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
+ static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
};
@@ -1632,7 +1632,7 @@
};
// DTriple_with_ssub_2 Bit set.
- static uint8_t DTriple_with_ssub_2Bits[] = {
+ static const uint8_t DTriple_with_ssub_2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
};
@@ -1642,7 +1642,7 @@
};
// DTripleSpc_with_dsub_2_then_ssub_0 Bit set.
- static uint8_t DTripleSpc_with_dsub_2_then_ssub_0Bits[] = {
+ static const uint8_t DTripleSpc_with_dsub_2_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
};
@@ -1652,7 +1652,7 @@
};
// DTriple_with_dsub_2_then_ssub_0 Bit set.
- static uint8_t DTriple_with_dsub_2_then_ssub_0Bits[] = {
+ static const uint8_t DTriple_with_dsub_2_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
};
@@ -1662,7 +1662,7 @@
};
// DTripleSpc_with_dsub_4_then_ssub_0 Bit set.
- static uint8_t DTripleSpc_with_dsub_4_then_ssub_0Bits[] = {
+ static const uint8_t DTripleSpc_with_dsub_4_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
};
@@ -1672,7 +1672,7 @@
};
// DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
};
@@ -1682,7 +1682,7 @@
};
// DTriple_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
@@ -1692,7 +1692,7 @@
};
// DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
- static uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
+ static const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
};
@@ -1702,7 +1702,7 @@
};
// DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
};
@@ -1712,7 +1712,7 @@
};
// DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set.
- static uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = {
+ static const uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
};
@@ -1722,7 +1722,7 @@
};
// DTriple_with_dsub_1_in_DPR_8 Bit set.
- static uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
+ static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
@@ -1732,7 +1732,7 @@
};
// DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Bit set.
- static uint8_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits[] = {
+ static const uint8_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
};
@@ -1742,7 +1742,7 @@
};
// DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
- static uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
+ static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
};
@@ -1752,7 +1752,7 @@
};
// DTriple_with_dsub_2_in_DPR_8 Bit set.
- static uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
+ static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
};
@@ -1762,7 +1762,7 @@
};
// DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
- static uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
+ static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
};
@@ -1772,7 +1772,7 @@
};
// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
};
@@ -1782,7 +1782,7 @@
};
// DTriple_with_qsub_0_in_QPR_8 Bit set.
- static uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
+ static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
};
@@ -1792,7 +1792,7 @@
};
// DTriple_with_dsub_1_dsub_2_in_QPR_8 Bit set.
- static uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_8Bits[] = {
+ static const uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
};
@@ -1802,7 +1802,7 @@
};
// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
- static uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
+ static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
};
@@ -1812,7 +1812,7 @@
};
// DQuadSpc Bit set.
- static uint8_t DQuadSpcBits[] = {
+ static const uint8_t DQuadSpcBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
};
@@ -1822,7 +1822,7 @@
};
// DQuadSpc_with_ssub_0 Bit set.
- static uint8_t DQuadSpc_with_ssub_0Bits[] = {
+ static const uint8_t DQuadSpc_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
};
@@ -1832,7 +1832,7 @@
};
// DQuadSpc_with_dsub_2_then_ssub_0 Bit set.
- static uint8_t DQuadSpc_with_dsub_2_then_ssub_0Bits[] = {
+ static const uint8_t DQuadSpc_with_dsub_2_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
};
@@ -1842,7 +1842,7 @@
};
// DQuadSpc_with_dsub_4_then_ssub_0 Bit set.
- static uint8_t DQuadSpc_with_dsub_4_then_ssub_0Bits[] = {
+ static const uint8_t DQuadSpc_with_dsub_4_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
};
@@ -1852,7 +1852,7 @@
};
// DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
};
@@ -1862,7 +1862,7 @@
};
// DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
- static uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
+ static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
};
@@ -1872,7 +1872,7 @@
};
// DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
- static uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
+ static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
};
@@ -1882,7 +1882,7 @@
};
// DQuad Bit set.
- static uint8_t DQuadBits[] = {
+ static const uint8_t DQuadBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
@@ -1892,7 +1892,7 @@
};
// DQuad_with_ssub_0 Bit set.
- static uint8_t DQuad_with_ssub_0Bits[] = {
+ static const uint8_t DQuad_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
@@ -1902,7 +1902,7 @@
};
// DQuad_with_ssub_2 Bit set.
- static uint8_t DQuad_with_ssub_2Bits[] = {
+ static const uint8_t DQuad_with_ssub_2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
};
@@ -1912,7 +1912,7 @@
};
// QQPR Bit set.
- static uint8_t QQPRBits[] = {
+ static const uint8_t QQPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
};
@@ -1922,7 +1922,7 @@
};
// DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
@@ -1932,7 +1932,7 @@
};
// DQuad_with_dsub_2_then_ssub_0 Bit set.
- static uint8_t DQuad_with_dsub_2_then_ssub_0Bits[] = {
+ static const uint8_t DQuad_with_dsub_2_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
};
@@ -1942,7 +1942,7 @@
};
// DQuad_with_dsub_3_then_ssub_0 Bit set.
- static uint8_t DQuad_with_dsub_3_then_ssub_0Bits[] = {
+ static const uint8_t DQuad_with_dsub_3_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
};
@@ -1952,7 +1952,7 @@
};
// DQuad_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
};
@@ -1962,7 +1962,7 @@
};
// DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
- static uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
+ static const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
};
@@ -1972,7 +1972,7 @@
};
// DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
@@ -1982,7 +1982,7 @@
};
// DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set.
- static uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = {
+ static const uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
};
@@ -1992,7 +1992,7 @@
};
// DQuad_with_dsub_1_in_DPR_8 Bit set.
- static uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
+ static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
};
@@ -2002,7 +2002,7 @@
};
// DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
- static uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
+ static const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
};
@@ -2012,7 +2012,7 @@
};
// DQuad_with_dsub_2_in_DPR_8 Bit set.
- static uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
+ static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
};
@@ -2022,7 +2022,7 @@
};
// DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
};
@@ -2032,7 +2032,7 @@
};
// DQuad_with_dsub_3_in_DPR_8 Bit set.
- static uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
+ static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
};
@@ -2042,7 +2042,7 @@
};
// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
};
@@ -2052,7 +2052,7 @@
};
// DQuad_with_qsub_0_in_QPR_8 Bit set.
- static uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
+ static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
};
@@ -2062,7 +2062,7 @@
};
// DQuad_with_dsub_1_dsub_2_in_QPR_8 Bit set.
- static uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_8Bits[] = {
+ static const uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
};
@@ -2072,7 +2072,7 @@
};
// DQuad_with_qsub_1_in_QPR_8 Bit set.
- static uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
+ static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
};
@@ -2082,7 +2082,7 @@
};
// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
- static uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
+ static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
};
@@ -2092,7 +2092,7 @@
};
// QQQQPR Bit set.
- static uint8_t QQQQPRBits[] = {
+ static const uint8_t QQQQPRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
};
@@ -2102,7 +2102,7 @@
};
// QQQQPR_with_ssub_0 Bit set.
- static uint8_t QQQQPR_with_ssub_0Bits[] = {
+ static const uint8_t QQQQPR_with_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
};
@@ -2112,7 +2112,7 @@
};
// QQQQPR_with_dsub_2_then_ssub_0 Bit set.
- static uint8_t QQQQPR_with_dsub_2_then_ssub_0Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_2_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
};
@@ -2122,7 +2122,7 @@
};
// QQQQPR_with_dsub_5_then_ssub_0 Bit set.
- static uint8_t QQQQPR_with_dsub_5_then_ssub_0Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_5_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
};
@@ -2132,7 +2132,7 @@
};
// QQQQPR_with_dsub_7_then_ssub_0 Bit set.
- static uint8_t QQQQPR_with_dsub_7_then_ssub_0Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_7_then_ssub_0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
};
@@ -2142,7 +2142,7 @@
};
// QQQQPR_with_dsub_0_in_DPR_8 Bit set.
- static uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
};
@@ -2152,7 +2152,7 @@
};
// QQQQPR_with_dsub_2_in_DPR_8 Bit set.
- static uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
};
@@ -2162,7 +2162,7 @@
};
// QQQQPR_with_dsub_4_in_DPR_8 Bit set.
- static uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
};
@@ -2172,7 +2172,7 @@
};
// QQQQPR_with_dsub_6_in_DPR_8 Bit set.
- static uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
+ static const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index 94e21d2..fbc89b4 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -236,7 +236,7 @@
#endif
}
-static name_map insn_update_flgs[] = {
+static const name_map insn_update_flgs[] = {
{ ARM_INS_CMN, "cmn" },
{ ARM_INS_CMP, "cmp" },
{ ARM_INS_TEQ, "teq" },
@@ -587,10 +587,7 @@
SStream_concat0(O, ", ");
tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
- if (tmp > HEX_THRESHOLD)
- SStream_concat(O, "#0x%x", tmp);
- else
- SStream_concat(O, "#%u", tmp);
+ printUInt32Bang(O, tmp);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
(arm_shifter)opc;
@@ -770,7 +767,7 @@
case ARM_STREXD:
case ARM_LDAEXD:
case ARM_STLEXD: {
- MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
+ const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
@@ -864,13 +861,15 @@
address = (uint32_t)MI->address + 4;
if (ARM_blx_to_arm_mode(MI->csh, opc)) {
// here need to align down to the nearest 4-byte address
- address &= ~3;
+#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
+ address = _ALIGN_DOWN(address, 4);
+#undef _ALIGN_DOWN
}
} else {
address = (uint32_t)MI->address + 8;
}
- imm = address + imm;
+ imm += address;
printUInt32Bang(O, imm);
} else {
switch(MI->flat_insn->id) {
@@ -1602,7 +1601,7 @@
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
- unsigned Mask = MCOperand_getImm(Op) & 0xf;
+ unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf;
unsigned reg;
uint64_t FeatureBits = ARM_getFeatureBits(MI->csh->mode);
@@ -1729,7 +1728,7 @@
uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
uint32_t R = (Banked & 0x20) >> 5;
uint32_t SysM = Banked & 0x1f;
- char *RegNames[] = {
+ const char *RegNames[] = {
"r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "",
"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "",
"lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und",
@@ -1746,7 +1745,7 @@
ARM_SYSREG_SP_UND, 0, 0, 0, 0, ARM_SYSREG_LR_MON, ARM_SYSREG_SP_MON,
ARM_SYSREG_ELR_HYP, ARM_SYSREG_SP_HYP,
};
- char *Name = RegNames[SysM];
+ const char *Name = RegNames[SysM];
// Nothing much we can do about this, the encodings are specified in B9.2.3 of
// the ARM ARM v7C, and are all over the shop.
@@ -1812,10 +1811,7 @@
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
- if (tmp > HEX_THRESHOLD)
- SStream_concat(O, "0x%x", tmp);
- else
- SStream_concat(O, "%u", tmp);
+ printUInt32(O, tmp);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm.op_count--;
@@ -2266,7 +2262,8 @@
SStream_concat0(O, ", lsl ");
SStream_concat(O, "#%d", ShAmt);
if (MI->csh->detail) {
- MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = ShAmt;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt;
}
}
@@ -2277,7 +2274,13 @@
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+#if defined(_KERNEL_MODE)
+ // Issue #681: Windows kernel does not support formatting float point
+ SStream_concat(O, "#<float_point_unsupported>");
+#else
SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
+#endif
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
@@ -2304,10 +2307,7 @@
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
- if (Imm + 1 > HEX_THRESHOLD)
- SStream_concat(O, "#0x%x", Imm + 1);
- else
- SStream_concat(O, "#%u", Imm + 1);
+ printUInt32Bang(O, Imm + 1);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c
index 600cc62..7689839 100644
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@@ -14,7 +14,7 @@
#include "ARMGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ ARM_REG_INVALID, NULL },
{ ARM_REG_APSR, "apsr"},
{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
@@ -127,7 +127,7 @@
{ ARM_REG_S30, "s30"},
{ ARM_REG_S31, "s31"},
};
-static name_map reg_name_maps2[] = {
+static const name_map reg_name_maps2[] = {
{ ARM_REG_INVALID, NULL },
{ ARM_REG_APSR, "apsr"},
{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
@@ -266,7 +266,7 @@
#endif
}
-static insn_map insns[] = {
+static const insn_map insns[] = {
// dummy item
{
0, 0,
@@ -312,7 +312,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ ARM_INS_INVALID, NULL },
{ ARM_INS_ADC, "adc" },
@@ -765,7 +765,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ ARM_GRP_INVALID, NULL },
{ ARM_GRP_JUMP, "jump" },
@@ -821,7 +821,7 @@
// list all relative branch instructions
// ie: insns[i].branch && !insns[i].indirect_branch
-static unsigned int insn_rel[] = {
+static const unsigned int insn_rel[] = {
ARM_BL,
ARM_BLX_pred,
ARM_Bcc,
@@ -838,7 +838,7 @@
0
};
-static unsigned int insn_blx_rel_to_arm[] = {
+static const unsigned int insn_blx_rel_to_arm[] = {
ARM_tBLXi,
0
};
diff --git a/arch/M680X/M680XInstPrinter.c b/arch/M680X/M680XInstPrinter.c
index 34a8836..8373e8a 100644
--- a/arch/M680X/M680XInstPrinter.c
+++ b/arch/M680X/M680XInstPrinter.c
@@ -138,7 +138,7 @@
if ((!isPost && !(op->idx.flags & M680X_IDX_POST_INC_DEC)) ||
(isPost && (op->idx.flags & M680X_IDX_POST_INC_DEC))) {
- char *prePostfix = "";
+ const char *prePostfix = "";
if (info->cpu_type == M680X_CPU_TYPE_CPU12)
prePostfix = (op->idx.inc_dec < 0) ? "-" : "+";
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index 5ff97a6..7f1211e 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -41,10 +41,10 @@
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
@@ -56,76 +56,76 @@
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
@@ -140,15 +140,15 @@
// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
// DecodeJumpTargetMM - Decode microMIPS jump target, which is
// shifted left by 1 bit.
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMem(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeCacheOp(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
@@ -163,7 +163,7 @@
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
@@ -178,13 +178,13 @@
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
- uint64_t Address, MCRegisterInfo *Decoder);
+ uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn,
uint64_t Address, MCRegisterInfo *Decoder);
@@ -196,7 +196,7 @@
uint64_t Address, MCRegisterInfo *Decoder);
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
@@ -211,24 +211,24 @@
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
static DecodeStatus DecodeSimm16(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
// Decode the immediate field of an LSA instruction which
// is off by one.
static DecodeStatus DecodeLSAImm(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeInsSize(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeExtSize(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeSimm9SP(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
@@ -245,28 +245,28 @@
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
/// handle.
static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeRegListOperand(MCInst *Inst,
- uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
static DecodeStatus DecodeRegListOperand16(MCInst *Inst,
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
@@ -514,16 +514,16 @@
return status == MCDisassembler_Success;
}
-static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
{
- MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+ const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
return rc->RegsBegin[RegNo];
}
static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
- typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, MCRegisterInfo *);
+ typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *);
// The size of the n field depends on the element size
// The register class also depends on this.
uint32_t tmp = fieldFromInstruction(insn, 17, 5);
@@ -573,7 +573,7 @@
}
static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the ADDI instruction from the earlier
@@ -609,7 +609,7 @@
}
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the ADDI instruction from the earlier
@@ -645,7 +645,7 @@
}
static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BLEZL instruction from the earlier
@@ -685,7 +685,7 @@
}
static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BGTZL instruction from the earlier
@@ -725,7 +725,7 @@
}
static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BGTZ instruction from the earlier
@@ -771,7 +771,7 @@
}
static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the BLEZL instruction from the earlier
@@ -811,13 +811,13 @@
}
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
return MCDisassembler_Fail;
}
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -869,7 +869,7 @@
}
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -882,7 +882,7 @@
}
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
// if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
if (Inst->csh->mode & CS_MODE_MIPS64)
@@ -892,13 +892,13 @@
}
static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -911,7 +911,7 @@
}
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -924,7 +924,7 @@
}
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -937,7 +937,7 @@
}
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -950,7 +950,7 @@
}
static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -963,7 +963,7 @@
}
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -976,7 +976,7 @@
}
static DecodeStatus DecodeMem(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
int Offset = SignExtend32(Insn & 0xffff, 16);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
@@ -1060,7 +1060,7 @@
}
static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10);
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
@@ -1202,7 +1202,7 @@
}
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
int Offset = SignExtend32(Insn & 0x0fff, 12);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
@@ -1236,7 +1236,7 @@
}
static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
int Offset = SignExtend32(Insn & 0xffff, 16);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
@@ -1253,7 +1253,7 @@
}
static DecodeStatus DecodeFMem(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
int Offset = SignExtend32(Insn & 0xffff, 16);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
@@ -1321,7 +1321,7 @@
}
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
unsigned Rt = fieldFromInstruction(Insn, 16, 5);
@@ -1343,7 +1343,7 @@
}
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
// Currently only hardware register 29 is supported.
if (RegNo != 29)
@@ -1355,7 +1355,7 @@
}
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1369,7 +1369,7 @@
}
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1382,7 +1382,7 @@
}
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1396,7 +1396,7 @@
}
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1410,7 +1410,7 @@
}
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1424,7 +1424,7 @@
}
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1438,7 +1438,7 @@
}
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1452,7 +1452,7 @@
}
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1466,7 +1466,7 @@
}
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1480,7 +1480,7 @@
}
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
- unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Reg;
@@ -1494,7 +1494,7 @@
}
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
{
uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
MCOperand_CreateImm0(Inst, TargetAddress);
@@ -1503,7 +1503,7 @@
}
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
MCOperand_CreateImm0(Inst, TargetAddress);
@@ -1512,7 +1512,7 @@
}
static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
{
int32_t BranchOffset = SignExtend32(Offset, 21) * 4;
@@ -1522,7 +1522,7 @@
}
static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
{
int32_t BranchOffset = SignExtend32(Offset, 26) * 4;
@@ -1547,7 +1547,7 @@
}
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
- unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
{
int32_t BranchOffset = SignExtend32(Offset, 16) * 2;
MCOperand_CreateImm0(Inst, BranchOffset);
@@ -1556,7 +1556,7 @@
}
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
MCOperand_CreateImm0(Inst, JumpOffset);
@@ -1605,7 +1605,7 @@
}
static DecodeStatus DecodeSimm16(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
@@ -1613,7 +1613,7 @@
}
static DecodeStatus DecodeLSAImm(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
// We add one to the immediate field as it was encoded as 'imm - 1'.
MCOperand_CreateImm0(Inst, Insn + 1);
@@ -1622,7 +1622,7 @@
}
static DecodeStatus DecodeInsSize(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
// First we need to grab the pos(lsb) from MCInst.
int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
@@ -1633,7 +1633,7 @@
}
static DecodeStatus DecodeExtSize(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
int Size = (int)Insn + 1;
@@ -1643,7 +1643,7 @@
}
static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
@@ -1651,7 +1651,7 @@
}
static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
- unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
{
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
@@ -1700,7 +1700,7 @@
}
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn,
- uint64_t Address, MCRegisterInfo *Decoder)
+ uint64_t Address, const MCRegisterInfo *Decoder)
{
unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5,
Mips_S6, Mips_FP};
diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc
index e707560..cd25213 100644
--- a/arch/Mips/MipsGenAsmWriter.inc
+++ b/arch/Mips/MipsGenAsmWriter.inc
@@ -11,7 +11,7 @@
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
-static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
{
static const uint32_t OpInfo[] = {
0U, // PHI
@@ -3592,7 +3592,7 @@
};
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0,
/* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0,
/* 15 */ 'd', 'm', 't', 'c', '0', 9, 0,
@@ -5095,12 +5095,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 394 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'f', '1', '0', 0,
/* 4 */ 'w', '1', '0', 0,
/* 8 */ 'f', '2', '0', 0,
diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc
index 85532cd..5013293 100644
--- a/arch/Mips/MipsGenDisassemblerTables.inc
+++ b/arch/Mips/MipsGenDisassemblerTables.inc
@@ -185,7 +185,7 @@
0
};
-static uint8_t DecoderTableMicroMips32[] = {
+static const uint8_t DecoderTableMicroMips32[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
@@ -598,7 +598,7 @@
0
};
-static uint8_t DecoderTableMips32[] = {
+static const uint8_t DecoderTableMips32[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
@@ -3823,7 +3823,7 @@
0
};
-static uint8_t DecoderTableMips32r6_64r632[] = {
+static const uint8_t DecoderTableMips32r6_64r632[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
@@ -4260,7 +4260,7 @@
0
};
-static uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
+static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22
/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41
@@ -4274,7 +4274,7 @@
0
};
-static uint8_t DecoderTableMips6432[] = {
+static const uint8_t DecoderTableMips6432[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
@@ -6859,11 +6859,11 @@
}
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
{ \
uint64_t Bits = getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
+ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0, ExpectedValue; \
DecodeStatus S = MCDisassembler_Success; \
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c
index e97bf4d..9bbf4bc 100644
--- a/arch/Mips/MipsInstPrinter.c
+++ b/arch/Mips/MipsInstPrinter.c
@@ -82,8 +82,8 @@
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
-static char *getRegisterName(unsigned RegNo);
-static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
+static const char *getRegisterName(unsigned RegNo);
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
static void set_mem_access(MCInst *MI, bool status)
{
@@ -108,7 +108,7 @@
MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
}
-static char* MipsFCCToString(Mips_CondCode CC)
+static const char* MipsFCCToString(Mips_CondCode CC)
{
switch (CC) {
default: return 0; // never reach
@@ -206,32 +206,12 @@
int64_t imm = MCOperand_getImm(Op);
if (MI->csh->doing_mem) {
if (imm) { // only print Imm offset if it is not 0
- if (imm >= 0) {
- if (imm > HEX_THRESHOLD)
- SStream_concat(O, "0x%"PRIx64, imm);
- else
- SStream_concat(O, "%"PRIu64, imm);
- } else {
- if (imm < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%"PRIx64, -imm);
- else
- SStream_concat(O, "-%"PRIu64, -imm);
- }
+ printInt64(O, imm);
}
if (MI->csh->detail)
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
} else {
- if (imm >= 0) {
- if (imm > HEX_THRESHOLD)
- SStream_concat(O, "0x%"PRIx64, imm);
- else
- SStream_concat(O, "%"PRIu64, imm);
- } else {
- if (imm < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%"PRIx64, -imm);
- else
- SStream_concat(O, "-%"PRIu64, -imm);
- }
+ printInt64(O, imm);
if (MI->csh->detail) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
@@ -247,17 +227,8 @@
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isImm(MO)) {
int64_t imm = MCOperand_getImm(MO);
- if (imm >= 0) {
- if (imm > HEX_THRESHOLD)
- SStream_concat(O, "0x%x", (unsigned short int)imm);
- else
- SStream_concat(O, "%u", (unsigned short int)imm);
- } else {
- if (imm < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%x", (short int)-imm);
- else
- SStream_concat(O, "-%u", (short int)-imm);
- }
+ printInt64(O, imm);
+
if (MI->csh->detail) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
@@ -334,14 +305,14 @@
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
}
-static char *printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
+static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
{
SStream_concat(OS, "%s\t", Str);
printOperand(MI, OpNo, OS);
return cs_strdup(Str);
}
-static char *printAlias2(char *Str, MCInst *MI,
+static char *printAlias2(const char *Str, MCInst *MI,
unsigned OpNo0, unsigned OpNo1, SStream *OS)
{
char *tmp;
diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c
index c58c9d1..01cfbc5 100644
--- a/arch/Mips/MipsMapping.c
+++ b/arch/Mips/MipsMapping.c
@@ -14,7 +14,7 @@
#include "MipsGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ MIPS_REG_INVALID, NULL },
{ MIPS_REG_PC, "pc"},
@@ -252,7 +252,7 @@
}
}
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ MIPS_INS_INVALID, NULL },
{ MIPS_INS_ABSQ_S, "absq_s" },
@@ -898,7 +898,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ MIPS_GRP_INVALID, NULL },
{ MIPS_GRP_JUMP, "jump" },
@@ -978,7 +978,7 @@
// for some reasons different Mips modes can map different register number to
// the same Mips register. this function handles the issue for exposing Mips
// operands by mapping internal registers to 'public' register.
- unsigned int map[] = { 0,
+ static const unsigned int map[] = { 0,
MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG,
MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2,
MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5,
diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c
index cec635b..e06871d 100644
--- a/arch/Mips/MipsModule.c
+++ b/arch/Mips/MipsModule.c
@@ -20,7 +20,6 @@
return mode;
}
-
cs_err Mips_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
diff --git a/arch/PowerPC/PPCGenAsmWriter.inc b/arch/PowerPC/PPCGenAsmWriter.inc
index 447bd04..7f71039 100644
--- a/arch/PowerPC/PPCGenAsmWriter.inc
+++ b/arch/PowerPC/PPCGenAsmWriter.inc
@@ -14,7 +14,7 @@
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
-static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
{
static const uint32_t OpInfo[] = {
0U, // PHI
@@ -3061,7 +3061,7 @@
};
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0,
/* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0,
/* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0,
@@ -4698,11 +4698,11 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 310 && "Invalid register number!");
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0,
/* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
/* 36 */ '*', '*', 'B', 'A', 'S', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
diff --git a/arch/PowerPC/PPCGenDisassemblerTables.inc b/arch/PowerPC/PPCGenDisassemblerTables.inc
index 1bfda9a..cd34bbd 100644
--- a/arch/PowerPC/PPCGenDisassemblerTables.inc
+++ b/arch/PowerPC/PPCGenDisassemblerTables.inc
@@ -28,7 +28,7 @@
// FieldFromInstruction(fieldFromInstruction_2, uint16_t)
FieldFromInstruction(fieldFromInstruction_4, uint32_t)
-static uint8_t DecoderTable32[] = {
+static const uint8_t DecoderTable32[] = {
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
/* 3 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 17
/* 7 */ MCD_OPC_CheckField, 1, 10, 128, 2, 231, 38, // Skip to: 9973
diff --git a/arch/PowerPC/PPCGenRegisterInfo.inc b/arch/PowerPC/PPCGenRegisterInfo.inc
index 6122321..d05d658 100644
--- a/arch/PowerPC/PPCGenRegisterInfo.inc
+++ b/arch/PowerPC/PPCGenRegisterInfo.inc
@@ -368,7 +368,7 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg PPCRegDiffLists[] = {
+static const MCPhysReg PPCRegDiffLists[] = {
/* 0 */ 0, 0,
/* 2 */ 65504, 1, 1, 1, 0,
/* 7 */ 3, 0,
@@ -405,7 +405,7 @@
/* 75 */ 65535, 0,
};
-static uint16_t PPCSubRegIdxLists[] = {
+static const uint16_t PPCSubRegIdxLists[] = {
/* 0 */ 1, 0,
/* 2 */ 3, 2, 0,
/* 5 */ 6, 5, 4, 7, 0,
@@ -726,7 +726,7 @@
// GPRC Register Class...
- static MCPhysReg GPRC[] = {
+ static const MCPhysReg GPRC[] = {
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP,
};
@@ -736,7 +736,7 @@
};
// GPRC_NOR0 Register Class...
- static MCPhysReg GPRC_NOR0[] = {
+ static const MCPhysReg GPRC_NOR0[] = {
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO,
};
@@ -746,7 +746,7 @@
};
// GPRC_and_GPRC_NOR0 Register Class...
- static MCPhysReg GPRC_and_GPRC_NOR0[] = {
+ static const MCPhysReg GPRC_and_GPRC_NOR0[] = {
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP,
};
@@ -756,7 +756,7 @@
};
// CRBITRC Register Class...
- static MCPhysReg CRBITRC[] = {
+ static const MCPhysReg CRBITRC[] = {
PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
};
@@ -766,7 +766,7 @@
};
// F4RC Register Class...
- static MCPhysReg F4RC[] = {
+ static const MCPhysReg F4RC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14,
};
@@ -776,7 +776,7 @@
};
// CRRC Register Class...
- static MCPhysReg CRRC[] = {
+ static const MCPhysReg CRRC[] = {
PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4,
};
@@ -786,17 +786,17 @@
};
// CARRYRC Register Class...
- static MCPhysReg CARRYRC[] = {
+ static const MCPhysReg CARRYRC[] = {
PPC_CARRY,
};
// CARRYRC Bit set.
- static uint8_t CARRYRCBits[] = {
+ static const uint8_t CARRYRCBits[] = {
0x04,
};
// CTRRC Register Class...
- static MCPhysReg CTRRC[] = {
+ static const MCPhysReg CTRRC[] = {
PPC_CTR,
};
@@ -806,7 +806,7 @@
};
// VRSAVERC Register Class...
- static MCPhysReg VRSAVERC[] = {
+ static const MCPhysReg VRSAVERC[] = {
PPC_VRSAVE,
};
@@ -816,7 +816,7 @@
};
// VSFRC Register Class...
- static MCPhysReg VSFRC[] = {
+ static const MCPhysReg VSFRC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
};
@@ -826,7 +826,7 @@
};
// G8RC Register Class...
- static MCPhysReg G8RC[] = {
+ static const MCPhysReg G8RC[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8,
};
@@ -836,7 +836,7 @@
};
// G8RC_NOX0 Register Class...
- static MCPhysReg G8RC_NOX0[] = {
+ static const MCPhysReg G8RC_NOX0[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8,
};
@@ -846,7 +846,7 @@
};
// G8RC_and_G8RC_NOX0 Register Class...
- static MCPhysReg G8RC_and_G8RC_NOX0[] = {
+ static const MCPhysReg G8RC_and_G8RC_NOX0[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8,
};
@@ -856,7 +856,7 @@
};
// F8RC Register Class...
- static MCPhysReg F8RC[] = {
+ static const MCPhysReg F8RC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14,
};
@@ -866,7 +866,7 @@
};
// VFRC Register Class...
- static MCPhysReg VFRC[] = {
+ static const MCPhysReg VFRC[] = {
PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
};
@@ -876,7 +876,7 @@
};
// CTRRC8 Register Class...
- static MCPhysReg CTRRC8[] = {
+ static const MCPhysReg CTRRC8[] = {
PPC_CTR8,
};
@@ -886,7 +886,7 @@
};
// VSRC Register Class...
- static MCPhysReg VSRC[] = {
+ static const MCPhysReg VSRC[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20,
};
@@ -906,7 +906,7 @@
};
// VRRC Register Class...
- static MCPhysReg VRRC[] = {
+ static const MCPhysReg VRRC[] = {
PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20,
};
@@ -916,7 +916,7 @@
};
// VSHRC Register Class...
- static MCPhysReg VSHRC[] = {
+ static const MCPhysReg VSHRC[] = {
PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20,
};
@@ -926,7 +926,7 @@
};
// VSLRC Register Class...
- static MCPhysReg VSLRC[] = {
+ static const MCPhysReg VSLRC[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14,
};
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index be1f95b..df15aef 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -30,11 +30,11 @@
#include "PPCMapping.h"
#ifndef CAPSTONE_DIET
-static char *getRegisterName(unsigned RegNo);
+static const char *getRegisterName(unsigned RegNo);
#endif
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
-static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info);
@@ -404,17 +404,7 @@
int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
Value = SignExtend32(Value, 5);
- if (Value >= 0) {
- if (Value > HEX_THRESHOLD)
- SStream_concat(O, "0x%x", Value);
- else
- SStream_concat(O, "%u", Value);
- } else {
- if (Value < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%x", -Value);
- else
- SStream_concat(O, "-%u", -Value);
- }
+ printInt32(O, Value);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
@@ -427,10 +417,7 @@
{
unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 31 && "Invalid u5imm argument!");
- if (Value > HEX_THRESHOLD)
- SStream_concat(O, "0x%x", Value);
- else
- SStream_concat(O, "%u", Value);
+ printUInt32(O, Value);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
@@ -443,10 +430,7 @@
{
unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 63 && "Invalid u6imm argument!");
- if (Value > HEX_THRESHOLD)
- SStream_concat(O, "0x%x", Value);
- else
- SStream_concat(O, "%u", Value);
+ printUInt32(O, Value);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
@@ -658,7 +642,7 @@
#ifndef CAPSTONE_DIET
/// stripRegisterPrefix - This method strips the character prefix from a
/// register name so that only the number is left. Used by for linux asm.
-static char *stripRegisterPrefix(char *RegName)
+static const char *stripRegisterPrefix(const char *RegName)
{
switch (RegName[0]) {
case 'r':
@@ -683,7 +667,7 @@
if (MCOperand_isReg(Op)) {
unsigned reg = MCOperand_getReg(Op);
#ifndef CAPSTONE_DIET
- char *RegName = getRegisterName(reg);
+ const char *RegName = getRegisterName(reg);
#endif
// map to public register
reg = PPC_map_register(reg);
@@ -709,18 +693,8 @@
}
if (MCOperand_isImm(Op)) {
- int64_t imm = MCOperand_getImm(Op);
- if (imm >= 0) {
- if (imm > HEX_THRESHOLD)
- SStream_concat(O, "0x%" PRIx64, imm);
- else
- SStream_concat(O, "%" PRIu64 , imm);
- } else {
- if (imm < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%" PRIx64 , -imm);
- else
- SStream_concat(O, "-%" PRIu64 , -imm);
- }
+ int32_t imm = (int32_t)MCOperand_getImm(Op);
+ printInt32(O, imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c
index 085d85f..2b2d24c 100644
--- a/arch/PowerPC/PPCMapping.c
+++ b/arch/PowerPC/PPCMapping.c
@@ -14,7 +14,7 @@
#include "PPCGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ PPC_REG_INVALID, NULL },
{ PPC_REG_CARRY, "ca" },
@@ -243,7 +243,7 @@
#endif
}
-static insn_map insns[] = {
+static const insn_map insns[] = {
// dummy item
{
0, 0,
@@ -291,7 +291,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ PPC_INS_INVALID, NULL },
{ PPC_INS_ADD, "add" },
@@ -1410,7 +1410,7 @@
};
// special alias insn
-static name_map alias_insn_names[] = {
+static const name_map alias_insn_names[] = {
{ 0, NULL }
};
#endif
@@ -1436,7 +1436,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ PPC_GRP_INVALID, NULL },
{ PPC_GRP_JUMP, "jump" },
@@ -1542,7 +1542,7 @@
return 0;
}
-static struct ppc_alias alias_insn_name_maps[] = {
+static const struct ppc_alias alias_insn_name_maps[] = {
//{ PPC_INS_BTA, "bta" },
{ PPC_INS_B, PPC_BC_LT, "blt" },
{ PPC_INS_B, PPC_BC_LE, "ble" },
@@ -1664,7 +1664,7 @@
}
// list all relative branch instructions
-static unsigned int insn_abs[] = {
+static const unsigned int insn_abs[] = {
PPC_BA,
PPC_BCCA,
PPC_BCCLA,
diff --git a/arch/Sparc/Sparc.h b/arch/Sparc/Sparc.h
index bfd8200..1f77362 100644
--- a/arch/Sparc/Sparc.h
+++ b/arch/Sparc/Sparc.h
@@ -20,7 +20,7 @@
#include "capstone/sparc.h"
-inline static char *SPARCCondCodeToString(sparc_cc CC)
+inline static const char *SPARCCondCodeToString(sparc_cc CC)
{
switch (CC) {
default: return NULL; // unreachable
diff --git a/arch/Sparc/SparcGenAsmWriter.inc b/arch/Sparc/SparcGenAsmWriter.inc
index 9ed9760..d290d3b 100644
--- a/arch/Sparc/SparcGenAsmWriter.inc
+++ b/arch/Sparc/SparcGenAsmWriter.inc
@@ -15,7 +15,7 @@
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
-static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
{
static const uint32_t OpInfo[] = {
0U, // PHI
@@ -516,7 +516,7 @@
};
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
/* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
/* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
@@ -1092,12 +1092,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 119 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'f', '1', '0', 0,
/* 4 */ 'f', '2', '0', 0,
/* 8 */ 'f', '3', '0', 0,
diff --git a/arch/Sparc/SparcGenDisassemblerTables.inc b/arch/Sparc/SparcGenDisassemblerTables.inc
index 7e8e0d9..8a69a13 100644
--- a/arch/Sparc/SparcGenDisassemblerTables.inc
+++ b/arch/Sparc/SparcGenDisassemblerTables.inc
@@ -24,7 +24,7 @@
return (insn & fieldMask) >> startBit; \
}
-static uint8_t DecoderTableSparc32[] = {
+static const uint8_t DecoderTableSparc32[] = {
/* 0 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ...
/* 3 */ MCD_OPC_FilterValue, 0, 13, 2, // Skip to: 532
/* 7 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ...
@@ -1455,7 +1455,7 @@
#define DecodeToMCInst(fname,fieldname, InsnType) \
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
- uint64_t Address, void *Decoder) \
+ uint64_t Address, const void *Decoder) \
{ \
InsnType tmp; \
switch (Idx) { \
@@ -1945,11 +1945,11 @@
}
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
- InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
{ \
uint64_t Bits = getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
+ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0, ExpectedValue; \
DecodeStatus S = MCDisassembler_Success; \
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
diff --git a/arch/Sparc/SparcGenRegisterInfo.inc b/arch/Sparc/SparcGenRegisterInfo.inc
index c8b2c1c..a59c852 100644
--- a/arch/Sparc/SparcGenRegisterInfo.inc
+++ b/arch/Sparc/SparcGenRegisterInfo.inc
@@ -162,7 +162,7 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg SparcRegDiffLists[] = {
+static const MCPhysReg SparcRegDiffLists[] = {
/* 0 */ 65126, 1, 1, 1, 0,
/* 5 */ 32, 1, 0,
/* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
@@ -229,7 +229,7 @@
/* 212 */ 65535, 0,
};
-static uint16_t SparcSubRegIdxLists[] = {
+static const uint16_t SparcSubRegIdxLists[] = {
/* 0 */ 1, 3, 0,
/* 3 */ 2, 4, 0,
/* 6 */ 2, 1, 3, 4, 5, 6, 0,
@@ -358,82 +358,82 @@
};
// FCCRegs Register Class...
- static MCPhysReg FCCRegs[] = {
+ static const MCPhysReg FCCRegs[] = {
SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3,
};
// FCCRegs Bit set.
- static uint8_t FCCRegsBits[] = {
+ static const uint8_t FCCRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
};
// FPRegs Register Class...
- static MCPhysReg FPRegs[] = {
+ static const MCPhysReg FPRegs[] = {
SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31,
};
// FPRegs Bit set.
- static uint8_t FPRegsBits[] = {
+ static const uint8_t FPRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// IntRegs Register Class...
- static MCPhysReg IntRegs[] = {
+ static const MCPhysReg IntRegs[] = {
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
};
// IntRegs Bit set.
- static uint8_t IntRegsBits[] = {
+ static const uint8_t IntRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
};
// DFPRegs Register Class...
- static MCPhysReg DFPRegs[] = {
+ static const MCPhysReg DFPRegs[] = {
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31,
};
// DFPRegs Bit set.
- static uint8_t DFPRegsBits[] = {
+ static const uint8_t DFPRegsBits[] = {
0xf8, 0xff, 0xff, 0xff, 0x07,
};
// I64Regs Register Class...
- static MCPhysReg I64Regs[] = {
+ static const MCPhysReg I64Regs[] = {
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
};
// I64Regs Bit set.
- static uint8_t I64RegsBits[] = {
+ static const uint8_t I64RegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
};
// DFPRegs_with_sub_even Register Class...
- static MCPhysReg DFPRegs_with_sub_even[] = {
+ static const MCPhysReg DFPRegs_with_sub_even[] = {
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15,
};
// DFPRegs_with_sub_even Bit set.
- static uint8_t DFPRegs_with_sub_evenBits[] = {
+ static const uint8_t DFPRegs_with_sub_evenBits[] = {
0xf8, 0xff, 0x07,
};
// QFPRegs Register Class...
- static MCPhysReg QFPRegs[] = {
+ static const MCPhysReg QFPRegs[] = {
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15,
};
// QFPRegs Bit set.
- static uint8_t QFPRegsBits[] = {
+ static const uint8_t QFPRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
};
// QFPRegs_with_sub_even Register Class...
- static MCPhysReg QFPRegs_with_sub_even[] = {
+ static const MCPhysReg QFPRegs_with_sub_even[] = {
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7,
};
// QFPRegs_with_sub_even Bit set.
- static uint8_t QFPRegs_with_sub_evenBits[] = {
+ static const uint8_t QFPRegs_with_sub_evenBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
};
diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c
index b080408..4947c9f 100644
--- a/arch/Sparc/SparcInstPrinter.c
+++ b/arch/Sparc/SparcInstPrinter.c
@@ -27,6 +27,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <limits.h>
#include "SparcInstPrinter.h"
#include "../../MCInst.h"
@@ -38,8 +39,8 @@
#include "Sparc.h"
-static char *getRegisterName(unsigned RegNo);
-static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
+static const char *getRegisterName(unsigned RegNo);
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
static void printOperand(MCInst *MI, int opNum, SStream *O);
@@ -261,6 +262,8 @@
Imm = MI->address + Imm * 4;
break;
}
+
+ printInt32(O, Imm);
printInt64(O, Imm);
diff --git a/arch/Sparc/SparcMapping.c b/arch/Sparc/SparcMapping.c
index 0f70ff0..35c911e 100644
--- a/arch/Sparc/SparcMapping.c
+++ b/arch/Sparc/SparcMapping.c
@@ -14,7 +14,7 @@
#include "SparcGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ SPARC_REG_INVALID, NULL },
{ SPARC_REG_F0, "f0"},
@@ -121,7 +121,7 @@
#endif
}
-static insn_map insns[] = {
+static const insn_map insns[] = {
// dummy item
{
0, 0,
@@ -136,7 +136,7 @@
static struct hint_map {
unsigned int id;
uint8_t hints;
-} insn_hints[] = {
+} const insn_hints[] = {
{ SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN },
{ SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT },
{ SP_BPGEZnapn, SPARC_HINT_PN },
@@ -194,7 +194,7 @@
}
}
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ SPARC_INS_INVALID, NULL },
{ SPARC_INS_ADDCC, "addcc" },
@@ -481,7 +481,7 @@
#ifndef CAPSTONE_DIET
// special alias insn
-static name_map alias_insn_names[] = {
+static const name_map alias_insn_names[] = {
{ 0, NULL }
};
#endif
@@ -507,7 +507,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ SPARC_GRP_INVALID, NULL },
{ SPARC_GRP_JUMP, "jump" },
@@ -535,7 +535,7 @@
// map internal raw register to 'public' register
sparc_reg Sparc_map_register(unsigned int r)
{
- static unsigned int map[] = { 0,
+ static const unsigned int map[] = { 0,
SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4,
SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14,
SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24,
@@ -582,7 +582,7 @@
// NOTE: put strings in the order of string length since
// we are going to compare with mnemonic to find out CC
-static name_map alias_icc_maps[] = {
+static const name_map alias_icc_maps[] = {
{ SPARC_CC_ICC_LEU, "leu" },
{ SPARC_CC_ICC_POS, "pos" },
{ SPARC_CC_ICC_NEG, "neg" },
@@ -601,7 +601,7 @@
{ SPARC_CC_ICC_L, "l" },
};
-static name_map alias_fcc_maps[] = {
+static const name_map alias_fcc_maps[] = {
{ SPARC_CC_FCC_UGE, "uge" },
{ SPARC_CC_FCC_ULE, "ule" },
{ SPARC_CC_FCC_UG, "ug" },
@@ -639,7 +639,7 @@
return (i != -1)? i : SPARC_CC_INVALID;
}
-static name_map hint_maps[] = {
+static const name_map hint_maps[] = {
{ SPARC_HINT_A, ",a" },
{ SPARC_HINT_A | SPARC_HINT_PN, ",a,pn" },
{ SPARC_HINT_PN, ",pn" },
diff --git a/arch/SystemZ/SystemZDisassembler.c b/arch/SystemZ/SystemZDisassembler.c
index e9db9ec..954c4c7 100644
--- a/arch/SystemZ/SystemZDisassembler.c
+++ b/arch/SystemZ/SystemZDisassembler.c
@@ -301,7 +301,7 @@
uint16_t *size, uint64_t address, void *info)
{
uint64_t Inst;
- uint8_t *Table;
+ const uint8_t *Table;
uint16_t I;
// The top 2 bits of the first byte specify the size.
diff --git a/arch/SystemZ/SystemZGenAsmWriter.inc b/arch/SystemZ/SystemZGenAsmWriter.inc
index 73baaaa..8400fe1 100644
--- a/arch/SystemZ/SystemZGenAsmWriter.inc
+++ b/arch/SystemZ/SystemZGenAsmWriter.inc
@@ -937,7 +937,7 @@
};
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'l', 'a', 'a', 9, 0,
/* 5 */ 'l', 'a', 9, 0,
/* 9 */ 'l', 'e', 'd', 'b', 'r', 'a', 9, 0,
diff --git a/arch/SystemZ/SystemZGenDisassemblerTables.inc b/arch/SystemZ/SystemZGenDisassemblerTables.inc
index cbe54d4..abb13e2 100644
--- a/arch/SystemZ/SystemZGenDisassemblerTables.inc
+++ b/arch/SystemZ/SystemZGenDisassemblerTables.inc
@@ -24,7 +24,7 @@
return (insn & fieldMask) >> startBit; \
}
-static uint8_t DecoderTable16[] = {
+static const uint8_t DecoderTable16[] = {
/* 0 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ...
/* 3 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 134
/* 7 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ...
@@ -97,7 +97,7 @@
0
};
-static uint8_t DecoderTable32[] = {
+static const uint8_t DecoderTable32[] = {
/* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ...
/* 3 */ MCD_OPC_FilterValue, 64, 4, 0, // Skip to: 11
/* 7 */ MCD_OPC_Decode, 219, 6, 7, // Opcode: STH
@@ -833,7 +833,7 @@
0
};
-static uint8_t DecoderTable48[] = {
+static const uint8_t DecoderTable48[] = {
/* 0 */ MCD_OPC_ExtractField, 40, 8, // Inst{47-40} ...
/* 3 */ MCD_OPC_FilterValue, 192, 1, 238, 0, // Skip to: 246
/* 8 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ...
@@ -1697,7 +1697,7 @@
#define DecodeToMCInst(fname,fieldname, InsnType) \
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
- uint64_t Address, void *Decoder) \
+ uint64_t Address, const void *Decoder) \
{ \
InsnType tmp; \
switch (Idx) { \
@@ -2936,11 +2936,11 @@
}
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
- InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
{ \
uint64_t Bits = getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
+ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0, ExpectedValue; \
DecodeStatus S = MCDisassembler_Success; \
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
diff --git a/arch/SystemZ/SystemZGenRegisterInfo.inc b/arch/SystemZ/SystemZGenRegisterInfo.inc
index c912ed3..28c1de9 100644
--- a/arch/SystemZ/SystemZGenRegisterInfo.inc
+++ b/arch/SystemZ/SystemZGenRegisterInfo.inc
@@ -145,7 +145,7 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg SystemZRegDiffLists[] = {
+static const MCPhysReg SystemZRegDiffLists[] = {
/* 0 */ 65193, 1, 1, 1, 0,
/* 5 */ 65469, 1, 0,
/* 8 */ 65519, 2, 0,
@@ -193,7 +193,7 @@
/* 171 */ 65535, 0,
};
-static uint16_t SystemZSubRegIdxLists[] = {
+static const uint16_t SystemZSubRegIdxLists[] = {
/* 0 */ 5, 1, 0,
/* 3 */ 6, 1, 2, 3, 0,
/* 8 */ 6, 5, 1, 2, 4, 3, 0,
@@ -301,122 +301,122 @@
};
// GRX32Bit Register Class...
- static MCPhysReg GRX32Bit[] = {
+ static const MCPhysReg GRX32Bit[] = {
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H,
};
// GRX32Bit Bit set.
- static uint8_t GRX32BitBits[] = {
+ static const uint8_t GRX32BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
};
// FP32Bit Register Class...
- static MCPhysReg FP32Bit[] = {
+ static const MCPhysReg FP32Bit[] = {
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
};
// FP32Bit Bit set.
- static uint8_t FP32BitBits[] = {
+ static const uint8_t FP32BitBits[] = {
0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
// GR32Bit Register Class...
- static MCPhysReg GR32Bit[] = {
+ static const MCPhysReg GR32Bit[] = {
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
};
// GR32Bit Bit set.
- static uint8_t GR32BitBits[] = {
+ static const uint8_t GR32BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
// GRH32Bit Register Class...
- static MCPhysReg GRH32Bit[] = {
+ static const MCPhysReg GRH32Bit[] = {
SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H,
};
// GRH32Bit Bit set.
- static uint8_t GRH32BitBits[] = {
+ static const uint8_t GRH32BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
// ADDR32Bit Register Class...
- static MCPhysReg ADDR32Bit[] = {
+ static const MCPhysReg ADDR32Bit[] = {
SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
};
// ADDR32Bit Bit set.
- static uint8_t ADDR32BitBits[] = {
+ static const uint8_t ADDR32BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
};
// CCRegs Register Class...
- static MCPhysReg CCRegs[] = {
+ static const MCPhysReg CCRegs[] = {
SystemZ_CC,
};
// CCRegs Bit set.
- static uint8_t CCRegsBits[] = {
+ static const uint8_t CCRegsBits[] = {
0x02,
};
// FP64Bit Register Class...
- static MCPhysReg FP64Bit[] = {
+ static const MCPhysReg FP64Bit[] = {
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
};
// FP64Bit Bit set.
- static uint8_t FP64BitBits[] = {
+ static const uint8_t FP64BitBits[] = {
0xfc, 0xff, 0x03,
};
// GR64Bit Register Class...
- static MCPhysReg GR64Bit[] = {
+ static const MCPhysReg GR64Bit[] = {
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
};
// GR64Bit Bit set.
- static uint8_t GR64BitBits[] = {
+ static const uint8_t GR64BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
// ADDR64Bit Register Class...
- static MCPhysReg ADDR64Bit[] = {
+ static const MCPhysReg ADDR64Bit[] = {
SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
};
// ADDR64Bit Bit set.
- static uint8_t ADDR64BitBits[] = {
+ static const uint8_t ADDR64BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
};
// FP128Bit Register Class...
- static MCPhysReg FP128Bit[] = {
+ static const MCPhysReg FP128Bit[] = {
SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q,
};
// FP128Bit Bit set.
- static uint8_t FP128BitBits[] = {
+ static const uint8_t FP128BitBits[] = {
0x00, 0x00, 0xfc, 0x03,
};
// GR128Bit Register Class...
- static MCPhysReg GR128Bit[] = {
+ static const MCPhysReg GR128Bit[] = {
SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
};
// GR128Bit Bit set.
- static uint8_t GR128BitBits[] = {
+ static const uint8_t GR128BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
};
// ADDR128Bit Register Class...
- static MCPhysReg ADDR128Bit[] = {
+ static const MCPhysReg ADDR128Bit[] = {
SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
};
// ADDR128Bit Bit set.
- static uint8_t ADDR128BitBits[] = {
+ static const uint8_t ADDR128BitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
};
diff --git a/arch/SystemZ/SystemZInstPrinter.c b/arch/SystemZ/SystemZInstPrinter.c
index 51ede35..c0fd796 100644
--- a/arch/SystemZ/SystemZInstPrinter.c
+++ b/arch/SystemZ/SystemZInstPrinter.c
@@ -249,6 +249,7 @@
if (MCOperand_isImm(MO)) {
imm = (int32_t)MCOperand_getImm(MO);
+
printInt32(O, imm);
if (MI->csh->detail) {
@@ -314,7 +315,7 @@
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
{
- static char *const CondNames[] = {
+ static const char *const CondNames[] = {
"o", "h", "nle", "l", "nhe", "lh", "ne",
"e", "nlh", "he", "nl", "le", "nh", "no"
};
diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c
index c32ec1a..8e58eaf 100644
--- a/arch/SystemZ/SystemZMapping.c
+++ b/arch/SystemZ/SystemZMapping.c
@@ -14,7 +14,7 @@
#include "SystemZGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ SYSZ_REG_INVALID, NULL },
{ SYSZ_REG_0, "0"},
@@ -66,7 +66,7 @@
#endif
}
-static insn_map insns[] = {
+static const insn_map insns[] = {
// dummy item
{
0, 0,
@@ -109,7 +109,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ SYSZ_INS_INVALID, NULL },
{ SYSZ_INS_A, "a" },
@@ -796,7 +796,7 @@
};
// special alias insn
-static name_map alias_insn_names[] = {
+static const name_map alias_insn_names[] = {
{ 0, NULL }
};
#endif
@@ -822,7 +822,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ SYSZ_GRP_INVALID, NULL },
{ SYSZ_GRP_JUMP, "jump" },
@@ -848,7 +848,7 @@
// map internal raw register to 'public' register
sysz_reg SystemZ_map_register(unsigned int r)
{
- static unsigned int map[] = { 0,
+ static const unsigned int map[] = { 0,
SYSZ_REG_CC, SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F2, SYSZ_REG_F3,
SYSZ_REG_F4, SYSZ_REG_F5, SYSZ_REG_F6, SYSZ_REG_F7, SYSZ_REG_F8,
SYSZ_REG_F9, SYSZ_REG_F10, SYSZ_REG_F11, SYSZ_REG_F12, SYSZ_REG_F13,
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 6978a47..252b828 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -27,6 +27,7 @@
#include <ctype.h>
#endif
#include <capstone/platform.h>
+
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <Availability.h>
#include <libkern/libkern.h>
@@ -659,6 +660,7 @@
uint8_t encsize;
int64_t imm = MCOperand_getImm(Op);
uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize);
+
if (opsize == 1) // print 1 byte immediate in positive form
imm = imm & 0xff;
@@ -794,17 +796,7 @@
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
if (DispVal) {
if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) {
- if (DispVal < 0) {
- if (DispVal < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%"PRIx64, -DispVal);
- else
- SStream_concat(O, "-%"PRIu64, -DispVal);
- } else {
- if (DispVal > HEX_THRESHOLD)
- SStream_concat(O, "0x%"PRIx64, DispVal);
- else
- SStream_concat(O, "%"PRIu64, DispVal);
- }
+ printInt64(O, DispVal);
} else {
// only immediate as address of memory
if (DispVal < 0) {
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index 24b0dbb..5034fae 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -76,7 +76,7 @@
static void translateRegister(MCInst *mcInst, Reg reg)
{
#define ENTRY(x) X86_##x,
- uint8_t llvmRegnums[] = {
+ static const uint8_t llvmRegnums[] = {
ALL_REGS
0
};
@@ -178,6 +178,7 @@
} // By default sign-extend all X86 immediates based on their encoding.
else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
type == TYPE_IMM64 || type == TYPE_IMMv) {
+
switch (operand->encoding) {
default:
break;
@@ -267,7 +268,9 @@
case X86_VCMPSSZrr: NewOpc = X86_VCMPSSZrri_alt; break;
}
// Switch opcode to the one that doesn't get special printing.
- MCInst_setOpcode(mcInst, NewOpc);
+ if (NewOpc != 0) {
+ MCInst_setOpcode(mcInst, NewOpc);
+ }
}
#endif
} else if (type == TYPE_AVX512ICC) {
@@ -486,12 +489,12 @@
static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn)
{
// Addresses in an MCInst are represented as five operands:
- // 1. basereg (register) The R/M base, or (if there is a SIB) the
+ // 1. basereg (register) The R/M base, or (if there is a SIB) the
// SIB base
- // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
+ // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
// scale amount
// 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
- // the index (which is multiplied by the
+ // the index (which is multiplied by the
// scale amount)
// 4. displacement (immediate) 0, or the displacement if there is one
// 5. segmentreg (register) x86_registerNONE for now, but could be set
@@ -643,7 +646,7 @@
// placeholders to keep the compiler happy.
#define ENTRY(x) \
case EA_BASE_##x: \
- MCOperand_CreateReg0(mcInst, X86_##x); break;
+ MCOperand_CreateReg0(mcInst, X86_##x); break;
ALL_EA_BASES
#undef ENTRY
#define ENTRY(x) case EA_REG_##x:
@@ -677,7 +680,7 @@
/// @return - 0 on success; nonzero otherwise
static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand,
InternalInstruction *insn)
-{
+{
switch (operand->type) {
case TYPE_R8:
case TYPE_R16:
@@ -748,7 +751,7 @@
return false;
}
-/// translateOperand - Translates an operand stored in an internal instruction
+/// translateOperand - Translates an operand stored in an internal instruction
/// to LLVM's format and appends it to an MCInst.
///
/// @param mcInst - The MCInst to append to.
diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c
index 203bcb5..35db745 100644
--- a/arch/X86/X86DisassemblerDecoder.c
+++ b/arch/X86/X86DisassemblerDecoder.c
@@ -1313,7 +1313,6 @@
}
}
-
/*
* Absolute moves need special handling.
* -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
diff --git a/arch/X86/X86DisassemblerDecoder.h b/arch/X86/X86DisassemblerDecoder.h
index 7061276..b1b0a98 100644
--- a/arch/X86/X86DisassemblerDecoder.h
+++ b/arch/X86/X86DisassemblerDecoder.h
@@ -616,7 +616,6 @@
uint8_t immediateOffset;
uint8_t modRMOffset;
-
// end-of-zero-members
/* Reader interface (C) */
diff --git a/arch/X86/X86GenAsmWriter.inc b/arch/X86/X86GenAsmWriter.inc
index e4f6033..f28c37d 100644
--- a/arch/X86/X86GenAsmWriter.inc
+++ b/arch/X86/X86GenAsmWriter.inc
@@ -19234,6 +19234,7 @@
// Emit the opcode for the instruction.
unsigned int opcode = MCInst_getOpcode(MI);
+ //printf("> opcode = %u\n", opcode);
uint64_t Bits1 = OpInfo[opcode];
uint64_t Bits2 = OpInfo2[opcode];
uint64_t Bits = (Bits2 << 32) | Bits1;
@@ -20847,12 +20848,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 242 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
/* 12 */ 's', 't', '(', '2', ')', 0,
diff --git a/arch/X86/X86GenAsmWriter1.inc b/arch/X86/X86GenAsmWriter1.inc
index 46c2f16..08239f5 100644
--- a/arch/X86/X86GenAsmWriter1.inc
+++ b/arch/X86/X86GenAsmWriter1.inc
@@ -18932,6 +18932,7 @@
// Emit the opcode for the instruction.
unsigned int opcode = MCInst_getOpcode(MI);
+ //printf(">> opcode = %u\n", opcode);
uint64_t Bits1 = OpInfo[opcode];
uint64_t Bits2 = OpInfo2[opcode];
uint64_t Bits = (Bits2 << 32) | Bits1;
@@ -20227,12 +20228,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 242 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
/* 12 */ 's', 't', '(', '2', ')', 0,
diff --git a/arch/X86/X86GenAsmWriter1_reduce.inc b/arch/X86/X86GenAsmWriter1_reduce.inc
index 9dd4fb8..3c80b38 100644
--- a/arch/X86/X86GenAsmWriter1_reduce.inc
+++ b/arch/X86/X86GenAsmWriter1_reduce.inc
@@ -4318,12 +4318,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 242 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
/* 12 */ 's', 't', '(', '2', ')', 0,
diff --git a/arch/X86/X86GenAsmWriter_reduce.inc b/arch/X86/X86GenAsmWriter_reduce.inc
index 0653e69..1f6fd65 100644
--- a/arch/X86/X86GenAsmWriter_reduce.inc
+++ b/arch/X86/X86GenAsmWriter_reduce.inc
@@ -2902,12 +2902,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 242 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
/* 12 */ 's', 't', '(', '2', ')', 0,
diff --git a/arch/X86/X86GenRegisterInfo.inc b/arch/X86/X86GenRegisterInfo.inc
index 8fa113e..b27b697 100644
--- a/arch/X86/X86GenRegisterInfo.inc
+++ b/arch/X86/X86GenRegisterInfo.inc
@@ -347,7 +347,7 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg X86RegDiffLists[] = {
+static const MCPhysReg X86RegDiffLists[] = {
/* 0 */ 0, 1, 0,
/* 3 */ 2, 1, 0,
/* 6 */ 5, 1, 0,
@@ -398,7 +398,7 @@
/* 149 */ 65520, 65520, 65535, 65535, 0,
};
-static uint16_t X86SubRegIdxLists[] = {
+static const uint16_t X86SubRegIdxLists[] = {
/* 0 */ 4, 3, 1, 0,
/* 4 */ 4, 3, 1, 2, 0,
/* 9 */ 4, 3, 0,
@@ -651,7 +651,7 @@
};
// GR8 Register Class...
- static MCPhysReg GR8[] = {
+ static const MCPhysReg GR8[] = {
X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, X86_SIL, X86_DIL, X86_BPL, X86_SPL, X86_R8B, X86_R9B, X86_R10B, X86_R11B, X86_R14B, X86_R15B, X86_R12B, X86_R13B,
};
@@ -661,17 +661,17 @@
};
// GR8_NOREX Register Class...
- static MCPhysReg GR8_NOREX[] = {
+ static const MCPhysReg GR8_NOREX[] = {
X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH,
};
// GR8_NOREX Bit set.
- static uint8_t GR8_NOREXBits[] = {
+ static const uint8_t GR8_NOREXBits[] = {
0x36, 0x26, 0x01,
};
// VK1 Register Class...
- static MCPhysReg VK1[] = {
+ static const MCPhysReg VK1[] = {
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -681,7 +681,7 @@
};
// VK2 Register Class...
- static MCPhysReg VK2[] = {
+ static const MCPhysReg VK2[] = {
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -691,7 +691,7 @@
};
// VK4 Register Class...
- static MCPhysReg VK4[] = {
+ static const MCPhysReg VK4[] = {
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -701,7 +701,7 @@
};
// VK8 Register Class...
- static MCPhysReg VK8[] = {
+ static const MCPhysReg VK8[] = {
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -711,7 +711,7 @@
};
// VK1WM Register Class...
- static MCPhysReg VK1WM[] = {
+ static const MCPhysReg VK1WM[] = {
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -721,7 +721,7 @@
};
// VK2WM Register Class...
- static MCPhysReg VK2WM[] = {
+ static const MCPhysReg VK2WM[] = {
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -731,7 +731,7 @@
};
// VK4WM Register Class...
- static MCPhysReg VK4WM[] = {
+ static const MCPhysReg VK4WM[] = {
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -741,7 +741,7 @@
};
// VK8WM Register Class...
- static MCPhysReg VK8WM[] = {
+ static const MCPhysReg VK8WM[] = {
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -811,37 +811,37 @@
};
// SEGMENT_REG Register Class...
- static MCPhysReg SEGMENT_REG[] = {
+ static const MCPhysReg SEGMENT_REG[] = {
X86_CS, X86_DS, X86_SS, X86_ES, X86_FS, X86_GS,
};
// SEGMENT_REG Bit set.
- static uint8_t SEGMENT_REGBits[] = {
+ static const uint8_t SEGMENT_REGBits[] = {
0x00, 0x08, 0x02, 0x10, 0x03, 0x00, 0x02,
};
// GR16_ABCD Register Class...
- static MCPhysReg GR16_ABCD[] = {
+ static const MCPhysReg GR16_ABCD[] = {
X86_AX, X86_CX, X86_DX, X86_BX,
};
// GR16_ABCD Bit set.
- static uint8_t GR16_ABCDBits[] = {
+ static const uint8_t GR16_ABCDBits[] = {
0x08, 0x11, 0x04,
};
// FPCCR Register Class...
- static MCPhysReg FPCCR[] = {
+ static const MCPhysReg FPCCR[] = {
X86_FPSW,
};
// FPCCR Bit set.
- static uint8_t FPCCRBits[] = {
+ static const uint8_t FPCCRBits[] = {
0x00, 0x00, 0x00, 0x80,
};
// FR32X Register Class...
- static MCPhysReg FR32X[] = {
+ static const MCPhysReg FR32X[] = {
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
};
@@ -851,7 +851,7 @@
};
// FR32 Register Class...
- static MCPhysReg FR32[] = {
+ static const MCPhysReg FR32[] = {
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
};
@@ -861,7 +861,7 @@
};
// GR32 Register Class...
- static MCPhysReg GR32[] = {
+ static const MCPhysReg GR32[] = {
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
};
@@ -871,7 +871,7 @@
};
// GR32_NOAX Register Class...
- static MCPhysReg GR32_NOAX[] = {
+ static const MCPhysReg GR32_NOAX[] = {
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
};
@@ -881,7 +881,7 @@
};
// GR32_NOSP Register Class...
- static MCPhysReg GR32_NOSP[] = {
+ static const MCPhysReg GR32_NOSP[] = {
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
};
@@ -891,7 +891,7 @@
};
// GR32_NOAX_and_GR32_NOSP Register Class...
- static MCPhysReg GR32_NOAX_and_GR32_NOSP[] = {
+ static const MCPhysReg GR32_NOAX_and_GR32_NOSP[] = {
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
};
@@ -901,27 +901,27 @@
};
// DEBUG_REG Register Class...
- static MCPhysReg DEBUG_REG[] = {
+ static const MCPhysReg DEBUG_REG[] = {
X86_DR0, X86_DR1, X86_DR2, X86_DR3, X86_DR4, X86_DR5, X86_DR6, X86_DR7,
};
// DEBUG_REG Bit set.
- static uint8_t DEBUG_REGBits[] = {
+ static const uint8_t DEBUG_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
};
// GR32_NOREX Register Class...
- static MCPhysReg GR32_NOREX[] = {
+ static const MCPhysReg GR32_NOREX[] = {
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP,
};
// GR32_NOREX Bit set.
- static uint8_t GR32_NOREXBits[] = {
+ static const uint8_t GR32_NOREXBits[] = {
0x00, 0x00, 0xf8, 0x61,
};
// VK32 Register Class...
- static MCPhysReg VK32[] = {
+ static const MCPhysReg VK32[] = {
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -931,27 +931,27 @@
};
// GR32_NOAX_and_GR32_NOREX Register Class...
- static MCPhysReg GR32_NOAX_and_GR32_NOREX[] = {
+ static const MCPhysReg GR32_NOAX_and_GR32_NOREX[] = {
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP,
};
// GR32_NOAX_and_GR32_NOREX Bit set.
- static uint8_t GR32_NOAX_and_GR32_NOREXBits[] = {
+ static const uint8_t GR32_NOAX_and_GR32_NOREXBits[] = {
0x00, 0x00, 0xf0, 0x61,
};
// GR32_NOREX_NOSP Register Class...
- static MCPhysReg GR32_NOREX_NOSP[] = {
+ static const MCPhysReg GR32_NOREX_NOSP[] = {
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP,
};
// GR32_NOREX_NOSP Bit set.
- static uint8_t GR32_NOREX_NOSPBits[] = {
+ static const uint8_t GR32_NOREX_NOSPBits[] = {
0x00, 0x00, 0xf8, 0x21,
};
// RFP32 Register Class...
- static MCPhysReg RFP32[] = {
+ static const MCPhysReg RFP32[] = {
X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
};
@@ -961,7 +961,7 @@
};
// VK32WM Register Class...
- static MCPhysReg VK32WM[] = {
+ static const MCPhysReg VK32WM[] = {
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -971,87 +971,87 @@
};
// GR32_NOAX_and_GR32_NOREX_NOSP Register Class...
- static MCPhysReg GR32_NOAX_and_GR32_NOREX_NOSP[] = {
+ static const MCPhysReg GR32_NOAX_and_GR32_NOREX_NOSP[] = {
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP,
};
// GR32_NOAX_and_GR32_NOREX_NOSP Bit set.
- static uint8_t GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
+ static const uint8_t GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
0x00, 0x00, 0xf0, 0x21,
};
// GR32_ABCD Register Class...
- static MCPhysReg GR32_ABCD[] = {
+ static const MCPhysReg GR32_ABCD[] = {
X86_EAX, X86_ECX, X86_EDX, X86_EBX,
};
// GR32_ABCD Bit set.
- static uint8_t GR32_ABCDBits[] = {
+ static const uint8_t GR32_ABCDBits[] = {
0x00, 0x00, 0x68, 0x01,
};
// GR32_ABCD_and_GR32_NOAX Register Class...
- static MCPhysReg GR32_ABCD_and_GR32_NOAX[] = {
+ static const MCPhysReg GR32_ABCD_and_GR32_NOAX[] = {
X86_ECX, X86_EDX, X86_EBX,
};
// GR32_ABCD_and_GR32_NOAX Bit set.
- static uint8_t GR32_ABCD_and_GR32_NOAXBits[] = {
+ static const uint8_t GR32_ABCD_and_GR32_NOAXBits[] = {
0x00, 0x00, 0x60, 0x01,
};
// GR32_TC Register Class...
- static MCPhysReg GR32_TC[] = {
+ static const MCPhysReg GR32_TC[] = {
X86_EAX, X86_ECX, X86_EDX,
};
// GR32_TC Bit set.
- static uint8_t GR32_TCBits[] = {
+ static const uint8_t GR32_TCBits[] = {
0x00, 0x00, 0x48, 0x01,
};
// GR32_AD Register Class...
- static MCPhysReg GR32_AD[] = {
+ static const MCPhysReg GR32_AD[] = {
X86_EAX, X86_EDX,
};
// GR32_AD Bit set.
- static uint8_t GR32_ADBits[] = {
+ static const uint8_t GR32_ADBits[] = {
0x00, 0x00, 0x08, 0x01,
};
// GR32_NOAX_and_GR32_TC Register Class...
- static MCPhysReg GR32_NOAX_and_GR32_TC[] = {
+ static const MCPhysReg GR32_NOAX_and_GR32_TC[] = {
X86_ECX, X86_EDX,
};
// GR32_NOAX_and_GR32_TC Bit set.
- static uint8_t GR32_NOAX_and_GR32_TCBits[] = {
+ static const uint8_t GR32_NOAX_and_GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x01,
};
// CCR Register Class...
- static MCPhysReg CCR[] = {
+ static const MCPhysReg CCR[] = {
X86_EFLAGS,
};
// CCR Bit set.
- static uint8_t CCRBits[] = {
+ static const uint8_t CCRBits[] = {
0x00, 0x00, 0x00, 0x02,
};
// GR32_AD_and_GR32_NOAX Register Class...
- static MCPhysReg GR32_AD_and_GR32_NOAX[] = {
+ static const MCPhysReg GR32_AD_and_GR32_NOAX[] = {
X86_EDX,
};
// GR32_AD_and_GR32_NOAX Bit set.
- static uint8_t GR32_AD_and_GR32_NOAXBits[] = {
+ static const uint8_t GR32_AD_and_GR32_NOAXBits[] = {
0x00, 0x00, 0x00, 0x01,
};
// RFP64 Register Class...
- static MCPhysReg RFP64[] = {
+ static const MCPhysReg RFP64[] = {
X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
};
@@ -1061,7 +1061,7 @@
};
// FR64X Register Class...
- static MCPhysReg FR64X[] = {
+ static const MCPhysReg FR64X[] = {
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
};
@@ -1071,7 +1071,7 @@
};
// GR64 Register Class...
- static MCPhysReg GR64[] = {
+ static const MCPhysReg GR64[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, X86_RIP,
};
@@ -1081,17 +1081,17 @@
};
// CONTROL_REG Register Class...
- static MCPhysReg CONTROL_REG[] = {
+ static const MCPhysReg CONTROL_REG[] = {
X86_CR0, X86_CR1, X86_CR2, X86_CR3, X86_CR4, X86_CR5, X86_CR6, X86_CR7, X86_CR8, X86_CR9, X86_CR10, X86_CR11, X86_CR12, X86_CR13, X86_CR14, X86_CR15,
};
// CONTROL_REG Bit set.
- static uint8_t CONTROL_REGBits[] = {
+ static const uint8_t CONTROL_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
// FR64 Register Class...
- static MCPhysReg FR64[] = {
+ static const MCPhysReg FR64[] = {
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
};
@@ -1101,7 +1101,7 @@
};
// GR64_with_sub_8bit Register Class...
- static MCPhysReg GR64_with_sub_8bit[] = {
+ static const MCPhysReg GR64_with_sub_8bit[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP,
};
@@ -1111,7 +1111,7 @@
};
// GR64_NOSP Register Class...
- static MCPhysReg GR64_NOSP[] = {
+ static const MCPhysReg GR64_NOSP[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP,
};
@@ -1121,7 +1121,7 @@
};
// GR64_with_sub_32bit_in_GR32_NOAX Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX[] = {
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP,
};
@@ -1131,7 +1131,7 @@
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP[] = {
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP,
};
@@ -1141,17 +1141,17 @@
};
// GR64_NOREX Register Class...
- static MCPhysReg GR64_NOREX[] = {
+ static const MCPhysReg GR64_NOREX[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, X86_RIP,
};
// GR64_NOREX Bit set.
- static uint8_t GR64_NOREXBits[] = {
+ static const uint8_t GR64_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0xf8, 0x1b,
};
// GR64_TC Register Class...
- static MCPhysReg GR64_TC[] = {
+ static const MCPhysReg GR64_TC[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, X86_RIP,
};
@@ -1161,7 +1161,7 @@
};
// GR64_NOSP_and_GR64_TC Register Class...
- static MCPhysReg GR64_NOSP_and_GR64_TC[] = {
+ static const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11,
};
@@ -1171,17 +1171,17 @@
};
// GR64_with_sub_16bit_in_GR16_NOREX Register Class...
- static MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
+ static const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP,
};
// GR64_with_sub_16bit_in_GR16_NOREX Bit set.
- static uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
+ static const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0xf8, 0x19,
};
// VK64 Register Class...
- static MCPhysReg VK64[] = {
+ static const MCPhysReg VK64[] = {
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -1191,7 +1191,7 @@
};
// VR64 Register Class...
- static MCPhysReg VR64[] = {
+ static const MCPhysReg VR64[] = {
X86_MM0, X86_MM1, X86_MM2, X86_MM3, X86_MM4, X86_MM5, X86_MM6, X86_MM7,
};
@@ -1201,17 +1201,17 @@
};
// GR64_NOREX_NOSP Register Class...
- static MCPhysReg GR64_NOREX_NOSP[] = {
+ static const MCPhysReg GR64_NOREX_NOSP[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP,
};
// GR64_NOREX_NOSP Bit set.
- static uint8_t GR64_NOREX_NOSPBits[] = {
+ static const uint8_t GR64_NOREX_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0xf8, 0x09,
};
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX Register Class...
- static MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
+ static const MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11,
};
@@ -1221,17 +1221,17 @@
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP,
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0xf0, 0x19,
};
// VK64WM Register Class...
- static MCPhysReg VK64WM[] = {
+ static const MCPhysReg VK64WM[] = {
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
};
@@ -1241,17 +1241,17 @@
};
// GR64_NOREX_and_GR64_TC Register Class...
- static MCPhysReg GR64_NOREX_and_GR64_TC[] = {
+ static const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RIP,
};
// GR64_NOREX_and_GR64_TC Bit set.
- static uint8_t GR64_NOREX_and_GR64_TCBits[] = {
+ static const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0xc8, 0x0b,
};
// GR64_TCW64 Register Class...
- static MCPhysReg GR64_TCW64[] = {
+ static const MCPhysReg GR64_TCW64[] = {
X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11,
};
@@ -1261,27 +1261,27 @@
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP[] = {
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP,
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0xf0, 0x09,
};
// GR64_NOREX_NOSP_and_GR64_TC Register Class...
- static MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
+ static const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI,
};
// GR64_NOREX_NOSP_and_GR64_TC Bit set.
- static uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
+ static const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0xc8, 0x09,
};
// GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX Register Class...
- static MCPhysReg GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
+ static const MCPhysReg GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11,
};
@@ -1291,77 +1291,77 @@
};
// GR64_ABCD Register Class...
- static MCPhysReg GR64_ABCD[] = {
+ static const MCPhysReg GR64_ABCD[] = {
X86_RAX, X86_RCX, X86_RDX, X86_RBX,
};
// GR64_ABCD Bit set.
- static uint8_t GR64_ABCDBits[] = {
+ static const uint8_t GR64_ABCDBits[] = {
0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
};
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Register Class...
- static MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
+ static const MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
X86_RCX, X86_RDX, X86_RSI, X86_RDI,
};
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Bit set.
- static uint8_t GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
+ static const uint8_t GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0xc0, 0x09,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX[] = {
X86_RCX, X86_RDX, X86_RBX,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x60, 0x01,
};
// GR64_with_sub_32bit_in_GR32_TC Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
X86_RAX, X86_RCX, X86_RDX,
};
// GR64_with_sub_32bit_in_GR32_TC Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
};
// GR64_with_sub_32bit_in_GR32_AD Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_AD[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_AD[] = {
X86_RAX, X86_RDX,
};
// GR64_with_sub_32bit_in_GR32_AD Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_ADBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_ADBits[] = {
0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC[] = {
X86_RCX, X86_RDX,
};
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
};
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX Register Class...
- static MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX[] = {
+ static const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX[] = {
X86_RDX,
};
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX Bit set.
- static uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXBits[] = {
+ static const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
};
// RST Register Class...
- static MCPhysReg RST[] = {
+ static const MCPhysReg RST[] = {
X86_ST0, X86_ST1, X86_ST2, X86_ST3, X86_ST4, X86_ST5, X86_ST6, X86_ST7,
};
@@ -1371,7 +1371,7 @@
};
// RFP80 Register Class...
- static MCPhysReg RFP80[] = {
+ static const MCPhysReg RFP80[] = {
X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
};
@@ -1381,7 +1381,7 @@
};
// VR128X Register Class...
- static MCPhysReg VR128X[] = {
+ static const MCPhysReg VR128X[] = {
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
};
@@ -1391,7 +1391,7 @@
};
// VR128 Register Class...
- static MCPhysReg VR128[] = {
+ static const MCPhysReg VR128[] = {
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
};
@@ -1401,7 +1401,7 @@
};
// VR256X Register Class...
- static MCPhysReg VR256X[] = {
+ static const MCPhysReg VR256X[] = {
X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, X86_YMM16, X86_YMM17, X86_YMM18, X86_YMM19, X86_YMM20, X86_YMM21, X86_YMM22, X86_YMM23, X86_YMM24, X86_YMM25, X86_YMM26, X86_YMM27, X86_YMM28, X86_YMM29, X86_YMM30, X86_YMM31,
};
@@ -1411,7 +1411,7 @@
};
// VR256 Register Class...
- static MCPhysReg VR256[] = {
+ static const MCPhysReg VR256[] = {
X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15,
};
@@ -1421,7 +1421,7 @@
};
// VR512 Register Class...
- static MCPhysReg VR512[] = {
+ static const MCPhysReg VR512[] = {
X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, X86_ZMM16, X86_ZMM17, X86_ZMM18, X86_ZMM19, X86_ZMM20, X86_ZMM21, X86_ZMM22, X86_ZMM23, X86_ZMM24, X86_ZMM25, X86_ZMM26, X86_ZMM27, X86_ZMM28, X86_ZMM29, X86_ZMM30, X86_ZMM31,
};
@@ -1431,7 +1431,7 @@
};
// VR512_with_sub_xmm_in_FR32 Register Class...
- static MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
+ static const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15,
};
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index ecc31d4..607bca3 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -26,6 +26,7 @@
#include <ctype.h>
#endif
#include <capstone/platform.h>
+
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <Availability.h>
#include <libkern/libkern.h>
@@ -351,7 +352,7 @@
#endif
-static char *getRegisterName(unsigned RegNo);
+static const char *getRegisterName(unsigned RegNo);
static void printRegName(SStream *OS, unsigned RegNo)
{
SStream_concat0(OS, getRegisterName(RegNo));
@@ -888,6 +889,7 @@
uint8_t encsize;
int64_t imm = MCOperand_getImm(Op);
uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize);
+
if (opsize == 1) // print 1 byte immediate in positive form
imm = imm & 0xff;
diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
index 07772df..3fcd1bd 100644
--- a/arch/X86/X86Mapping.c
+++ b/arch/X86/X86Mapping.c
@@ -20,7 +20,7 @@
#include "../../utils.h"
-uint64_t arch_masks[9] = {
+const uint64_t arch_masks[9] = {
0, 0xff,
0xffff,
0,
@@ -29,7 +29,7 @@
0xffffffffffffffffLL
};
-static x86_reg sib_base_map[] = {
+static const x86_reg sib_base_map[] = {
X86_REG_INVALID,
#define ENTRY(x) X86_REG_##x,
ALL_SIB_BASES
@@ -48,7 +48,7 @@
X86_REG_sib64 = 505
};
-static x86_reg sib_index_map[] = {
+static const x86_reg sib_index_map[] = {
X86_REG_INVALID,
#define ENTRY(x) X86_REG_##x,
ALL_EA_BASES
@@ -58,7 +58,7 @@
#undef ENTRY
};
-static x86_reg segment_map[] = {
+static const x86_reg segment_map[] = {
X86_REG_INVALID,
X86_REG_CS,
X86_REG_SS,
@@ -84,7 +84,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ X86_REG_INVALID, NULL },
{ X86_REG_AH, "ah" },
@@ -332,7 +332,7 @@
#endif
// register size in non-64bit mode
-uint8_t regsize_map_32 [] = {
+const uint8_t regsize_map_32 [] = {
0, // { X86_REG_INVALID, NULL },
1, // { X86_REG_AH, "ah" },
1, // { X86_REG_AL, "al" },
@@ -578,7 +578,7 @@
};
// register size in 64bit mode
-uint8_t regsize_map_64 [] = {
+const uint8_t regsize_map_64 [] = {
0, // { X86_REG_INVALID, NULL },
1, // { X86_REG_AH, "ah" },
1, // { X86_REG_AL, "al" },
@@ -845,7 +845,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ X86_INS_INVALID, NULL },
{ X86_INS_AAA, "aaa" },
@@ -2374,7 +2374,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
// generic groups
{ X86_GRP_INVALID, NULL },
{ X86_GRP_JUMP, "jump" },
@@ -2448,7 +2448,7 @@
#endif
#ifndef CAPSTONE_X86_REDUCE
-static insn_map insns[] = { // full x86 instructions
+static const insn_map insns[] = { // full x86 instructions
// dummy item
{
0, 0,
diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h
index 2ab464e..b217b61 100644
--- a/arch/X86/X86Mapping.h
+++ b/arch/X86/X86Mapping.h
@@ -36,15 +36,15 @@
bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
-extern uint64_t arch_masks[9];
+extern const uint64_t arch_masks[9];
// handle LOCK/REP/REPNE prefixes
// return True if we patch mnemonic, like in MULPD case
bool X86_lockrep(MCInst *MI, SStream *O);
// map registers to sizes
-extern uint8_t regsize_map_32[];
-extern uint8_t regsize_map_64[];
+extern const uint8_t regsize_map_32[];
+extern const uint8_t regsize_map_64[];
void op_addReg(MCInst *MI, int reg);
void op_addImm(MCInst *MI, int v);
diff --git a/arch/XCore/XCoreDisassembler.c b/arch/XCore/XCoreDisassembler.c
index 46e885a..e661d35 100644
--- a/arch/XCore/XCoreDisassembler.c
+++ b/arch/XCore/XCoreDisassembler.c
@@ -51,89 +51,90 @@
// Encoded as a little-endian 32-bit word in the stream.
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24);
+
return true;
}
-static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
{
- MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+ const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
return rc->RegsBegin[RegNo];
}
static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
- uint64_t Address, void *Decoder);
+ uint64_t Address, const void *Decoder);
#include "XCoreGenDisassemblerTables.inc"
@@ -142,7 +143,7 @@
#include "XCoreGenRegisterInfo.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Address, void *Decoder)
+ uint64_t Address, const void *Decoder)
{
unsigned Reg;
@@ -156,7 +157,7 @@
}
static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
- uint64_t Address, void *Decoder)
+ uint64_t Address, const void *Decoder)
{
unsigned Reg;
if (RegNo > 15)
@@ -169,9 +170,9 @@
}
static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
- uint64_t Address, void *Decoder)
+ uint64_t Address, const void *Decoder)
{
- static unsigned Values[] = {
+ static const unsigned Values[] = {
32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
};
@@ -183,7 +184,7 @@
}
static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
- uint64_t Address, void *Decoder)
+ uint64_t Address, const void *Decoder)
{
MCOperand_CreateImm0(Inst, -(int64_t)Val);
return MCDisassembler_Success;
@@ -233,7 +234,7 @@
#define GET_INSTRINFO_ENUM
#include "XCoreGenInstrInfo.inc"
static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
// Try and decode as a 3R instruction.
unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
@@ -304,7 +305,7 @@
}
static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
@@ -318,7 +319,7 @@
}
static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
@@ -332,7 +333,7 @@
}
static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
@@ -346,7 +347,7 @@
}
static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
@@ -361,7 +362,7 @@
}
static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
@@ -375,7 +376,7 @@
}
static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
@@ -389,7 +390,7 @@
}
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
@@ -404,7 +405,7 @@
}
static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
// Try and decode as a L3R / L2RUS instruction.
unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
@@ -476,7 +477,7 @@
}
static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
@@ -490,7 +491,7 @@
}
static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
@@ -504,7 +505,7 @@
}
static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
@@ -518,7 +519,7 @@
}
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
@@ -532,7 +533,7 @@
}
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
@@ -546,7 +547,7 @@
}
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
@@ -560,7 +561,7 @@
}
static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S =
@@ -575,7 +576,7 @@
}
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S =
@@ -591,7 +592,7 @@
}
static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S =
@@ -606,7 +607,7 @@
}
static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S =
@@ -621,7 +622,7 @@
}
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
DecodeStatus S =
@@ -643,7 +644,7 @@
}
static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Opcode;
@@ -662,7 +663,7 @@
}
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3, Op4, Op5;
DecodeStatus S =
@@ -683,7 +684,7 @@
}
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
@@ -703,7 +704,7 @@
}
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
- void *Decoder)
+ const void *Decoder)
{
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
diff --git a/arch/XCore/XCoreGenAsmWriter.inc b/arch/XCore/XCoreGenAsmWriter.inc
index 95babb2..adddeff 100644
--- a/arch/XCore/XCoreGenAsmWriter.inc
+++ b/arch/XCore/XCoreGenAsmWriter.inc
@@ -268,7 +268,7 @@
0U
};
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0,
/* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0,
/* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0,
@@ -732,12 +732,12 @@
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
-static char *getRegisterName(unsigned RegNo)
+static const char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 17 && "Invalid register number!");
#ifndef CAPSTONE_DIET
- static char AsmStrs[] = {
+ static const char AsmStrs[] = {
/* 0 */ 'r', '1', '0', 0,
/* 4 */ 'r', '0', 0,
/* 7 */ 'r', '1', '1', 0,
diff --git a/arch/XCore/XCoreGenDisassemblerTables.inc b/arch/XCore/XCoreGenDisassemblerTables.inc
index a52afa9..fe4e670 100644
--- a/arch/XCore/XCoreGenDisassemblerTables.inc
+++ b/arch/XCore/XCoreGenDisassemblerTables.inc
@@ -24,7 +24,7 @@
return (insn & fieldMask) >> startBit; \
}
-static uint8_t DecoderTable16[] = {
+static const uint8_t DecoderTable16[] = {
/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
/* 3 */ MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115
/* 7 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
@@ -355,7 +355,7 @@
0
};
-static uint8_t DecoderTable32[] = {
+static const uint8_t DecoderTable32[] = {
/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
/* 3 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96
/* 7 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
@@ -606,7 +606,7 @@
#define DecodeToMCInst(fname,fieldname, InsnType) \
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
- uint64_t Address, void *Decoder) \
+ uint64_t Address, const void *Decoder) \
{ \
InsnType tmp; \
switch (Idx) { \
@@ -766,11 +766,11 @@
}
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
- InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
{ \
uint64_t Bits = getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
+ const uint8_t *Ptr = DecodeTable; \
uint32_t CurFieldValue = 0, ExpectedValue; \
DecodeStatus S = MCDisassembler_Success; \
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
diff --git a/arch/XCore/XCoreGenRegisterInfo.inc b/arch/XCore/XCoreGenRegisterInfo.inc
index 0cdab0a..b73b2fd 100644
--- a/arch/XCore/XCoreGenRegisterInfo.inc
+++ b/arch/XCore/XCoreGenRegisterInfo.inc
@@ -54,11 +54,11 @@
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
-static MCPhysReg XCoreRegDiffLists[] = {
+static const MCPhysReg XCoreRegDiffLists[] = {
/* 0 */ 65535, 0,
};
-static uint16_t XCoreSubRegIdxLists[] = {
+static const uint16_t XCoreSubRegIdxLists[] = {
/* 0 */ 0,
};
@@ -83,22 +83,22 @@
};
// RRegs Register Class...
- static MCPhysReg RRegs[] = {
+ static const MCPhysReg RRegs[] = {
XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR,
};
// RRegs Bit set.
- static uint8_t RRegsBits[] = {
+ static const uint8_t RRegsBits[] = {
0xfe, 0xff, 0x01,
};
// GRRegs Register Class...
- static MCPhysReg GRRegs[] = {
+ static const MCPhysReg GRRegs[] = {
XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11,
};
// GRRegs Bit set.
- static uint8_t GRRegsBits[] = {
+ static const uint8_t GRRegsBits[] = {
0xe0, 0xff, 0x01,
};
diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c
index c9aec94..fcd0205 100644
--- a/arch/XCore/XCoreInstPrinter.c
+++ b/arch/XCore/XCoreInstPrinter.c
@@ -34,7 +34,7 @@
#include "../../MathExtras.h"
#include "XCoreMapping.h"
-static char *getRegisterName(unsigned RegNo);
+static const char *getRegisterName(unsigned RegNo);
void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
@@ -208,17 +208,7 @@
} else if (MCOperand_isImm(MO)) {
int32_t Imm = (int32_t)MCOperand_getImm(MO);
- if (Imm >= 0) {
- if (Imm > HEX_THRESHOLD)
- SStream_concat(O, "0x%x", Imm);
- else
- SStream_concat(O, "%u", Imm);
- } else {
- if (Imm < -HEX_THRESHOLD)
- SStream_concat(O, "-0x%x", -Imm);
- else
- SStream_concat(O, "-%u", -Imm);
- }
+ printInt32(O, Imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
diff --git a/arch/XCore/XCoreMapping.c b/arch/XCore/XCoreMapping.c
index 8c86eb8..e2a4c67 100644
--- a/arch/XCore/XCoreMapping.c
+++ b/arch/XCore/XCoreMapping.c
@@ -13,7 +13,7 @@
#define GET_INSTRINFO_ENUM
#include "XCoreGenInstrInfo.inc"
-static name_map reg_name_maps[] = {
+static const name_map reg_name_maps[] = {
{ XCORE_REG_INVALID, NULL },
{ XCORE_REG_CP, "cp" },
@@ -71,7 +71,7 @@
return 0;
}
-static insn_map insns[] = {
+static const insn_map insns[] = {
// dummy item
{
0, 0,
@@ -114,7 +114,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map insn_name_maps[] = {
+static const name_map insn_name_maps[] = {
{ XCORE_INS_INVALID, NULL },
{ XCORE_INS_ADD, "add" },
@@ -240,7 +240,7 @@
};
// special alias insn
-static name_map alias_insn_names[] = {
+static const name_map alias_insn_names[] = {
{ 0, NULL }
};
#endif
@@ -266,7 +266,7 @@
}
#ifndef CAPSTONE_DIET
-static name_map group_name_maps[] = {
+static const name_map group_name_maps[] = {
{ XCORE_GRP_INVALID, NULL },
{ XCORE_GRP_JUMP, "jump" },
};
@@ -284,7 +284,7 @@
// map internal raw register to 'public' register
xcore_reg XCore_map_register(unsigned int r)
{
- static unsigned int map[] = { 0,
+ static const unsigned int map[] = { 0,
};
if (r < ARR_SIZE(map))
diff --git a/bindings/README b/bindings/README
index a3c7e70..7eb2004 100644
--- a/bindings/README
+++ b/bindings/README
@@ -29,12 +29,24 @@
- Capstone-RS: Rust binding (by Richo Healey).
- https://github.com/richo/capstone-rs
+ https://github.com/capstone-rust/capstone-rs
- Capstone.NET: .NET framework binding (by Ahmed Garhy).
https://github.com/9ee1/Capstone.NET
+- CapstoneJ: High level Java wrapper for Capstone-java (by Keve Müller).
+
+ https://github.com/kevemueller/capstonej
+
+- Hapstone: Haskell binding (by ibabushkin)
+
+ https://github.com/ibabushkin/hapstone
+
+- Emacs-capstone: Emacs (elisp) binding (by Bas Alberts)
+
+ https://github.com/collarchoke/emacs-capstone
+
- C# binding (by Matt Graeber). Note: this is only for Capstone v2.0.
https://github.com/mattifestation/capstone
diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index 2c76090..84cff65 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -78,6 +78,7 @@
def gen(lang):
global include, INCL_DIR
+ print('Generating bindings for', lang)
templ = template[lang]
print('Generating bindings for', lang)
for target in include:
diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java
index 88c3ba2..668d0de 100644
--- a/bindings/java/capstone/Capstone.java
+++ b/bindings/java/capstone/Capstone.java
@@ -521,11 +521,11 @@
PointerByReference insnRef = new PointerByReference();
NativeLong c = cs.cs_disasm(ns.csh, code, new NativeLong(code.length), address, new NativeLong(count), insnRef);
-
+
if (0 == c.intValue()) {
- return EMPTY_INSN;
+ return EMPTY_INSN;
}
-
+
Pointer p = insnRef.getValue();
_cs_insn byref = new _cs_insn(p);
diff --git a/bindings/java/capstone/Ppc_const.java b/bindings/java/capstone/Ppc_const.java
index 91407bc..ef8359c 100644
--- a/bindings/java/capstone/Ppc_const.java
+++ b/bindings/java/capstone/Ppc_const.java
@@ -23,14 +23,6 @@
public static final int PPC_BH_PLUS = 1;
public static final int PPC_BH_MINUS = 2;
- // Operand type for instruction's operands
-
- public static final int PPC_OP_INVALID = 0;
- public static final int PPC_OP_REG = 1;
- public static final int PPC_OP_IMM = 2;
- public static final int PPC_OP_MEM = 3;
- public static final int PPC_OP_CRX = 64;
-
// PPC registers
public static final int PPC_REG_INVALID = 0;
@@ -245,6 +237,14 @@
public static final int PPC_REG_X2 = 209;
public static final int PPC_REG_ENDING = 210;
+ // Operand type for instruction's operands
+
+ public static final int PPC_OP_INVALID = 0;
+ public static final int PPC_OP_REG = 1;
+ public static final int PPC_OP_IMM = 2;
+ public static final int PPC_OP_MEM = 3;
+ public static final int PPC_OP_CRX = 64;
+
// PPC instruction
public static final int PPC_INS_INVALID = 0;
diff --git a/bindings/ocaml/ppc_const.ml b/bindings/ocaml/ppc_const.ml
index 9dde83c..da294a2 100644
--- a/bindings/ocaml/ppc_const.ml
+++ b/bindings/ocaml/ppc_const.ml
@@ -20,14 +20,6 @@
let _PPC_BH_PLUS = 1;;
let _PPC_BH_MINUS = 2;;
-(* Operand type for instruction's operands *)
-
-let _PPC_OP_INVALID = 0;;
-let _PPC_OP_REG = 1;;
-let _PPC_OP_IMM = 2;;
-let _PPC_OP_MEM = 3;;
-let _PPC_OP_CRX = 64;;
-
(* PPC registers *)
let _PPC_REG_INVALID = 0;;
@@ -242,6 +234,14 @@
let _PPC_REG_X2 = 209;;
let _PPC_REG_ENDING = 210;;
+(* Operand type for instruction's operands *)
+
+let _PPC_OP_INVALID = 0;;
+let _PPC_OP_REG = 1;;
+let _PPC_OP_IMM = 2;;
+let _PPC_OP_MEM = 3;;
+let _PPC_OP_CRX = 64;;
+
(* PPC instruction *)
let _PPC_INS_INVALID = 0;;
diff --git a/bindings/powershell/Capstone/Capstone.psd1 b/bindings/powershell/Capstone/Capstone.psd1
new file mode 100755
index 0000000..f7b1f4c
--- /dev/null
+++ b/bindings/powershell/Capstone/Capstone.psd1
@@ -0,0 +1,25 @@
+@{
+# Script module or binary module file associated with this manifest.
+ModuleToProcess = 'Capstone.psm1'
+
+# Version number of this module.
+ModuleVersion = '0.0.0.1'
+
+# ID used to uniquely identify this module
+GUID = 'd34db33f-9958-436d-a2d8-a77844a2bda5'
+
+# Author of this module
+Author = 'Ruben Boonen'
+
+# Copyright statement for this module
+Copyright = 'BSD 3-Clause'
+
+# Description of the functionality provided by this module
+Description = 'Capstone Engine Binding Module'
+
+# Minimum version of the Windows PowerShell engine required by this module
+PowerShellVersion = '2.0'
+
+# Functions to export from this module
+FunctionsToExport = '*'
+}
diff --git a/bindings/powershell/Capstone/Capstone.psm1 b/bindings/powershell/Capstone/Capstone.psm1
new file mode 100755
index 0000000..3a13cdd
--- /dev/null
+++ b/bindings/powershell/Capstone/Capstone.psm1
@@ -0,0 +1,442 @@
+function Get-CapstoneDisassembly {
+<#
+.SYNOPSIS
+ Powershell wrapper for Capstone (using inline C#).
+
+.DESCRIPTION
+ Author: Ruben Boonen (@FuzzySec)
+ License: BSD 3-Clause
+ Required Dependencies: None
+ Optional Dependencies: None
+
+.PARAMETER Architecture
+ Architecture type.
+
+.PARAMETER Mode
+ Mode type.
+
+.PARAMETER Bytes
+ Byte array to be disassembled.
+
+.PARAMETER Syntax
+ Syntax for output assembly.
+
+.PARAMETER Address
+ Assign address for the first instruction to be disassembled.
+
+.PARAMETER Detailed
+ Return detailed output.
+
+.PARAMETER Version
+ Print ASCII version banner.
+
+.EXAMPLE
+
+ C:\PS> $Bytes = [Byte[]] @( 0x10, 0xf1, 0x10, 0xe7, 0x11, 0xf2, 0x31, 0xe7, 0xdc, 0xa1, 0x2e, 0xf3, 0xe8, 0x4e, 0x62, 0xf3 )
+ C:\PS> Get-CapstoneDisassembly -Architecture CS_ARCH_ARM -Mode CS_MODE_ARM -Bytes $Bytes
+
+ sdiv r0, r0, r1
+ udiv r1, r1, r2
+ vbit q5, q15, q6
+ vcgt.f32 q10, q9, q12
+
+.EXAMPLE
+
+ # Detailed mode & ATT syntax
+ C:\PS> $Bytes = [Byte[]] @( 0xB8, 0x0A, 0x00, 0x00, 0x00, 0xF7, 0xF3 )
+ C:\PS> Get-CapstoneDisassembly -Architecture CS_ARCH_X86 -Mode CS_MODE_32 -Bytes $Bytes -Syntax ATT -Detailed
+
+ Size : 5
+ Address : 0x100000
+ Mnemonic : movl
+ Operands : $0xa, %eax
+ Bytes : {184, 10, 0, 0...}
+ RegRead :
+ RegWrite :
+
+ Size : 2
+ Address : 0x100005
+ Mnemonic : divl
+ Operands : %ebx
+ Bytes : {247, 243, 0, 0...}
+ RegRead : {eax, edx}
+ RegWrite : {eax, edx, eflags}
+
+.EXAMPLE
+
+ # Get-CapstoneDisassembly emits objects
+ C:\PS> $Bytes = [Byte[]] @( 0xB8, 0x0A, 0x00, 0x00, 0x00, 0xF7, 0xF3 )
+ C:\PS> $Object = Get-CapstoneDisassembly -Architecture CS_ARCH_X86 -Mode CS_MODE_32 -Bytes $Bytes -Detailed
+ C:\PS> $Object |Select-Object Size,Mnemonic,Operands
+
+ Size Mnemonic Operands
+ ---- -------- --------
+ 5 mov eax, 0xa
+ 2 div ebx
+
+#>
+
+ param(
+ [Parameter(ParameterSetName='Capstone', Mandatory = $True)]
+ [ValidateSet(
+ 'CS_ARCH_ARM',
+ 'CS_ARCH_ARM64',
+ 'CS_ARCH_MIPS',
+ 'CS_ARCH_X86',
+ 'CS_ARCH_PPC',
+ 'CS_ARCH_SPARC',
+ 'CS_ARCH_SYSZ',
+ 'CS_ARCH_XCORE',
+ 'CS_ARCH_MAX',
+ 'CS_ARCH_ALL')
+ ]
+ [String]$Architecture,
+
+ [Parameter(ParameterSetName='Capstone', Mandatory = $True)]
+ [ValidateSet(
+ 'CS_MODE_LITTLE_ENDIAN',
+ 'CS_MODE_ARM',
+ 'CS_MODE_16',
+ 'CS_MODE_32',
+ 'CS_MODE_64',
+ 'CS_MODE_THUMB',
+ 'CS_MODE_MCLASS',
+ 'CS_MODE_V8',
+ 'CS_MODE_MICRO',
+ 'CS_MODE_MIPS3',
+ 'CS_MODE_MIPS32R6',
+ 'CS_MODE_MIPSGP64',
+ 'CS_MODE_V9',
+ 'CS_MODE_BIG_ENDIAN',
+ 'CS_MODE_MIPS32',
+ 'CS_MODE_MIPS64')
+ ]
+ [String]$Mode,
+
+ [Parameter(ParameterSetName='Capstone', Mandatory = $True)]
+ [ValidateNotNullOrEmpty()]
+ [Byte[]]$Bytes,
+
+ [Parameter(ParameterSetName='Capstone', Mandatory = $False)]
+ [ValidateSet(
+ 'Intel',
+ 'ATT')
+ ]
+ [String]$Syntax = "Intel",
+
+ [Parameter(ParameterSetName='Capstone', Mandatory = $False)]
+ [UInt64]$Address = 0x100000,
+
+ [Parameter(ParameterSetName='Capstone', Mandatory = $False)]
+ [switch]$Detailed = $null,
+
+ [Parameter(ParameterSetName='Version', Mandatory = $False)]
+ [switch]$Version = $null
+ )
+
+ # Compatibility for PS v2 / PS v3+
+ if(!$PSScriptRoot) {
+ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent
+ }
+
+ # Set the capstone DLL path
+ $DllPath = $($PSScriptRoot + '\Lib\Capstone\capstone.dll').Replace('\','\\')
+
+ # Make sure the user didn't forget the DLL
+ if (![IO.File]::Exists($DllPath)) {
+ echo "`n[!] Missing Capstone DLL"
+ echo "[>] Quitting!`n"
+ Return
+ }
+
+ # Inline C# to parse the unmanaged capstone DLL
+ Add-Type -TypeDefinition @"
+ using System;
+ using System.Diagnostics;
+ using System.Runtime.InteropServices;
+ using System.Security.Principal;
+
+ [StructLayout(LayoutKind.Sequential)]
+ public struct cs_insn
+ {
+ public uint id;
+ public ulong address;
+ public ushort size;
+ [MarshalAs(UnmanagedType.ByValArray, SizeConst = 16)]
+ public byte[] bytes;
+ [MarshalAs(UnmanagedType.ByValTStr, SizeConst = 32)]
+ public string mnemonic;
+ [MarshalAs(UnmanagedType.ByValTStr, SizeConst = 160)]
+ public string operands;
+ public IntPtr detail;
+ }
+
+ /// Partial, only architecture-independent internal data
+ [StructLayout(LayoutKind.Sequential)]
+ public struct cs_detail
+ {
+ [MarshalAs(UnmanagedType.ByValArray, SizeConst = 12)]
+ public byte[] regs_read;
+ public byte regs_read_count;
+ [MarshalAs(UnmanagedType.ByValArray, SizeConst = 20)]
+ public byte[] regs_write;
+ public byte regs_write_count;
+ [MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
+ public byte[] groups;
+ public byte groups_count;
+ }
+
+ public enum cs_err : int
+ {
+ CS_ERR_OK = 0, /// No error: everything was fine
+ CS_ERR_MEM, /// Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
+ CS_ERR_ARCH, /// Unsupported architecture: cs_open()
+ CS_ERR_HANDLE, /// Invalid handle: cs_op_count(), cs_op_index()
+ CS_ERR_CSH, /// Invalid csh argument: cs_close(), cs_errno(), cs_option()
+ CS_ERR_MODE, /// Invalid/unsupported mode: cs_open()
+ CS_ERR_OPTION, /// Invalid/unsupported option: cs_option()
+ CS_ERR_DETAIL, /// Information is unavailable because detail option is OFF
+ CS_ERR_MEMSETUP, /// Dynamic memory management uninitialized (see CS_OPT_MEM)
+ CS_ERR_VERSION, /// Unsupported version (bindings)
+ CS_ERR_DIET, /// Access irrelevant data in "diet" engine
+ CS_ERR_SKIPDATA, /// Access irrelevant data for "data" instruction in SKIPDATA mode
+ CS_ERR_X86_ATT, /// X86 AT&T syntax is unsupported (opt-out at compile time)
+ CS_ERR_X86_INTEL, /// X86 Intel syntax is unsupported (opt-out at compile time)
+ }
+ public enum cs_arch : int
+ {
+ CS_ARCH_ARM = 0, /// ARM architecture (including Thumb, Thumb-2)
+ CS_ARCH_ARM64, /// ARM-64, also called AArch64
+ CS_ARCH_MIPS, /// Mips architecture
+ CS_ARCH_X86, /// X86 architecture (including x86 & x86-64)
+ CS_ARCH_PPC, /// PowerPC architecture
+ CS_ARCH_SPARC, /// Sparc architecture
+ CS_ARCH_SYSZ, /// SystemZ architecture
+ CS_ARCH_XCORE, /// XCore architecture
+ CS_ARCH_MAX,
+ CS_ARCH_ALL = 0xFFFF, /// All architectures - for cs_support()
+ }
+ public enum cs_mode : int
+ {
+ CS_MODE_LITTLE_ENDIAN = 0, /// little-endian mode (default mode)
+ CS_MODE_ARM = 0, /// 32-bit ARM
+ CS_MODE_16 = 1 << 1, /// 16-bit mode (X86)
+ CS_MODE_32 = 1 << 2, /// 32-bit mode (X86)
+ CS_MODE_64 = 1 << 3, /// 64-bit mode (X86, PPC)
+ CS_MODE_THUMB = 1 << 4, /// ARM's Thumb mode, including Thumb-2
+ CS_MODE_MCLASS = 1 << 5, /// ARM's Cortex-M series
+ CS_MODE_V8 = 1 << 6, /// ARMv8 A32 encodings for ARM
+ CS_MODE_MICRO = 1 << 4, /// MicroMips mode (MIPS)
+ CS_MODE_MIPS3 = 1 << 5, /// Mips III ISA
+ CS_MODE_MIPS32R6 = 1 << 6, /// Mips32r6 ISA
+ CS_MODE_MIPSGP64 = 1 << 7, /// General Purpose Registers are 64-bit wide (MIPS)
+ CS_MODE_V9 = 1 << 4, /// SparcV9 mode (Sparc)
+ CS_MODE_BIG_ENDIAN = 1 << 31, /// big-endian mode
+ CS_MODE_MIPS32 = CS_MODE_32, /// Mips32 ISA (Mips)
+ CS_MODE_MIPS64 = CS_MODE_64, /// Mips64 ISA (Mips)
+ }
+
+ public static class Capstone
+ {
+ [DllImport("$DllPath")]
+ public static extern cs_err cs_open(
+ cs_arch arch,
+ cs_mode mode,
+ ref IntPtr handle);
+
+ [DllImport("$DllPath")]
+ public static extern UInt32 cs_disasm(
+ IntPtr handle,
+ byte[] code,
+ int code_size,
+ ulong address,
+ int count,
+ ref IntPtr insn);
+
+ [DllImport("$DllPath")]
+ public static extern bool cs_free(
+ IntPtr insn,
+ int count);
+
+ [DllImport("$DllPath")]
+ public static extern cs_err cs_close(
+ ref IntPtr handle);
+
+ [DllImport("$DllPath")]
+ public static extern cs_err cs_option(
+ IntPtr handle,
+ int type,
+ int value);
+
+ [DllImport("$DllPath", CallingConvention = CallingConvention.Cdecl)]
+ public static extern IntPtr cs_reg_name(
+ IntPtr handle,
+ uint reg_id);
+
+ [DllImport("$DllPath")]
+ public static extern int cs_version(
+ uint major,
+ uint minor);
+ }
+"@
+
+ if ($Version){
+ $VerCount = [System.BitConverter]::GetBytes($([Capstone]::cs_version($null,$null)))
+ $Banner = @"
+
+ (((;
+ (; "((((\
+ ;((((((; "((((;
+ ((((""\(((( "((((
+ ((((" ((\ "(((( "(((\
+ ;(((/ ((((((( "(((( \(((
+ ((((" (((* "(((( \(((;"(((\
+ ((((";((("/(( \(((;"(((\"(((\
+ (((( (((( ((((" "(((\ ((() (((\
+ ;((("(((( (((* **"" ((()"(((;
+ (((" ((( (((( ((((((((((((((:*(((
+ (((( (((*)((( ********"""" ;;(((((;
+ (((* ((( (((((((((((((((((((((*"" (
+ ((("(((( """***********"""" ;;(((((
+ "" (((((((((((((((((((((((((((*""
+ """****(((((****"""
+
+ -=[Capstone Engine v$($VerCount[1]).$($VerCount[0])]=-
+
+"@
+ # Mmm ASCII version banner!
+ $Banner
+ Return
+ }
+
+ # Disasm Handle
+ $DisAsmHandle = [IntPtr]::Zero
+
+ # Initialize Capstone with cs_open()
+ $CallResult = [Capstone]::cs_open($Architecture,$Mode,[ref]$DisAsmHandle)
+ if ($CallResult -ne "CS_ERR_OK") {
+ if ($CallResult -eq "CS_ERR_MODE"){
+ echo "`n[!] Invalid Architecture/Mode combination"
+ echo "[>] Quitting..`n"
+ } else {
+ echo "`n[!] cs_open error: $CallResult"
+ echo "[>] Quitting..`n"
+ }
+ Return
+ }
+
+ # Set disassembly syntax
+ #---
+ # cs_opt_type -> CS_OPT_SYNTAX = 1
+ #---
+ # cs_opt_value -> CS_OPT_SYNTAX_INTEL = 1
+ # -> CS_OPT_SYNTAX_ATT = 2
+ if ($Syntax -eq "Intel") {
+ $CS_OPT_SYNTAX = 1
+ } else {
+ $CS_OPT_SYNTAX = 2
+ }
+ $CallResult = [Capstone]::cs_option($DisAsmHandle, 1, $CS_OPT_SYNTAX)
+ if ($CallResult -ne "CS_ERR_OK") {
+ echo "`n[!] cs_option error: $CallResult"
+ echo "[>] Quitting..`n"
+ $CallResult = [Capstone]::cs_close([ref]$DisAsmHandle)
+ Return
+ }
+
+ # Set disassembly detail
+ #---
+ # cs_opt_type -> CS_OPT_DETAIL = 2
+ #---
+ # cs_opt_value -> CS_OPT_ON = 3
+ # -> CS_OPT_OFF = 0
+ if ($Detailed) {
+ $CS_OPT = 3
+ } else {
+ $CS_OPT = 0
+ }
+ $CallResult = [Capstone]::cs_option($DisAsmHandle, 2, $CS_OPT)
+ if ($CallResult -ne "CS_ERR_OK") {
+ echo "`n[!] cs_option error: $CallResult"
+ echo "[>] Quitting..`n"
+ $CallResult = [Capstone]::cs_close([ref]$DisAsmHandle)
+ Return
+ }
+
+ # Out Buffer Handle
+ $InsnHandle = [IntPtr]::Zero
+
+ # Disassemble bytes
+ $Count = [Capstone]::cs_disasm($DisAsmHandle, $Bytes, $Bytes.Count, $Address, 0, [ref]$InsnHandle)
+
+ if ($Count -gt 0) {
+ # Result Array
+ $Disasm = @()
+
+ # Result struct
+ $cs_insn = New-Object cs_insn
+ $cs_insn_size = [System.Runtime.InteropServices.Marshal]::SizeOf($cs_insn)
+ $cs_insn = $cs_insn.GetType()
+
+ # Result detail struct
+ $cs_detail = New-Object cs_detail
+ $cs_detail = $cs_detail.GetType()
+
+ # Result buffer offset
+ $BuffOffset = $InsnHandle.ToInt64()
+
+ for ($i=0; $i -lt $Count; $i++) {
+ # Cast Offset to cs_insn
+ $InsnPointer = New-Object System.Intptr -ArgumentList $BuffOffset
+ $Cast = [system.runtime.interopservices.marshal]::PtrToStructure($InsnPointer,[type]$cs_insn)
+
+ if ($CS_OPT -eq 0) {
+ $HashTable = @{
+ Address = echo "0x$("{0:X}" -f $Cast.address)"
+ Instruction = echo "$($Cast.mnemonic) $($Cast.operands)"
+ }
+ $Object = New-Object PSObject -Property $HashTable
+ $Disasm += $Object |Select-Object Address,Instruction
+ } else {
+ $DetailCast = [system.runtime.interopservices.marshal]::PtrToStructure($Cast.detail,[type]$cs_detail)
+ if($DetailCast.regs_read_count -gt 0) {
+ $RegRead = @()
+ for ($r=0; $r -lt $DetailCast.regs_read_count; $r++) {
+ $NamePointer = [Capstone]::cs_reg_name($DisAsmHandle, $DetailCast.regs_read[$r])
+ $RegRead += [System.Runtime.InteropServices.Marshal]::PtrToStringAnsi($NamePointer)
+ }
+ }
+ if ($DetailCast.regs_write_count -gt 0) {
+ $RegWrite = @()
+ for ($r=0; $r -lt $DetailCast.regs_write_count; $r++) {
+ $NamePointer = [Capstone]::cs_reg_name($DisAsmHandle, $DetailCast.regs_write[$r])
+ $RegWrite += [System.Runtime.InteropServices.Marshal]::PtrToStringAnsi($NamePointer)
+ }
+ }
+ $HashTable = @{
+ Address = echo "0x$("{0:X}" -f $Cast.address)"
+ Mnemonic = $Cast.mnemonic
+ Operands = $Cast.operands
+ Bytes = $Cast.bytes
+ Size = $Cast.size
+ RegRead = $RegRead
+ RegWrite = $RegWrite
+ }
+ $Object = New-Object PSObject -Property $HashTable
+ $Disasm += $Object |Select-Object Size,Address,Mnemonic,Operands,Bytes,RegRead,RegWrite
+ }
+ $BuffOffset = $BuffOffset + $cs_insn_size
+ }
+ } else {
+ echo "`n[!] Disassembly Failed"
+ echo "[>] Quitting..`n"
+ $CallResult = [Capstone]::cs_close([ref]$DisAsmHandle)
+ Return
+ }
+
+ # Print result
+ $Disasm
+
+ # Free Buffer Handle
+ $CallResult = [Capstone]::cs_free($InsnHandle, $Count)
+}
\ No newline at end of file
diff --git a/bindings/powershell/Capstone/Lib/Capstone/.gitignore b/bindings/powershell/Capstone/Lib/Capstone/.gitignore
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/bindings/powershell/Capstone/Lib/Capstone/.gitignore
diff --git a/bindings/powershell/README.md b/bindings/powershell/README.md
new file mode 100755
index 0000000..1197a31
--- /dev/null
+++ b/bindings/powershell/README.md
@@ -0,0 +1,30 @@
+This documentation explains how to install & use the PowerShell binding for Capstone.
+
+
+Install
+------
+
+Compile the relevant version (x86/x64) of `capstone.dll` and place it in
+`./Capstone/Lib/Capstone/`.
+
+Alternatively, pre-compiled DLL’s can be obtained from the Capstone homepage
+at http://capstone-engine.org/download
+
+
+Usage
+-----
+
+To use the PowerShell binding, the entire Capstone folder should be added to
+one of the PowerShell module directories:
+
+ # Global PSModulePath path
+ %Windir%\System32\WindowsPowerShell\v1.0\Modules
+
+ # User PSModulePath path
+ %UserProfile%\Documents\WindowsPowerShell\Modules
+
+Once this is done the module can be initialized by typing “Import-Module Capstone”
+in a new PowerShell terminal. Further information on the usage of the binding
+can be obtained with the following command:
+
+ Get-Help Get-CapstoneDisassembly -Full
\ No newline at end of file
diff --git a/bindings/python/Makefile b/bindings/python/Makefile
index b38a4a4..d50420b 100644
--- a/bindings/python/Makefile
+++ b/bindings/python/Makefile
@@ -67,6 +67,7 @@
TESTS = test_basic.py test_detail.py test_arm.py test_arm64.py test_m68k.py test_mips.py
TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py test_m680x.py test_skipdata.py
+
check:
@for t in $(TESTS); do \
echo Check $$t ... ; \
diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py
index b42433a..893c588 100644
--- a/bindings/python/capstone/ppc_const.py
+++ b/bindings/python/capstone/ppc_const.py
@@ -20,14 +20,6 @@
PPC_BH_PLUS = 1
PPC_BH_MINUS = 2
-# Operand type for instruction's operands
-
-PPC_OP_INVALID = 0
-PPC_OP_REG = 1
-PPC_OP_IMM = 2
-PPC_OP_MEM = 3
-PPC_OP_CRX = 64
-
# PPC registers
PPC_REG_INVALID = 0
@@ -242,6 +234,14 @@
PPC_REG_X2 = 209
PPC_REG_ENDING = 210
+# Operand type for instruction's operands
+
+PPC_OP_INVALID = 0
+PPC_OP_REG = 1
+PPC_OP_IMM = 2
+PPC_OP_MEM = 3
+PPC_OP_CRX = 64
+
# PPC instruction
PPC_INS_INVALID = 0
diff --git a/bindings/python/setup.py b/bindings/python/setup.py
index c552030..575d581 100755
--- a/bindings/python/setup.py
+++ b/bindings/python/setup.py
@@ -144,6 +144,7 @@
os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh")
shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE))
+
# only copy static library if it exists (it's a build option)
if STATIC_LIBRARY_FILE and os.path.exists(STATIC_LIBRARY_FILE):
shutil.copy(STATIC_LIBRARY_FILE, LIBS_DIR)
diff --git a/bindings/python/test_all.py b/bindings/python/test_all.py
index 7e41d8a..9f4521e 100755
--- a/bindings/python/test_all.py
+++ b/bindings/python/test_all.py
@@ -4,7 +4,6 @@
test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \
test_m680x
-
test_basic.test_class()
test_arm.test_class()
test_arm64.test_class()
diff --git a/bindings/vb6/CDisassembler.cls b/bindings/vb6/CDisassembler.cls
new file mode 100644
index 0000000..c390d58
--- /dev/null
+++ b/bindings/vb6/CDisassembler.cls
@@ -0,0 +1,153 @@
+VERSION 1.0 CLASS
+BEGIN
+ MultiUse = -1 'True
+ Persistable = 0 'NotPersistable
+ DataBindingBehavior = 0 'vbNone
+ DataSourceBehavior = 0 'vbNone
+ MTSTransactionMode = 0 'NotAnMTSObject
+END
+Attribute VB_Name = "CDisassembler"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = True
+Attribute VB_PredeclaredId = False
+Attribute VB_Exposed = False
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+
+'NOTE: the VB code was built and tested against Capstone v3.0 rc4
+' if the capstone C structures change, the VB code will have to
+' be adjusted to match!
+'
+' instructions details are currently only implemented for x86
+
+Public arch As cs_arch
+Public mode As cs_mode
+Public hCapstone As Long
+Public hLib As Long
+
+Public version As String
+Public vMajor As Long
+Public vMinor As Long
+
+Public errMsg As String
+Public lastErr As cs_err
+
+Private Function CheckPath(pth As String) As Long
+
+ Dim hCap As Long, capPth As String, shimPth As String
+
+ shimPth = pth & "\vbCapstone.dll"
+ capPth = pth & "\capstone.dll"
+
+ If Not FileExists(shimPth) Then Exit Function
+
+ hCap = LoadLibrary(capPth)
+ If hCap = 0 Then hCap = LoadLibrary("capstone.dll")
+ If hCap = 0 Then errMsg = "Could not find capstone.dll"
+
+ CheckPath = LoadLibrary(shimPth)
+ 'If CheckPath = 0 Then MsgBox Err.LastDllError
+
+End Function
+
+Public Function init(arch As cs_arch, mode As cs_mode, Optional enableDetails As Boolean = False) As Boolean
+
+ errMsg = Empty
+ hLib = GetModuleHandle("vbCapstone.dll")
+
+ If hLib = 0 Then hLib = CheckPath(App.path & "\bin\")
+ If hLib = 0 Then hLib = CheckPath(App.path & "\")
+ If hLib = 0 Then hLib = CheckPath(App.path & "\..\")
+ If hLib = 0 Then hLib = LoadLibrary("vbCapstone.dll")
+
+ If hLib = 0 Then
+ errMsg = errMsg & " Could not load vbCapstone.dll"
+ Exit Function
+ End If
+
+ Me.arch = arch
+ Me.mode = mode
+
+ cs_version vMajor, vMinor
+ version = vMajor & "." & vMinor
+
+ If cs_support(arch) = 0 Then
+ errMsg = "specified architecture not supported"
+ Exit Function
+ End If
+
+ Dim handle As Long 'in vb class a public var is actually a property get/set can not use as byref to api..
+ lastErr = cs_open(arch, mode, handle)
+ If lastErr <> CS_ERR_OK Then
+ errMsg = err2str(lastErr)
+ Exit Function
+ End If
+
+ hCapstone = handle
+ If enableDetails Then 'vb bindings currently only support details for x86
+ If arch = CS_ARCH_X86 Then
+ cs_option handle, CS_OPT_DETAIL, CS_OPT_ON
+ End If
+ End If
+
+ init = True
+
+End Function
+
+'base is a variant and currently accepts the following input types:
+' x64 number held as currency type (ex. makeCur(&haabbccdd, &h11223344) )
+' int/long value (ex. &h1000 or 12345)
+' numeric string or 0x/&h prefixed hex string (ex. "12345", "0x1200", "&haabbccdd")
+Function disasm(ByVal base, code() As Byte, Optional count As Long = 0) As Collection
+
+ Dim c As Long
+ Dim instAry As Long
+ Dim ret As New Collection
+ Dim ci As CInstruction
+ Dim i As Long
+ Dim address As Currency
+
+ On Error Resume Next
+
+ Set disasm = ret
+
+ If TypeName(base) = "Currency" Then
+ address = base
+ Else
+ If TypeName(base) = "String" Then base = Replace(Trim(base), "0x", "&h")
+ address = lng2Cur(CLng(base))
+ If Err.Number <> 0 Then
+ errMsg = "Could not convert base address to long"
+ Exit Function
+ End If
+ End If
+
+ c = cs_disasm(Me.hCapstone, code(0), UBound(code) + 1, address, count, instAry)
+ If c = 0 Then Exit Function
+
+ For i = 0 To c - 1
+ Set ci = New CInstruction
+ ci.LoadInstruction instAry, i, Me
+ ret.Add ci
+ Next
+
+ cs_free instAry, c
+
+End Function
+
+
+Private Sub Class_Terminate()
+ Dim msg As String
+ If DEBUG_DUMP Then
+ msg = "CDissembler.Terminate " & Hex(hCapstone)
+ If hCapstone <> 0 Then lastErr = cs_close(hCapstone)
+ Debug.Print msg & " : " & lastErr
+ End If
+End Sub
+
diff --git a/bindings/vb6/CInstDetails.cls b/bindings/vb6/CInstDetails.cls
new file mode 100644
index 0000000..c6e0b20
--- /dev/null
+++ b/bindings/vb6/CInstDetails.cls
@@ -0,0 +1,119 @@
+VERSION 1.0 CLASS
+BEGIN
+ MultiUse = -1 'True
+ Persistable = 0 'NotPersistable
+ DataBindingBehavior = 0 'vbNone
+ DataSourceBehavior = 0 'vbNone
+ MTSTransactionMode = 0 'NotAnMTSObject
+END
+Attribute VB_Name = "CInstDetails"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = True
+Attribute VB_PredeclaredId = False
+Attribute VB_Exposed = False
+Option Explicit
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+'Public Type cs_detail
+' regs_read(0 To 11) As Byte ' list of implicit registers read by this insn UNSIGNED
+' regs_read_count As Byte ' number of implicit registers read by this insn UNSIGNED
+' regs_write(0 To 19) As Byte ' list of implicit registers modified by this insn UNSIGNED
+' regs_write_count As Byte ' number of implicit registers modified by this insn UNSIGNED
+' groups(0 To 7) As Byte ' list of group this instruction belong to UNSIGNED
+' groups_count As Byte ' number of groups this insn belongs to UNSIGNED
+'
+' // Architecture-specific instruction info
+' union {
+' cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
+' cs_arm64 arm64; // ARM64 architecture (aka AArch64)
+' cs_arm arm; // ARM architecture (including Thumb/Thumb2)
+' cs_mips mips; // MIPS architecture
+' cs_ppc ppc; // PowerPC architecture
+' cs_sparc sparc; // Sparc architecture
+' cs_sysz sysz; // SystemZ architecture
+' cs_xcore xcore; // XCore architecture
+' };
+'} cs_detail;
+
+Public regRead As New Collection
+Public regWritten As New Collection
+Public groups As New Collection
+Public parent As CDisassembler
+
+'this will be set to a class of the specific instruction info type by architecture..
+Public info As Object
+
+Private m_raw() As Byte
+
+Function toString() As String
+
+ On Error Resume Next
+
+ Dim ret() As String
+ Dim v, tmp
+
+ push ret, "Instruction details: "
+ push ret, String(40, "-")
+
+ If DEBUG_DUMP Then
+ push ret, "Raw: "
+ push ret, HexDump(m_raw)
+ End If
+
+ push ret, "Registers Read: " & regRead.count & IIf(regRead.count > 0, " Values: " & col2Str(regRead), Empty)
+ push ret, "Registers Written: " & regWritten.count & IIf(regWritten.count > 0, " Values: " & col2Str(regWritten), Empty)
+ push ret, "Groups: " & groups.count & IIf(groups.count > 0, " Values: " & col2Str(groups), Empty)
+
+ 'it is expected that each CXXInst class implements a toString() method..if not we catch the error anyway..
+ If Not info Is Nothing Then
+ push ret, info.toString()
+ End If
+
+ toString = Join(ret, vbCrLf)
+
+End Function
+
+Friend Sub LoadDetails(lpDetails As Long, parent As CDisassembler)
+
+ Dim cd As cs_detail
+ Dim i As Long
+ Dim x86 As CX86Inst
+
+ Set Me.parent = parent
+
+ 'vbdef only contains up to the groups_count field..
+ CopyMemory ByVal VarPtr(cd), ByVal lpDetails, LenB(cd)
+
+ If DEBUG_DUMP Then
+ ReDim m_raw(LenB(cd))
+ CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpDetails, LenB(cd)
+ End If
+
+ For i = 1 To cd.regs_read_count
+ regRead.Add cd.regs_read(i - 1)
+ Next
+
+ For i = 1 To cd.regs_write_count
+ regWritten.Add cd.regs_write(i - 1)
+ Next
+
+ For i = 1 To cd.groups_count
+ groups.Add cd.groups(i - 1)
+ Next
+
+ Const align = 5
+
+ 'each arch needs its own CxxInstr class implemented here...
+ If parent.arch = CS_ARCH_X86 Then
+ Set x86 = New CX86Inst
+ x86.LoadDetails lpDetails + LenB(cd) + align, parent
+ Set info = x86
+ End If
+
+
+
+End Sub
diff --git a/bindings/vb6/CInstruction.cls b/bindings/vb6/CInstruction.cls
new file mode 100644
index 0000000..6463237
--- /dev/null
+++ b/bindings/vb6/CInstruction.cls
@@ -0,0 +1,133 @@
+VERSION 1.0 CLASS
+BEGIN
+ MultiUse = -1 'True
+ Persistable = 0 'NotPersistable
+ DataBindingBehavior = 0 'vbNone
+ DataSourceBehavior = 0 'vbNone
+ MTSTransactionMode = 0 'NotAnMTSObject
+END
+Attribute VB_Name = "CInstruction"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = True
+Attribute VB_PredeclaredId = False
+Attribute VB_Exposed = False
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+
+'Public Type cs_insn
+' ' Instruction ID (basically a numeric ID for the instruction mnemonic)
+' ' Find the instruction id in the '[ARCH]_insn' enum in the header file
+' ' of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
+' ' 'x86_insn' in x86.h for X86, etc...
+' ' available even when CS_OPT_DETAIL = CS_OPT_OFF
+' ' NOTE: in Skipdata mode, "data" instruction has 0 for this id field. UNSIGNED
+' id As Long '
+' align As Long 'not sure why it needs this..but it does..
+' address As Currency ' Address (EIP) of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED
+' size As Integer ' Size of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED
+' bytes(0 To 15) As Byte ' Machine bytes of this instruction, with number of bytes indicated by @size above available even when CS_OPT_DETAIL = CS_OPT_OFF
+' mnemonic(0 To 31) As Byte ' Ascii text of instruction mnemonic available even when CS_OPT_DETAIL = CS_OPT_OFF
+' op_str(0 To 159) As Byte ' Ascii text of instruction operands available even when CS_OPT_DETAIL = CS_OPT_OFF
+'
+' ' Pointer to cs_detail.
+' ' NOTE: detail pointer is only valid when both requirements below are met:
+' ' (1) CS_OP_DETAIL = CS_OPT_ON
+' ' (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
+' ' NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
+' ' is not NULL, its content is still irrelevant.
+' lpDetail As Long ' points to a cs_detail structure NOTE: only available when CS_OPT_DETAIL = CS_OPT_ON
+'
+'End Type
+
+Public ID As Long
+Public address As Currency
+Public size As Long
+Private m_bytes() As Byte
+Public instruction As String
+Public operand As String
+Public lpDetails As Long
+Public parent As CDisassembler
+
+Public details As CInstDetails 'may be null
+
+Property Get bytes() As Byte()
+ bytes = Me.bytes()
+End Property
+
+Property Get byteDump(Optional padding = 15) As String
+ Dim b As String, i As Long
+ For i = 0 To UBound(m_bytes)
+ b = b & hhex(m_bytes(i)) & " "
+ Next
+ byteDump = rpad(b, padding)
+End Property
+
+Property Get text() As String
+
+ text = cur2str(address) & " " & byteDump & " " & instruction & " " & operand
+
+End Property
+
+Function toString() As String
+
+ Dim r() As String
+
+ push r, "CInstruction: "
+ push r, String(40, "-")
+ push r, "Id: " & Hex(ID)
+ push r, "address: " & cur2str(address)
+ push r, "size: " & Hex(size)
+ push r, "bytes: " & byteDump()
+ push r, "instruction: " & instruction
+ push r, "operand: " & operand
+ push r, "lpDetails: " & Hex(lpDetails)
+
+ If Not details Is Nothing Then
+ push r, details.toString()
+ End If
+
+ toString = Join(r, vbCrLf)
+
+End Function
+
+Friend Sub LoadInstruction(instAry As Long, index As Long, parent As CDisassembler)
+
+ Dim inst As cs_insn
+ Dim i As Long
+
+ getInstruction instAry, index, VarPtr(inst), LenB(inst)
+
+ ID = inst.ID
+ address = inst.address
+ size = inst.size
+ lpDetails = inst.lpDetail
+ Set Me.parent = parent
+
+ m_bytes() = inst.bytes
+ ReDim Preserve m_bytes(size - 1)
+
+ For i = 0 To UBound(inst.mnemonic)
+ If inst.mnemonic(i) = 0 Then Exit For
+ instruction = instruction & Chr(inst.mnemonic(i))
+ Next
+
+ For i = 0 To UBound(inst.op_str)
+ If inst.op_str(i) = 0 Then Exit For
+ operand = operand & Chr(inst.op_str(i))
+ Next
+
+ If lpDetails = 0 Then Exit Sub
+ Set details = New CInstDetails
+ details.LoadDetails lpDetails, parent
+
+End Sub
+
+
+
+
diff --git a/bindings/vb6/CX86Inst.cls b/bindings/vb6/CX86Inst.cls
new file mode 100644
index 0000000..daf7dd5
--- /dev/null
+++ b/bindings/vb6/CX86Inst.cls
@@ -0,0 +1,197 @@
+VERSION 1.0 CLASS
+BEGIN
+ MultiUse = -1 'True
+ Persistable = 0 'NotPersistable
+ DataBindingBehavior = 0 'vbNone
+ DataSourceBehavior = 0 'vbNone
+ MTSTransactionMode = 0 'NotAnMTSObject
+END
+Attribute VB_Name = "CX86Inst"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = True
+Attribute VB_PredeclaredId = False
+Attribute VB_Exposed = False
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+
+'// Instruction structure sizeof() = 432 bytes
+'typedef struct cs_x86 {
+' // Instruction prefix, which can be up to 4 bytes.
+' // A prefix byte gets value 0 when irrelevant.
+' // prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)
+' // prefix[1] indicates segment override (irrelevant for x86_64):
+' // See X86_PREFIX_CS/SS/DS/ES/FS/GS above.
+' // prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)
+' // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)
+' uint8_t prefix[4];
+'
+' // Instruction opcode, wich can be from 1 to 4 bytes in size.
+' // This contains VEX opcode as well.
+' // An trailing opcode byte gets value 0 when irrelevant.
+' uint8_t opcode[4];
+'
+' // REX prefix: only a non-zero value is relavant for x86_64
+' uint8_t rex;
+'
+' // Address size, which can be overrided with above prefix[5].
+' uint8_t addr_size;
+'
+' // ModR/M byte
+' uint8_t modrm;
+'
+' // SIB value, or 0 when irrelevant.
+' uint8_t sib;
+'
+' // Displacement value, or 0 when irrelevant.
+' int32_t disp;
+'
+' /* SIB state */
+' // SIB index register, or X86_REG_INVALID when irrelevant.
+' x86_reg sib_index;
+' // SIB scale. only applicable if sib_index is relavant.
+' int8_t sib_scale;
+' // SIB base register, or X86_REG_INVALID when irrelevant.
+' x86_reg sib_base;
+'
+' // SSE Code Condition
+' x86_sse_cc sse_cc;
+'
+' // AVX Code Condition
+' x86_avx_cc avx_cc;
+'
+' // AVX Suppress all Exception
+' bool avx_sae;
+'
+' // AVX static rounding mode
+' x86_avx_rm avx_rm;
+'
+' // Number of operands of this instruction,
+' // or 0 when instruction has no operand.
+' uint8_t op_count;
+'
+' cs_x86_op operands[8]; // operands for this instruction.
+'} cs_x86;
+
+Private m_prefix() As Byte
+Private m_opcode() As Byte
+Public rex As Byte
+Public addr_size As Byte
+Public modrm As Byte
+Public sib As Byte
+Public disp As Long
+Public sib_index As x86_reg
+Public sib_scale As Byte
+Public sib_base As x86_reg
+Public sse_cc As x86_sse_cc
+Public avx_cc As x86_avx_cc
+Public avx_sae As Boolean
+Public avx_rm As x86_avx_rm
+Public operands As New Collection
+
+Public parent As CDisassembler
+Private hEngine As Long
+Private m_raw() As Byte
+
+Property Get prefix() As Byte()
+ prefix = m_prefix
+End Property
+
+Property Get opcode() As Byte()
+ opcode = m_opcode
+End Property
+
+Function toString() As String
+
+ Dim r() As String
+ Dim o As CX86Operand
+
+ push r, "X86 Instruction Details:"
+ push r, String(40, "-")
+
+ If DEBUG_DUMP Then
+ push r, "Raw: "
+ push r, HexDump(m_raw)
+ End If
+
+ push r, "Prefix: " & b2Str(m_prefix)
+ push r, "OpCode: " & b2Str(m_opcode)
+ push r, "Rex: " & rex
+ push r, "addr_size: " & addr_size
+ push r, "modrm: " & Hex(modrm)
+ push r, "disp: " & Hex(disp)
+
+ If parent.mode <> CS_MODE_16 Then
+ push r, "sib: " & Hex(sib)
+ push r, "sib_index: " & regName(hEngine, sib_index)
+ push r, "sib_scale: " & Hex(sib_scale)
+ push r, "sib_base: " & regName(hEngine, sib_base)
+ End If
+
+ If sse_cc <> 0 Then push r, "sse_cc: " & x86_sse_cc2str(sse_cc)
+ If avx_cc <> 0 Then push r, "avx_cc: " & x86_avx_cc2str(avx_cc)
+ If avx_sae <> 0 Then push r, "avx_sae: " & avx_sae
+ If avx_rm <> 0 Then push r, "avx_rm: " & x86_avx_rm2str(avx_rm)
+
+ push r, "Operands: " & operands.count
+
+ For Each o In operands
+ push r, String(40, "-")
+ push r, o.toString
+ Next
+
+ toString = Join(r, vbCrLf)
+
+End Function
+
+Friend Sub LoadDetails(lpStruct As Long, parent As CDisassembler)
+
+ Dim cs As cs_x86
+ Dim o As CX86Operand
+ Dim ptr As Long
+ Dim i As Long
+
+ Const sizeOfx86Operand = 48
+
+ Set Me.parent = parent
+ hEngine = parent.hCapstone
+
+ CopyMemory ByVal VarPtr(cs), ByVal lpStruct, LenB(cs)
+
+ If DEBUG_DUMP Then
+ ReDim m_raw(LenB(cs))
+ CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpStruct, LenB(cs)
+ End If
+
+ Me.rex = cs.rex
+ Me.addr_size = cs.addr_size
+ Me.modrm = cs.modrm
+ Me.sib = cs.sib
+ Me.disp = cs.disp
+ Me.sib_index = cs.sib_index
+ Me.sib_scale = cs.sib_scale
+ Me.sib_base = cs.sib_base
+ Me.sse_cc = cs.sse_cc
+ Me.avx_cc = cs.avx_cc
+ Me.avx_sae = cs.avx_sae
+ Me.avx_rm = cs.avx_rm
+ m_prefix = cs.prefix
+ m_opcode = cs.opcode
+
+ ptr = lpStruct + LenB(cs) 'we dont include the operands in our vb struct..
+ For i = 1 To cs.op_count
+ Set o = New CX86Operand
+ o.LoadDetails ptr, hEngine
+ operands.Add o
+ ptr = ptr + sizeOfx86Operand
+ Next
+
+
+
+End Sub
+
diff --git a/bindings/vb6/CX86OpMem.cls b/bindings/vb6/CX86OpMem.cls
new file mode 100644
index 0000000..d867c1a
--- /dev/null
+++ b/bindings/vb6/CX86OpMem.cls
@@ -0,0 +1,28 @@
+VERSION 1.0 CLASS
+BEGIN
+ MultiUse = -1 'True
+ Persistable = 0 'NotPersistable
+ DataBindingBehavior = 0 'vbNone
+ DataSourceBehavior = 0 'vbNone
+ MTSTransactionMode = 0 'NotAnMTSObject
+END
+Attribute VB_Name = "CX86OpMem"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = True
+Attribute VB_PredeclaredId = False
+Attribute VB_Exposed = False
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+
+Public segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED
+Public base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED
+Public index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED
+Public scale_ As Long ' scale for index register
+Public disp As Currency ' displacement value
+
diff --git a/bindings/vb6/CX86Operand.cls b/bindings/vb6/CX86Operand.cls
new file mode 100644
index 0000000..ed3c543
--- /dev/null
+++ b/bindings/vb6/CX86Operand.cls
@@ -0,0 +1,202 @@
+VERSION 1.0 CLASS
+BEGIN
+ MultiUse = -1 'True
+ Persistable = 0 'NotPersistable
+ DataBindingBehavior = 0 'vbNone
+ DataSourceBehavior = 0 'vbNone
+ MTSTransactionMode = 0 'NotAnMTSObject
+END
+Attribute VB_Name = "CX86Operand"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = True
+Attribute VB_PredeclaredId = False
+Attribute VB_Exposed = False
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+
+'// Instruction operand sizeof() reports 48 bytes
+'typedef struct cs_x86_op {
+' x86_op_type type; // operand type
+'
+' union {
+' x86_reg reg; // register value for REG operand
+' int64_t imm; // immediate value for IMM operand
+' double fp; // floating point value for FP operand
+' x86_op_mem mem; // base/index/scale/disp value for MEM operand (24bytes max)
+' };
+'
+' // size of this operand (in bytes).
+' uint8_t size;
+'
+' // AVX broadcast type, or 0 if irrelevant
+' x86_avx_bcast avx_bcast;
+'
+' // AVX zero opmask {z}
+' bool avx_zero_opmask;
+'} cs_x86_op;
+
+'Instruction's operand referring to memory
+'This is associated with X86_OP_MEM operand type above
+'Public Type x86_op_mem
+' segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED
+' base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED
+' index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED
+' scale As Long ' scale for index register
+' disp As Currency ' displacement value
+'End Type
+
+'this shows the alignment padding used by compiler..
+' cs_x86_op op;
+' op.type = (x86_op_type)1;
+' op.reg = (x86_reg)2;
+' op.avx_bcast = (x86_avx_bcast)3;
+' op.avx_zero_opmask = 4;
+' op.size = 0xaa;
+' printf("&cs_x86_op = %x", &op);
+' _asm int 3
+'
+'
+'0x0012FF34 01 00 00 00 cc cc cc cc 02 00 00 00 cc cc cc cc ....ÌÌÌÌ....ÌÌÌÌ
+'0x0012FF44 cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
+'0x0012FF54 aa cc cc cc 03 00 00 00 01 cc cc cc cc cc cc cc ªÌÌÌ.....ÌÌÌÌÌÌÌ
+
+Public optype As x86_op_type
+Public size As Byte
+Public avx_bcast As x86_avx_bcast
+Public avx_zero_opmask As Boolean
+
+'only one of the following will be set based on type
+Public reg As x86_reg
+Public fp As Currency
+Public imm As Currency
+Public mem As CX86OpMem
+
+Private hEngine As Long
+Private m_raw() As Byte
+
+Function toString() As String
+
+ Dim ret() As String
+
+ push ret, "X86 Operand:"
+ push ret, String(45, "-")
+
+ If DEBUG_DUMP Then
+ push ret, "Raw: "
+ push ret, HexDump(m_raw)
+ End If
+
+ push ret, "Type: " & opStr()
+ push ret, "Size: " & size
+ If avx_bcast <> 0 Then push ret, "BCast: " & bcastStr()
+ If avx_zero_opmask Then push ret, "AvxOpMask: " & avx_zero_opmask
+
+ If optype = X86_OP_FP Then
+ push ret, "FP: " & cur2str(fp)
+ ElseIf optype = X86_OP_IMM Then
+ push ret, "IMM: " & cur2str(imm)
+ ElseIf optype = x86_op_mem Then
+ If mem.base <> 0 Then push ret, "Base: " & regName(hEngine, mem.base)
+ If mem.index <> 0 Then push ret, "Index: " & regName(hEngine, mem.index)
+ If mem.scale_ <> 1 Then push ret, "Scale: " & Hex(mem.scale_)
+ If mem.segment <> 0 Then push ret, "Seg: " & regName(hEngine, mem.segment)
+ If mem.disp <> 0 Then push ret, "Disp: " & cur2str(mem.disp)
+ ElseIf optype = X86_OP_REG Then
+ push ret, "Reg: " & regName(hEngine, reg)
+ End If
+
+ toString = Join(ret, vbCrLf)
+
+End Function
+
+Function opStr() As String
+
+ If optype = X86_OP_FP Then opStr = "X86_OP_FP"
+ If optype = x86_op_mem Then opStr = "x86_op_mem"
+ If optype = X86_OP_IMM Then opStr = "X86_OP_IMM"
+ If optype = X86_OP_REG Then opStr = "X86_OP_REG"
+ If optype = X86_OP_INVALID Then opStr = "X86_OP_INVALID"
+
+ If Len(opStr) = 0 Then
+ opStr = "Error: " & Hex(optype)
+ ElseIf DEBUG_DUMP Then
+ opStr = opStr & " (" & Hex(optype) & ")"
+ End If
+
+End Function
+
+Function bcastStr() As String
+ Dim r As String
+
+ If avx_bcast = X86_AVX_BCAST_INVALID Then r = "X86_AVX_BCAST_INVALID"
+ If avx_bcast = X86_AVX_BCAST_2 Then r = "X86_AVX_BCAST_2"
+ If avx_bcast = X86_AVX_BCAST_4 Then r = "X86_AVX_BCAST_4"
+ If avx_bcast = X86_AVX_BCAST_8 Then r = "X86_AVX_BCAST_8"
+ If avx_bcast = X86_AVX_BCAST_16 Then r = "X86_AVX_BCAST_16"
+
+ If Len(r) = 0 Then
+ r = "Unknown: " & Hex(avx_bcast)
+ ElseIf DEBUG_DUMP Then
+ r = r & " (" & Hex(avx_bcast) & ")"
+ End If
+
+ bcastStr = r
+End Function
+
+
+Friend Sub LoadDetails(lpStruct As Long, hCapstone As Long)
+
+ Dim opMem As x86_op_mem
+ Dim ptr As Long
+
+ Const align4 = 4
+ Const align3 = 3
+
+ hEngine = hCapstone
+
+ If DEBUG_DUMP Then
+ ReDim m_raw(48)
+ CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpStruct, 48
+ End If
+
+ optype = readLng(lpStruct)
+ ptr = lpStruct + 4 + align4
+
+ If optype = X86_OP_FP Then
+ fp = readCur(ptr)
+ ElseIf optype = X86_OP_IMM Then
+ imm = readCur(ptr)
+ ElseIf optype = x86_op_mem Then
+ CopyMemory ByVal VarPtr(opMem), ByVal ptr, LenB(opMem)
+ Set mem = New CX86OpMem
+ mem.base = opMem.base
+ mem.disp = opMem.disp
+ mem.index = opMem.index
+ mem.scale_ = opMem.scale
+ mem.segment = opMem.segment
+ ElseIf optype = X86_OP_REG Then
+ reg = readLng(ptr)
+ End If
+
+ ptr = ptr + LenB(opMem)
+
+ size = readByte(ptr)
+ ptr = ptr + 1 + align3
+
+ avx_bcast = readLng(ptr)
+ ptr = ptr + 4
+
+ avx_zero_opmask = (readByte(ptr) = 1)
+
+End Sub
+
+Private Sub Class_Terminate()
+ 'looks like everything is freeing up ok
+ 'Debug.Print "Cx86Operand.Terminate"
+End Sub
diff --git a/bindings/vb6/Form1.frm b/bindings/vb6/Form1.frm
new file mode 100644
index 0000000..df71dbe
--- /dev/null
+++ b/bindings/vb6/Form1.frm
@@ -0,0 +1,275 @@
+VERSION 5.00
+Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "mscomctl.ocx"
+Begin VB.Form Form1
+ Caption = "VB6 Bindings for Capstone Disassembly Engine - Contributed by FireEye FLARE Team"
+ ClientHeight = 7290
+ ClientLeft = 60
+ ClientTop = 345
+ ClientWidth = 10275
+ LinkTopic = "Form1"
+ ScaleHeight = 7290
+ ScaleWidth = 10275
+ StartUpPosition = 2 'CenterScreen
+ Begin VB.CommandButton Command2
+ Caption = "Save"
+ Height = 375
+ Left = 8760
+ TabIndex = 8
+ Top = 120
+ Width = 1455
+ End
+ Begin VB.CommandButton Command1
+ Caption = " Arm 64"
+ Height = 375
+ Index = 4
+ Left = 6840
+ TabIndex = 7
+ Top = 120
+ Width = 1455
+ End
+ Begin VB.CommandButton Command1
+ Caption = "Arm"
+ Height = 375
+ Index = 3
+ Left = 5160
+ TabIndex = 6
+ Top = 120
+ Width = 1455
+ End
+ Begin VB.CommandButton Command1
+ Caption = "x86 64bit"
+ Height = 375
+ Index = 2
+ Left = 3480
+ TabIndex = 5
+ Top = 120
+ Width = 1455
+ End
+ Begin VB.CommandButton Command1
+ Caption = "x86 16bit"
+ Height = 375
+ Index = 0
+ Left = 120
+ TabIndex = 4
+ Top = 120
+ Width = 1455
+ End
+ Begin VB.CommandButton Command1
+ Caption = "x86 32bit"
+ Height = 375
+ Index = 1
+ Left = 1800
+ TabIndex = 3
+ Top = 120
+ Width = 1455
+ End
+ Begin MSComctlLib.ListView lv
+ Height = 2415
+ Left = 120
+ TabIndex = 2
+ Top = 1440
+ Width = 10095
+ _ExtentX = 17806
+ _ExtentY = 4260
+ View = 3
+ LabelEdit = 1
+ LabelWrap = -1 'True
+ HideSelection = 0 'False
+ FullRowSelect = -1 'True
+ _Version = 393217
+ ForeColor = -2147483640
+ BackColor = -2147483643
+ BorderStyle = 1
+ Appearance = 1
+ BeginProperty Font {0BE35203-8F91-11CE-9DE3-00AA004BB851}
+ Name = "Courier"
+ Size = 9.75
+ Charset = 0
+ Weight = 400
+ Underline = 0 'False
+ Italic = 0 'False
+ Strikethrough = 0 'False
+ EndProperty
+ NumItems = 1
+ BeginProperty ColumnHeader(1) {BDD1F052-858B-11D1-B16A-00C0F0283628}
+ Object.Width = 2540
+ EndProperty
+ End
+ Begin VB.ListBox List1
+ BeginProperty Font
+ Name = "Courier"
+ Size = 9.75
+ Charset = 0
+ Weight = 400
+ Underline = 0 'False
+ Italic = 0 'False
+ Strikethrough = 0 'False
+ EndProperty
+ Height = 840
+ Left = 120
+ TabIndex = 1
+ Top = 600
+ Width = 10095
+ End
+ Begin VB.TextBox Text1
+ BeginProperty Font
+ Name = "Courier"
+ Size = 9.75
+ Charset = 0
+ Weight = 400
+ Underline = 0 'False
+ Italic = 0 'False
+ Strikethrough = 0 'False
+ EndProperty
+ Height = 3375
+ Left = 120
+ MultiLine = -1 'True
+ ScrollBars = 3 'Both
+ TabIndex = 0
+ Text = "Form1.frx":0000
+ Top = 3840
+ Width = 10095
+ End
+End
+Attribute VB_Name = "Form1"
+Attribute VB_GlobalNameSpace = False
+Attribute VB_Creatable = False
+Attribute VB_PredeclaredId = True
+Attribute VB_Exposed = False
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+Dim cap As CDisassembler
+Dim lastSample As Long
+
+Private Sub Command1_Click(index As Integer)
+
+ Dim code() As Byte, arch As cs_arch, mode As cs_mode
+ lastSample = index
+
+ Const x86_code32 As String = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
+ Const X86_CODE16 As String = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
+ Const X86_CODE64 As String = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
+ Const ARM_CODE As String = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
+ Const ARM64_CODE As String = "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
+
+ Select Case index
+ Case 0:
+ arch = CS_ARCH_X86
+ mode = CS_MODE_16
+ code = toBytes(X86_CODE16)
+ Case 1:
+ arch = CS_ARCH_X86
+ mode = CS_MODE_32
+ code = toBytes(x86_code32)
+ Case 2:
+ arch = CS_ARCH_X86
+ mode = CS_MODE_64
+ code = toBytes(X86_CODE64)
+
+ Case 3:
+ arch = CS_ARCH_ARM
+ mode = CS_MODE_ARM
+ code = toBytes(ARM_CODE)
+
+ Case 4:
+ arch = CS_ARCH_ARM64
+ mode = CS_MODE_ARM
+ code = toBytes(ARM64_CODE)
+ End Select
+
+
+ test code, arch, mode
+
+End Sub
+
+Private Sub test(code() As Byte, arch As cs_arch, mode As cs_mode)
+
+
+ Dim ret As Collection
+ Dim ci As CInstruction
+ Dim li As ListItem
+
+ clearForm
+ If Not cap Is Nothing Then Set cap = Nothing
+
+ Set cap = New CDisassembler
+
+ If Not cap.init(arch, mode, True) Then
+ List1.AddItem "Failed to init engine: " & cap.errMsg
+ Exit Sub
+ End If
+
+ List1.AddItem "Capstone loaded @ 0x" & Hex(cap.hLib)
+ List1.AddItem "hEngine: 0x" & Hex(cap.hCapstone)
+ List1.AddItem "Version: " & cap.version
+
+ If cap.vMajor < 3 Then
+ List1.AddItem "Sample requires Capstone v3+"
+ Exit Sub
+ End If
+
+ Set ret = cap.disasm(&H1000, code)
+
+ For Each ci In ret
+ Set li = lv.ListItems.Add(, , ci.text)
+ Set li.Tag = ci
+ Next
+
+End Sub
+
+Private Sub Command2_Click()
+
+ Dim fName() As String
+ Dim fPath As String
+ Dim t() As String
+ Dim li As ListItem
+ Dim ci As CInstruction
+
+ On Error Resume Next
+
+ If lastSample = -1 Then
+ MsgBox "Run a test first..."
+ Exit Sub
+ End If
+
+ fName = Split("16b,32b,64b,Arm,Arm64", ",")
+
+ fPath = App.path & "\vb" & fName(lastSample) & "Test.txt"
+ If FileExists(fPath) Then Kill fPath
+
+ For Each li In lv.ListItems
+ push t, li.text
+ Set ci = li.Tag
+ push t, ci.toString()
+ push t, String(60, "-")
+ Next
+
+ WriteFile fPath, Join(t, vbCrLf)
+
+ MsgBox FileLen(fPath) & " bytes saved to: " & vbCrLf & vbCrLf & fPath
+
+End Sub
+
+Private Sub lv_ItemClick(ByVal Item As MSComctlLib.ListItem)
+ Dim ci As CInstruction
+ Set ci = Item.Tag
+ Text1 = ci.toString()
+End Sub
+
+Function clearForm()
+ List1.Clear
+ lv.ListItems.Clear
+ Text1 = Empty
+End Function
+
+Private Sub Form_Load()
+ lv.ColumnHeaders(1).Width = lv.Width
+ clearForm
+ lastSample = -1
+End Sub
diff --git a/bindings/vb6/Form1.frx b/bindings/vb6/Form1.frx
new file mode 100644
index 0000000..da8c0d9
--- /dev/null
+++ b/bindings/vb6/Form1.frx
@@ -0,0 +1 @@
+Text1
\ No newline at end of file
diff --git a/bindings/vb6/Module1.bas b/bindings/vb6/Module1.bas
new file mode 100644
index 0000000..942adff
--- /dev/null
+++ b/bindings/vb6/Module1.bas
@@ -0,0 +1,635 @@
+Attribute VB_Name = "mCapStone"
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+'todo: cs_disasm_iter / skipdata
+
+'this is for my vb code and how much info it spits out in tostring methods..
+Global Const DEBUG_DUMP = 0
+
+'Architecture type
+Public Enum cs_arch
+ CS_ARCH_ARM = 0 ' ARM architecture (including Thumb, Thumb-2)
+ CS_ARCH_ARM64 ' ARM-64, also called AArch64
+ CS_ARCH_MIPS ' Mips architecture
+ CS_ARCH_X86 ' X86 architecture (including x86 & x86-64)
+ CS_ARCH_PPC ' PowerPC architecture
+ CS_ARCH_SPARC ' Sparc architecture
+ CS_ARCH_SYSZ ' SystemZ architecture
+ CS_ARCH_XCORE ' XCore architecture
+ CS_ARCH_MAX
+ CS_ARCH_ALL = &HFFFF ' All architectures - for cs_support()
+End Enum
+
+Public Enum cs_mode
+ CS_MODE_LITTLE_ENDIAN = 0 ' little-endian mode (default mode)
+ CS_MODE_ARM = 0 ' 32-bit ARM
+ CS_MODE_16 = 2 ' 16-bit mode (X86)
+ CS_MODE_32 = 4 ' 32-bit mode (X86)
+ CS_MODE_64 = 8 ' 64-bit mode (X86, PPC)
+ CS_MODE_THUMB = 16 ' ARM's Thumb mode, including Thumb-2
+ CS_MODE_MCLASS = 32 ' ARM's Cortex-M series
+ CS_MODE_V8 = 64 ' ARMv8 A32 encodings for ARM
+ CS_MODE_MICRO = 16 ' MicroMips mode (MIPS)
+ CS_MODE_MIPS3 = 32 ' Mips III ISA
+ CS_MODE_MIPS32R6 = 64 ' Mips32r6 ISA
+ CS_MODE_MIPSGP64 = 128 ' General Purpose Registers are 64-bit wide (MIPS)
+ CS_MODE_V9 = 16 ' SparcV9 mode (Sparc)
+ CS_MODE_BIG_ENDIAN = &H80000000 ' big-endian mode
+ CS_MODE_MIPS32 = CS_MODE_32 ' Mips32 ISA (Mips)
+ CS_MODE_MIPS64 = CS_MODE_64 ' Mips64 ISA (Mips)
+End Enum
+
+'Runtime option for the disassembled engine
+Public Enum cs_opt_type
+ CS_OPT_SYNTAX = 1 ' Assembly output syntax
+ CS_OPT_DETAIL ' Break down instruction structure into details
+ CS_OPT_MODE ' Change engine's mode at run-time
+ CS_OPT_MEM ' User-defined dynamic memory related functions
+ CS_OPT_SKIPDATA ' Skip data when disassembling. Then engine is in SKIPDATA mode.
+ CS_OPT_SKIPDATA_SETUP ' Setup user-defined function for SKIPDATA option
+End Enum
+
+
+'Runtime option value (associated with option type above)
+Public Enum cs_opt_value
+ CS_OPT_OFF = 0 ' Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA.
+ CS_OPT_ON = 3 ' Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
+ CS_OPT_SYNTAX_DEFAULT = 0 ' Default asm syntax (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_INTEL ' X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_ATT ' X86 ATT asm syntax (CS_OPT_SYNTAX).
+ CS_OPT_SYNTAX_NOREGNAME ' Prints register name with only number (CS_OPT_SYNTAX)
+End Enum
+
+'Common instruction operand types - to be consistent across all architectures.
+Public Enum cs_op_type
+ CS_OP_INVALID = 0 ' uninitialized/invalid operand.
+ CS_OP_REG ' Register operand.
+ CS_OP_IMM ' Immediate operand.
+ CS_OP_MEM ' Memory operand.
+ CS_OP_FP ' Floating-Point operand.
+End Enum
+
+'Common instruction groups - to be consistent across all architectures.
+Public Enum cs_group_type
+ CS_GRP_INVALID = 0 ' uninitialized/invalid group.
+ CS_GRP_JUMP ' all jump instructions (conditional+direct+indirect jumps)
+ CS_GRP_CALL ' all call instructions
+ CS_GRP_RET ' all return instructions
+ CS_GRP_INT ' all interrupt instructions (int+syscall)
+ CS_GRP_IRET ' all interrupt return instructions
+End Enum
+
+
+'NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
+Public Type cs_detail
+ regs_read(0 To 11) As Byte ' list of implicit registers read by this insn UNSIGNED
+ regs_read_count As Byte ' number of implicit registers read by this insn UNSIGNED
+ regs_write(0 To 19) As Byte ' list of implicit registers modified by this insn UNSIGNED
+ regs_write_count As Byte ' number of implicit registers modified by this insn UNSIGNED
+ groups(0 To 7) As Byte ' list of group this instruction belong to UNSIGNED
+ groups_count As Byte ' number of groups this insn belongs to UNSIGNED
+End Type
+
+'typedef struct cs_detail {
+' uint8_t regs_read[12]; // list of implicit registers read by this insn
+' uint8_t regs_read_count; // number of implicit registers read by this insn
+'
+' uint8_t regs_write[20]; // list of implicit registers modified by this insn
+' uint8_t regs_write_count; // number of implicit registers modified by this insn
+'
+' uint8_t groups[8]; // list of group this instruction belong to
+' uint8_t groups_count; // number of groups this insn belongs to
+'
+' // Architecture-specific instruction info
+' union {
+' cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
+' cs_arm64 arm64; // ARM64 architecture (aka AArch64)
+' cs_arm arm; // ARM architecture (including Thumb/Thumb2)
+' cs_mips mips; // MIPS architecture
+' cs_ppc ppc; // PowerPC architecture
+' cs_sparc sparc; // Sparc architecture
+' cs_sysz sysz; // SystemZ architecture
+' cs_xcore xcore; // XCore architecture
+' };
+'} cs_detail;
+
+'Detail information of disassembled instruction
+Public Type cs_insn
+ ' Instruction ID (basically a numeric ID for the instruction mnemonic)
+ ' Find the instruction id in the '[ARCH]_insn' enum in the header file
+ ' of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
+ ' 'x86_insn' in x86.h for X86, etc...
+ ' available even when CS_OPT_DETAIL = CS_OPT_OFF
+ ' NOTE: in Skipdata mode, "data" instruction has 0 for this id field. UNSIGNED
+ ID As Long '
+ align As Long 'not sure why it needs this..but it does..
+ address As Currency ' Address (EIP) of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED
+ size As Integer ' Size of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED
+ bytes(0 To 15) As Byte ' Machine bytes of this instruction, with number of bytes indicated by @size above available even when CS_OPT_DETAIL = CS_OPT_OFF
+ mnemonic(0 To 31) As Byte ' Ascii text of instruction mnemonic available even when CS_OPT_DETAIL = CS_OPT_OFF
+ op_str(0 To 159) As Byte ' Ascii text of instruction operands available even when CS_OPT_DETAIL = CS_OPT_OFF
+
+ ' Pointer to cs_detail.
+ ' NOTE: detail pointer is only valid when both requirements below are met:
+ ' (1) CS_OP_DETAIL = CS_OPT_ON
+ ' (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
+ ' NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
+ ' is not NULL, its content is still irrelevant.
+ lpDetail As Long ' points to a cs_detail structure NOTE: only available when CS_OPT_DETAIL = CS_OPT_ON
+
+End Type
+
+'All type of errors encountered by Capstone API.
+'These are values returned by cs_errno()
+Public Enum cs_err
+ CS_ERR_OK = 0 ' No error: everything was fine
+ CS_ERR_MEM ' Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
+ CS_ERR_ARCH ' Unsupported architecture: cs_open()
+ CS_ERR_HANDLE ' Invalid handle: cs_op_count(), cs_op_index()
+ CS_ERR_CSH ' Invalid csh argument: cs_close(), cs_errno(), cs_option()
+ CS_ERR_MODE ' Invalid/unsupported mode: cs_open()
+ CS_ERR_OPTION ' Invalid/unsupported option: cs_option()
+ CS_ERR_DETAIL ' Information is unavailable because detail option is OFF
+ CS_ERR_MEMSETUP ' Dynamic memory management uninitialized (see CS_OPT_MEM)
+ CS_ERR_VERSION ' Unsupported version (bindings)
+ CS_ERR_DIET ' Access irrelevant data in "diet" engine
+ CS_ERR_SKIPDATA ' Access irrelevant data for "data" instruction in SKIPDATA mode
+ CS_ERR_X86_ATT ' X86 AT&T syntax is unsupported (opt-out at compile time)
+ CS_ERR_X86_INTEL ' X86 Intel syntax is unsupported (opt-out at compile time)
+End Enum
+
+
+'/*
+' Return combined API version & major and minor version numbers.
+'
+' @major: major number of API version
+' @minor: minor number of API version
+'
+' @return hexical number as (major << 8 | minor), which encodes both
+' major & minor versions.
+' NOTE: This returned value can be compared with version number made
+' with macro CS_MAKE_VERSION
+'
+' For example, second API version would return 1 in @major, and 1 in @minor
+' The return value would be 0x0101
+'
+' NOTE: if you only care about returned value, but not major and minor values,
+' set both @major & @minor arguments to NULL.
+'*/
+'CAPSTONE_EXPORT
+'unsigned int cs_version(int *major, int *minor);
+Public Declare Function cs_version Lib "vbCapstone.dll" Alias "bs_version" (ByRef major As Long, ByRef minor As Long) As Long
+
+
+
+'
+'/*
+' This API can be used to either ask for archs supported by this library,
+' or check to see if the library was compile with 'diet' option (or called
+' in 'diet' mode).
+'
+' To check if a particular arch is supported by this library, set @query to
+' arch mode (CS_ARCH_* value).
+' To verify if this library supports all the archs, use CS_ARCH_ALL.
+'
+' To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
+'
+' @return True if this library supports the given arch, or in 'diet' mode.
+'*/
+'CAPSTONE_EXPORT
+'bool cs_support(int query);
+Public Declare Function cs_support Lib "vbCapstone.dll" Alias "bs_support" (ByVal query As Long) As Long
+
+
+
+'/*
+' Initialize CS handle: this must be done before any usage of CS.
+'
+' @arch: architecture type (CS_ARCH_*)
+' @mode: hardware mode. This is combined of CS_MODE_*
+' @handle: pointer to handle, which will be updated at return time
+'
+' @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+' for detailed error).
+'*/
+'CAPSTONE_EXPORT
+'cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle);
+Public Declare Function cs_open Lib "vbCapstone.dll" Alias "bs_open" (ByVal arch As cs_arch, ByVal mode As cs_mode, ByRef hEngine As Long) As cs_err
+
+
+'/*
+' Close CS handle: MUST do to release the handle when it is not used anymore.
+' NOTE: this must be only called when there is no longer usage of Capstone,
+' not even access to cs_insn array. The reason is the this API releases some
+' cached memory, thus access to any Capstone API after cs_close() might crash
+' your application.
+'
+' In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
+'
+' @handle: pointer to a handle returned by cs_open()
+'
+' @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+' for detailed error).
+'*/
+'CAPSTONE_EXPORT
+'cs_err cs_close(csh *handle);
+Public Declare Function cs_close Lib "vbCapstone.dll" Alias "bs_close" (ByRef hEngine As Long) As cs_err
+
+
+
+'/*
+' Set option for disassembling engine at runtime
+'
+' @handle: handle returned by cs_open()
+' @type: type of option to be set
+' @value: option value corresponding with @type
+'
+' @return: CS_ERR_OK on success, or other value on failure.
+' Refer to cs_err enum for detailed error.
+'
+' NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
+' so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
+' even before cs_open()
+'*/
+'CAPSTONE_EXPORT
+'cs_err cs_option(csh handle, cs_opt_type type, size_t value);
+Public Declare Function cs_option Lib "vbCapstone.dll" Alias "bs_option" (ByVal hEngine As Long, ByVal typ As cs_opt_type, ByVal size As Long) As cs_err
+
+
+
+'/*
+' Report the last error number when some API function fail.
+' Like glibc's errno, cs_errno might not retain its old value once accessed.
+'
+' @handle: handle returned by cs_open()
+'
+' @return: error code of cs_err enum type (CS_ERR_*, see above)
+'*/
+'CAPSTONE_EXPORT
+'cs_err cs_errno(csh handle);
+Public Declare Function cs_errno Lib "vbCapstone.dll" Alias "bs_errno" (ByVal hEngine As Long) As cs_err
+
+'
+'/*
+' Return a string describing given error code.
+'
+' @code: error code (see CS_ERR_* above)
+'
+' @return: returns a pointer to a string that describes the error code
+' passed in the argument @code
+'*/
+'CAPSTONE_EXPORT
+'const char *cs_strerror(cs_err code);
+Public Declare Function cs_strerror Lib "vbCapstone.dll" Alias "bs_strerror" (ByVal errCode As cs_err) As Long
+
+
+'/*
+' Disassemble binary code, given the code buffer, size, address and number
+' of instructions to be decoded.
+' This API dynamically allocate memory to contain disassembled instruction.
+' Resulted instructions will be put into @*insn
+'
+' NOTE 1: this API will automatically determine memory needed to contain
+' output disassembled instructions in @insn.
+'
+' NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
+'
+' NOTE 3: for system with scarce memory to be dynamically allocated such as
+' OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
+' cs_disasm(). The reason is that with cs_disasm(), based on limited available
+' memory, we have to calculate in advance how many instructions to be disassembled,
+' which complicates things. This is especially troublesome for the case @count=0,
+' when cs_disasm() runs uncontrollably (until either end of input buffer, or
+' when it encounters an invalid instruction).
+'
+' @handle: handle returned by cs_open()
+' @code: buffer containing raw binary code to be disassembled.
+' @code_size: size of the above code buffer.
+' @address: address of the first instruction in given raw code buffer.
+' @insn: array of instructions filled in by this API.
+' NOTE: @insn will be allocated by this function, and should be freed
+' with cs_free() API.
+' @count: number of instructions to be disassembled, or 0 to get all of them
+'
+' @return: the number of successfully disassembled instructions,
+' or 0 if this function failed to disassemble the given code
+'
+' On failure, call cs_errno() for error code.
+'*/
+'CAPSTONE_EXPORT
+'size_t cs_disasm(
+' csh handle,
+' const uint8_t *code,
+' size_t code_size,
+' uint64_t address,
+' size_t count,
+' cs_insn **insn
+');
+Public Declare Function cs_disasm Lib "vbCapstone.dll" Alias "bs_disasm" ( _
+ ByVal hEngine As Long, _
+ ByRef code As Byte, _
+ ByVal size As Long, _
+ ByVal address As Currency, _
+ ByVal count As Long, _
+ ByRef instAryPtr As Long _
+) As Long
+
+'this proto also lets use byte() to get a dump easily..
+Public Declare Sub getInstruction Lib "vbCapstone.dll" (ByVal hInstrAry As Long, ByVal index As Long, ByVal insPtr As Long, ByVal size As Long)
+
+
+'/*
+' Deprecated function - to be retired in the next version!
+' Use cs_disasm() instead of cs_disasm_ex()
+'*/
+'CAPSTONE_EXPORT
+'CAPSTONE_DEPRECATED
+'size_t cs_disasm_ex(csh handle,
+' const uint8_t *code, size_t code_size,
+' uint64_t address,
+' size_t count,
+' cs_insn **insn);
+
+
+
+'/*
+' Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
+'
+' @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
+' @count: number of cs_insn structures returned by cs_disasm(), or 1
+' to free memory allocated by cs_malloc().
+'*/
+'CAPSTONE_EXPORT
+'void cs_free(cs_insn *insn, size_t count);
+Public Declare Sub cs_free Lib "vbCapstone.dll" Alias "bs_free" (ByVal instr As Long, ByVal count As Long)
+
+
+'
+'/*
+' Allocate memory for 1 instruction to be used by cs_disasm_iter().
+'
+' @handle: handle returned by cs_open()
+'
+' NOTE: when no longer in use, you can reclaim the memory allocated for
+' this instruction with cs_free(insn, 1)
+'*/
+'CAPSTONE_EXPORT
+'cs_insn *cs_malloc(csh handle);
+Public Declare Function cs_malloc Lib "vbCapstone.dll" Alias "bs_malloc" (ByVal handle As Long) As Long
+
+
+
+'/*
+' Fast API to disassemble binary code, given the code buffer, size, address
+' and number of instructions to be decoded.
+' This API put the resulted instruction into a given cache in @insn.
+' See tests/test_iter.c for sample code demonstrating this API.
+'
+' NOTE 1: this API will update @code, @size & @address to point to the next
+' instruction in the input buffer. Therefore, it is convenient to use
+' cs_disasm_iter() inside a loop to quickly iterate all the instructions.
+' While decoding one instruction at a time can also be achieved with
+' cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
+' faster on random input.
+'
+' NOTE 2: the cache in @insn can be created with cs_malloc() API.
+'
+' NOTE 3: for system with scarce memory to be dynamically allocated such as
+' OS kernel or firmware, this API is recommended over cs_disasm(), which
+' allocates memory based on the number of instructions to be disassembled.
+' The reason is that with cs_disasm(), based on limited available memory,
+' we have to calculate in advance how many instructions to be disassembled,
+' which complicates things. This is especially troublesome for the case
+' @count=0, when cs_disasm() runs uncontrollably (until either end of input
+' buffer, or when it encounters an invalid instruction).
+'
+' @handle: handle returned by cs_open()
+' @code: buffer containing raw binary code to be disassembled
+' @code_size: size of above code
+' @address: address of the first insn in given raw code buffer
+' @insn: pointer to instruction to be filled in by this API.
+'
+' @return: true if this API successfully decode 1 instruction,
+' or false otherwise.
+'
+' On failure, call cs_errno() for error code.
+'*/
+'CAPSTONE_EXPORT
+'bool cs_disasm_iter(csh handle, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn);
+
+
+
+'/*
+' Return friendly name of register in a string.
+' Find the instruction id from header file of corresponding architecture (arm.h for ARM,
+' x86.h for X86, ...)
+'
+' WARN: when in 'diet' mode, this API is irrelevant because engine does not
+' store register name.
+'
+' @handle: handle returned by cs_open()
+' @reg_id: register id
+'
+' @return: string name of the register, or NULL if @reg_id is invalid.
+'*/
+'CAPSTONE_EXPORT
+'const char *cs_reg_name(csh handle, unsigned int reg_id);
+Public Declare Function cs_reg_name Lib "vbCapstone.dll" Alias "bs_reg_name" (ByVal handle As Long, ByVal regID As Long) As Long
+
+
+
+
+'/*
+' Return friendly name of an instruction in a string.
+' Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+'
+' WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+' store instruction name.
+'
+' @handle: handle returned by cs_open()
+' @insn_id: instruction id
+'
+' @return: string name of the instruction, or NULL if @insn_id is invalid.
+'*/
+'CAPSTONE_EXPORT
+'const char *cs_insn_name(csh handle, unsigned int insn_id);
+Public Declare Function cs_insn_name Lib "vbCapstone.dll" Alias "bs_insn_name" (ByVal handle As Long, ByVal insn_id As Long) As Long
+
+
+
+
+'/*
+' Return friendly name of a group id (that an instruction can belong to)
+' Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+'
+' WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+' store group name.
+'
+' @handle: handle returned by cs_open()
+' @group_id: group id
+'
+' @return: string name of the group, or NULL if @group_id is invalid.
+'*/
+'CAPSTONE_EXPORT
+'const char *cs_group_name(csh handle, unsigned int group_id);
+Public Declare Function cs_group_name Lib "vbCapstone.dll" Alias "bs_group_name" (ByVal handle As Long, ByVal group_id As Long) As Long
+
+
+
+'/*
+' Check if a disassembled instruction belong to a particular group.
+' Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+' Internally, this simply verifies if @group_id matches any member of insn->groups array.
+'
+' NOTE: this API is only valid when detail option is ON (which is OFF by default).
+'
+' WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+' update @groups array.
+'
+' @handle: handle returned by cs_open()
+' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+' @group_id: group that you want to check if this instruction belong to.
+'
+' @return: true if this instruction indeed belongs to aboved group, or false otherwise.
+'*/
+'CAPSTONE_EXPORT
+'bool cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);
+Public Declare Function cs_insn_group Lib "vbCapstone.dll" Alias "bs_insn_group" (ByVal handle As Long, ByVal instruction As Long, ByVal group_id As Long) As Long
+
+
+
+'/*
+' Check if a disassembled instruction IMPLICITLY used a particular register.
+' Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+' Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
+'
+' NOTE: this API is only valid when detail option is ON (which is OFF by default)
+'
+' WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+' update @regs_read array.
+'
+' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+' @reg_id: register that you want to check if this instruction used it.
+'
+' @return: true if this instruction indeed implicitly used aboved register, or false otherwise.
+'*/
+'CAPSTONE_EXPORT
+'bool cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);
+Public Declare Function cs_reg_read Lib "vbCapstone.dll" Alias "bs_reg_read" (ByVal handle As Long, ByVal instruction As Long, ByVal reg_id As Long) As Long
+
+
+
+'/*
+' Check if a disassembled instruction IMPLICITLY modified a particular register.
+' Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+' Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
+'
+' NOTE: this API is only valid when detail option is ON (which is OFF by default)
+'
+' WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+' update @regs_write array.
+'
+' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+' @reg_id: register that you want to check if this instruction modified it.
+'
+' @return: true if this instruction indeed implicitly modified aboved register, or false otherwise.
+'*/
+'CAPSTONE_EXPORT
+'bool cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);
+Public Declare Function cs_reg_write Lib "vbCapstone.dll" Alias "bs_reg_write" (ByVal handle As Long, ByVal instruction As Long, ByVal reg_id As Long) As Long
+
+
+
+'/*
+' Count the number of operands of a given type.
+' Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+'
+' NOTE: this API is only valid when detail option is ON (which is OFF by default)
+'
+' @handle: handle returned by cs_open()
+' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+' @op_type: Operand type to be found.
+'
+' @return: number of operands of given type @op_type in instruction @insn,
+' or -1 on failure.
+'*/
+'CAPSTONE_EXPORT
+'int cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);
+Public Declare Function cs_op_count Lib "vbCapstone.dll" Alias "bs_op_count" (ByVal handle As Long, ByVal instruction As Long, ByVal op_type As Long) As Long
+
+
+
+'/*
+' Retrieve the position of operand of given type in <arch>.operands[] array.
+' Later, the operand can be accessed using the returned position.
+' Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+'
+' NOTE: this API is only valid when detail option is ON (which is OFF by default)
+'
+' @handle: handle returned by cs_open()
+' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+' @op_type: Operand type to be found.
+' @position: position of the operand to be found. This must be in the range
+' [1, cs_op_count(handle, insn, op_type)]
+'
+' @return: index of operand of given type @op_type in <arch>.operands[] array
+' in instruction @insn, or -1 on failure.
+'*/
+'CAPSTONE_EXPORT
+'int cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, unsigned int position);
+Public Declare Function cs_op_index Lib "vbCapstone.dll" Alias "bs_op_index" (ByVal handle As Long, ByVal instruction As Long, ByVal op_type As Long, ByVal position As Long) As Long
+
+
+
+Private Declare Function lstrcpy Lib "kernel32" Alias "lstrcpyA" (ByVal lpString1 As String, ByVal lpString2 As String) As Long
+Private Declare Function lstrlen Lib "kernel32" Alias "lstrlenA" (ByVal lpString As Long) As Long
+
+Function cstr2vb(lpStr As Long) As String
+
+ Dim length As Long
+ Dim buf() As Byte
+
+ If lpStr = 0 Then Exit Function
+
+ length = lstrlen(lpStr)
+ If length < 1 Then Exit Function
+
+ ReDim buf(1 To length)
+ CopyMemory buf(1), ByVal lpStr, length
+
+ cstr2vb = StrConv(buf, vbUnicode, &H409)
+
+End Function
+
+Function err2str(e As cs_err) As String
+ Dim lpStr As Long
+ lpStr = cs_strerror(e)
+ err2str = cstr2vb(lpStr)
+End Function
+
+Function regName(hEngine As Long, regID As Long) As String
+ Dim lpStr As Long
+ lpStr = cs_reg_name(hEngine, regID)
+ regName = cstr2vb(lpStr)
+ If Len(regName) = 0 Or DEBUG_DUMP Then regName = regName & " (" & Hex(regID) & ")"
+End Function
+
+Function insnName(hEngine As Long, insnID As Long) As String
+ Dim lpStr As Long
+ lpStr = cs_insn_name(hEngine, insnID)
+ insnName = cstr2vb(lpStr)
+ If Len(insnName) = 0 Or DEBUG_DUMP Then insnName = insnName & " (" & Hex(insnID) & ")"
+End Function
+
+Function groupName(hEngine As Long, groupID As Long) As String
+ Dim lpStr As Long
+ lpStr = cs_group_name(hEngine, groupID)
+ groupName = cstr2vb(lpStr)
+ If Len(groupName) = 0 Or DEBUG_DUMP Then groupName = groupName & " (" & Hex(groupID) & ")"
+End Function
diff --git a/bindings/vb6/Project1.vbp b/bindings/vb6/Project1.vbp
new file mode 100644
index 0000000..249657a
--- /dev/null
+++ b/bindings/vb6/Project1.vbp
@@ -0,0 +1,46 @@
+Type=Exe
+Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#C:\WINDOWS\system32\stdole2.tlb#OLE Automation
+Form=Form1.frm
+Module=mCapStone; Module1.bas
+Module=mx86; mx86.bas
+Module=mMisc; mMisc.bas
+Class=CInstruction; CInstruction.cls
+Class=CInstDetails; CInstDetails.cls
+Class=CDisassembler; CDisassembler.cls
+Object={831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0; mscomctl.ocx
+Class=CX86Inst; CX86Inst.cls
+Class=CX86Operand; CX86Operand.cls
+Class=CX86OpMem; CX86OpMem.cls
+Startup="Form1"
+ExeName32="Project1.exe"
+Command32=""
+Name="Project1"
+HelpContextID="0"
+CompatibleMode="0"
+MajorVer=1
+MinorVer=0
+RevisionVer=0
+AutoIncrementVer=0
+ServerSupportFiles=0
+VersionCompanyName="sandsprite"
+CompilationType=0
+OptimizationType=0
+FavorPentiumPro(tm)=0
+CodeViewDebugInfo=0
+NoAliasing=0
+BoundsCheck=0
+OverflowCheck=0
+FlPointCheck=0
+FDIVCheck=0
+UnroundedFP=0
+StartMode=0
+Unattended=0
+Retained=0
+ThreadPerObject=0
+MaxNumberOfThreads=1
+
+[MS Transaction Server]
+AutoRefresh=1
+
+[fastBuild]
+fullPath=%ap%\bin\demo.exe
diff --git a/bindings/vb6/Project1.vbw b/bindings/vb6/Project1.vbw
new file mode 100644
index 0000000..0db503f
--- /dev/null
+++ b/bindings/vb6/Project1.vbw
@@ -0,0 +1,10 @@
+Form1 = 110, 110, 1233, 906, , 88, 88, 1116, 749, C
+mCapStone = 22, 22, 1050, 683,
+mx86 = 88, 88, 1040, 757,
+mMisc = 66, 66, 1094, 727,
+CInstruction = 0, 0, 0, 0, C
+CInstDetails = 132, 132, 1084, 801, C
+CDisassembler = 44, 44, 1229, 809,
+CX86Inst = 154, 154, 1106, 823, C
+CX86Operand = 176, 176, 1128, 845, C
+CX86OpMem = 198, 198, 1150, 867, C
diff --git a/bindings/vb6/README.txt b/bindings/vb6/README.txt
new file mode 100644
index 0000000..aca836a
--- /dev/null
+++ b/bindings/vb6/README.txt
@@ -0,0 +1,30 @@
+
+Capstone Disassembly Engine bindings for VB6
+Contributed by FireEye FLARE Team
+Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+License: Apache
+Copyright: FireEye 2017
+
+This is a sample for using the capstone disassembly engine with VB6.
+
+All of the capstone API are implemented, so this lib supports basic
+disassembly of all of the processor architectures that capstone implements.
+
+In the vb code, full instruction details are currently only supported for
+the x86 processor family.
+
+This sample was built against Capstone 3.0 rc4. Note that if the capstone
+structures change in the future this code will have to be adjusted to match.
+
+The vbCapstone.dll is written in C. Project files are provided for VS2008.
+It is a small shim to give VB6 access to a stdcall API to access capstone.
+You could also modify capstone itself so its exports were stdcall.
+
+The C project has an additional include directory set to ./../../include/
+for <capstone.h>. This is for the /capstone/bindings/vb6/ directory structure
+
+
+
+
+
+
diff --git a/bindings/vb6/mMisc.bas b/bindings/vb6/mMisc.bas
new file mode 100644
index 0000000..2ccb130
--- /dev/null
+++ b/bindings/vb6/mMisc.bas
@@ -0,0 +1,385 @@
+Attribute VB_Name = "mMisc"
+Option Explicit
+
+'These are old library functions
+
+Private Type Bit64Currency
+ value As Currency
+End Type
+
+Private Type Bit64Integer
+ LowValue As Long
+ HighValue As Long
+End Type
+
+Global Const LANG_US = &H409
+
+Public Declare Function LoadLibrary Lib "kernel32" Alias "LoadLibraryA" (ByVal lpLibFileName As String) As Long
+Public Declare Function FreeLibrary Lib "kernel32" (ByVal hLibModule As Long) As Long
+Public Declare Sub CopyMemory Lib "kernel32" Alias "RtlMoveMemory" (Destination As Any, Source As Any, ByVal length As Long)
+Public Declare Function GetProcAddress Lib "kernel32" (ByVal hModule As Long, ByVal lpProcName As String) As Long
+Public Declare Function GetModuleHandle Lib "kernel32" Alias "GetModuleHandleA" (ByVal lpModuleName As String) As Long
+Public Declare Function SetDllDirectory Lib "kernel32" Alias "SetDllDirectoryA" (ByVal lpPathName As String) As Long
+
+Function makeCur(high As Long, low As Long) As Currency
+ Dim c As Bit64Currency
+ Dim dl As Bit64Integer
+ dl.LowValue = low
+ dl.HighValue = high
+ LSet c = dl
+ makeCur = c.value
+End Function
+
+Function lng2Cur(v As Long) As Currency
+ Dim c As Bit64Currency
+ Dim dl As Bit64Integer
+ dl.LowValue = v
+ dl.HighValue = 0
+ LSet c = dl
+ lng2Cur = c.value
+End Function
+
+Function cur2str(v As Currency) As String
+ Dim c As Bit64Currency
+ Dim dl As Bit64Integer
+ c.value = v
+ LSet dl = c
+ If dl.HighValue = 0 Then
+ cur2str = Right("00000000" & Hex(dl.LowValue), 8)
+ Else
+ cur2str = Right("00000000" & Hex(dl.HighValue), 8) & "`" & Right("00000000" & Hex(dl.LowValue), 8)
+ End If
+End Function
+
+Function x64StrToCur(ByVal str As String) As Currency
+
+ str = Replace(Trim(str), "0x", "")
+ str = Replace(str, " ", "")
+ str = Replace(str, "`", "")
+
+ Dim low As String, high As String
+ Dim c As Bit64Currency
+ Dim dl As Bit64Integer
+
+ low = VBA.Right(str, 8)
+ dl.LowValue = CLng("&h" & low)
+
+ If Len(str) > 8 Then
+ high = Mid(str, 1, Len(str) - 8)
+ dl.HighValue = CLng("&h" & high)
+ End If
+
+ LSet c = dl
+ x64StrToCur = c.value
+
+End Function
+
+Function cur2lng(v As Currency) As Long
+ Dim c As Bit64Currency
+ Dim dl As Bit64Integer
+ c.value = v
+ LSet dl = c
+ cur2lng = dl.LowValue
+End Function
+
+Function readLng(offset As Long) As Long
+ Dim tmp As Long
+ CopyMemory ByVal VarPtr(tmp), ByVal offset, 4
+ readLng = tmp
+End Function
+
+Function readByte(offset As Long) As Byte
+ Dim tmp As Byte
+ CopyMemory ByVal VarPtr(tmp), ByVal offset, 1
+ readByte = tmp
+End Function
+
+Function readCur(offset As Long) As Currency
+ Dim tmp As Currency
+ CopyMemory ByVal VarPtr(tmp), ByVal offset, 8
+ readCur = tmp
+End Function
+
+Function col2Str(c As Collection, Optional emptyVal = "") As String
+ Dim v, tmp As String
+
+ If c.count = 0 Then
+ col2Str = emptyVal
+ Else
+ For Each v In c
+ col2Str = col2Str & hhex(v) & ", "
+ Next
+ col2Str = Mid(col2Str, 1, Len(col2Str) - 2)
+ End If
+
+End Function
+
+Function regCol2Str(hEngine As Long, c As Collection) As String
+ Dim v, tmp As String
+
+ If c.count = 0 Then Exit Function
+
+ For Each v In c
+ regCol2Str = regCol2Str & regName(hEngine, CLng(v)) & ", "
+ Next
+ regCol2Str = Mid(regCol2Str, 1, Len(regCol2Str) - 2)
+
+End Function
+
+
+
+Function b2Str(b() As Byte) As String
+ Dim i As Long
+
+ If AryIsEmpty(b) Then
+ b2Str = "Empty"
+ Else
+ For i = 0 To UBound(b)
+ b2Str = b2Str & hhex(b(i)) & " "
+ Next
+ b2Str = Trim(b2Str)
+ End If
+
+End Function
+
+
+
+Function AryIsEmpty(ary) As Boolean
+ Dim i As Long
+
+ On Error GoTo oops
+ i = UBound(ary) '<- throws error if not initalized
+ AryIsEmpty = False
+ Exit Function
+oops: AryIsEmpty = True
+End Function
+
+Public Function toBytes(ByVal hexstr, Optional strRet As Boolean = False)
+
+'supports:
+'11 22 33 44 spaced hex chars
+'11223344 run together hex strings
+'11,22,33,44 csv hex
+'\x11,0x22 misc C source rips
+'
+'ignores common C source prefixes, operators, delimiters, and whitespace
+'
+'not supported
+'1,2,3,4 all hex chars are must have two chars even if delimited
+'
+'a version which supports more formats is here:
+' https://github.com/dzzie/libs/blob/master/dzrt/globals.cls
+
+ Dim ret As String, x As String, str As String
+ Dim r() As Byte, b As Byte, b1 As Byte
+ Dim foundDecimal As Boolean, tmp, i, a, a2
+ Dim pos As Long, marker As String
+
+ On Error GoTo nope
+
+ str = Replace(hexstr, vbCr, Empty)
+ str = Replace(str, vbLf, Empty)
+ str = Replace(str, vbTab, Empty)
+ str = Replace(str, Chr(0), Empty)
+ str = Replace(str, "{", Empty)
+ str = Replace(str, "}", Empty)
+ str = Replace(str, ";", Empty)
+ str = Replace(str, "+", Empty)
+ str = Replace(str, """""", Empty)
+ str = Replace(str, "'", Empty)
+ str = Replace(str, " ", Empty)
+ str = Replace(str, "0x", Empty)
+ str = Replace(str, "\x", Empty)
+ str = Replace(str, ",", Empty)
+
+ For i = 1 To Len(str) Step 2
+ x = Mid(str, i, 2)
+ If Not isHexChar(x, b) Then Exit Function
+ bpush r(), b
+ Next
+
+ If strRet Then
+ toBytes = StrConv(r, vbUnicode, LANG_US)
+ Else
+ toBytes = r
+ End If
+
+nope:
+End Function
+
+Private Sub bpush(bAry() As Byte, b As Byte) 'this modifies parent ary object
+ On Error GoTo init
+ Dim x As Long
+
+ x = UBound(bAry) '<-throws Error If Not initalized
+ ReDim Preserve bAry(UBound(bAry) + 1)
+ bAry(UBound(bAry)) = b
+
+ Exit Sub
+
+init:
+ ReDim bAry(0)
+ bAry(0) = b
+
+End Sub
+
+Sub push(ary, value) 'this modifies parent ary object
+ On Error GoTo init
+ Dim x
+
+ x = UBound(ary)
+ ReDim Preserve ary(x + 1)
+
+ If IsObject(value) Then
+ Set ary(x + 1) = value
+ Else
+ ary(x + 1) = value
+ End If
+
+ Exit Sub
+init:
+ ReDim ary(0)
+ If IsObject(value) Then
+ Set ary(0) = value
+ Else
+ ary(0) = value
+ End If
+End Sub
+
+
+Public Function isHexChar(hexValue As String, Optional b As Byte) As Boolean
+ On Error Resume Next
+ Dim v As Long
+
+ If Len(hexValue) = 0 Then GoTo nope
+ If Len(hexValue) > 2 Then GoTo nope 'expecting hex char code like FF or 90
+
+ v = CLng("&h" & hexValue)
+ If Err.Number <> 0 Then GoTo nope 'invalid hex code
+
+ b = CByte(v)
+ If Err.Number <> 0 Then GoTo nope 'shouldnt happen.. > 255 cant be with len() <=2 ?
+
+ isHexChar = True
+
+ Exit Function
+nope:
+ Err.Clear
+ isHexChar = False
+End Function
+
+Function hhex(b) As String
+ hhex = Right("00" & Hex(b), 2)
+End Function
+
+Function rpad(x, i, Optional c = " ")
+ rpad = Left(x & String(i, c), i)
+End Function
+
+Function HexDump(bAryOrStrData, Optional hexOnly = 0, Optional ByVal startAt As Long = 1, Optional ByVal length As Long = -1) As String
+ Dim s() As String, chars As String, tmp As String
+ On Error Resume Next
+ Dim ary() As Byte
+ Dim offset As Long
+ Const LANG_US = &H409
+ Dim i As Long, tt, h, x
+
+ offset = 0
+
+ If TypeName(bAryOrStrData) = "Byte()" Then
+ ary() = bAryOrStrData
+ Else
+ ary = StrConv(CStr(bAryOrStrData), vbFromUnicode, LANG_US)
+ End If
+
+ If startAt < 1 Then startAt = 1
+ If length < 1 Then length = -1
+
+ While startAt Mod 16 <> 0
+ startAt = startAt - 1
+ Wend
+
+ startAt = startAt + 1
+
+ chars = " "
+ For i = startAt To UBound(ary) + 1
+ tt = Hex(ary(i - 1))
+ If Len(tt) = 1 Then tt = "0" & tt
+ tmp = tmp & tt & " "
+ x = ary(i - 1)
+ 'chars = chars & IIf((x > 32 And x < 127) Or x > 191, Chr(x), ".") 'x > 191 causes \x0 problems on non us systems... asc(chr(x)) = 0
+ chars = chars & IIf((x > 32 And x < 127), Chr(x), ".")
+ If i > 1 And i Mod 16 = 0 Then
+ h = Hex(offset)
+ While Len(h) < 6: h = "0" & h: Wend
+ If hexOnly = 0 Then
+ push s, h & " " & tmp & chars
+ Else
+ push s, tmp
+ End If
+ offset = offset + 16
+ tmp = Empty
+ chars = " "
+ End If
+ If length <> -1 Then
+ length = length - 1
+ If length = 0 Then Exit For
+ End If
+ Next
+
+ 'if read length was not mod 16=0 then
+ 'we have part of line to account for
+ If tmp <> Empty Then
+ If hexOnly = 0 Then
+ h = Hex(offset)
+ While Len(h) < 6: h = "0" & h: Wend
+ h = h & " " & tmp
+ While Len(h) <= 56: h = h & " ": Wend
+ push s, h & chars
+ Else
+ push s, tmp
+ End If
+ End If
+
+ HexDump = Join(s, vbCrLf)
+
+ If hexOnly <> 0 Then
+ HexDump = Replace(HexDump, " ", "")
+ HexDump = Replace(HexDump, vbCrLf, "")
+ End If
+
+End Function
+
+
+
+Function FileExists(path As String) As Boolean
+ On Error GoTo hell
+
+ If Len(path) = 0 Then Exit Function
+ If Right(path, 1) = "\" Then Exit Function
+ If Dir(path, vbHidden Or vbNormal Or vbReadOnly Or vbSystem) <> "" Then FileExists = True
+
+ Exit Function
+hell: FileExists = False
+End Function
+
+Sub WriteFile(path, it)
+ Dim f
+ f = FreeFile
+ Open path For Output As #f
+ Print #f, it
+ Close f
+End Sub
+
+Function GetParentFolder(path) As String
+ Dim tmp() As String, ub As Long
+ On Error Resume Next
+ tmp = Split(path, "\")
+ ub = tmp(UBound(tmp))
+ If Err.Number = 0 Then
+ GetParentFolder = Replace(Join(tmp, "\"), "\" & ub, "")
+ Else
+ GetParentFolder = path
+ End If
+End Function
+
diff --git a/bindings/vb6/mx86.bas b/bindings/vb6/mx86.bas
new file mode 100644
index 0000000..aa073ad
--- /dev/null
+++ b/bindings/vb6/mx86.bas
@@ -0,0 +1,1868 @@
+Attribute VB_Name = "mx86"
+Option Explicit
+
+'Capstone Disassembly Engine bindings for VB6
+'Contributed by FireEye FLARE Team
+'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+'License: Apache
+'Copyright: FireEye 2017
+
+
+Enum x86_reg
+ X86_REG_INVALID = 0
+ X86_REG_AH
+ X86_REG_AL
+ X86_REG_AX
+ X86_REG_BH
+ X86_REG_BL
+ X86_REG_BP
+ X86_REG_BPL
+ X86_REG_BX
+ X86_REG_CH
+ X86_REG_CL
+ X86_REG_CS
+ X86_REG_CX
+ X86_REG_DH
+ X86_REG_DI
+ X86_REG_DIL
+ X86_REG_DL
+ X86_REG_DS
+ X86_REG_DX
+ X86_REG_EAX
+ X86_REG_EBP
+ X86_REG_EBX
+ X86_REG_ECX
+ X86_REG_EDI
+ X86_REG_EDX
+ X86_REG_EFLAGS
+ X86_REG_EIP
+ X86_REG_EIZ
+ X86_REG_ES
+ X86_REG_ESI
+ X86_REG_ESP
+ X86_REG_FPSW
+ X86_REG_FS
+ X86_REG_GS
+ X86_REG_IP
+ X86_REG_RAX
+ X86_REG_RBP
+ X86_REG_RBX
+ X86_REG_RCX
+ X86_REG_RDI
+ X86_REG_RDX
+ X86_REG_RIP
+ X86_REG_RIZ
+ X86_REG_RSI
+ X86_REG_RSP
+ X86_REG_SI
+ X86_REG_SIL
+ X86_REG_SP
+ X86_REG_SPL
+ X86_REG_SS
+ X86_REG_CR0
+ X86_REG_CR1
+ X86_REG_CR2
+ X86_REG_CR3
+ X86_REG_CR4
+ X86_REG_CR5
+ X86_REG_CR6
+ X86_REG_CR7
+ X86_REG_CR8
+ X86_REG_CR9
+ X86_REG_CR10
+ X86_REG_CR11
+ X86_REG_CR12
+ X86_REG_CR13
+ X86_REG_CR14
+ X86_REG_CR15
+ X86_REG_DR0
+ X86_REG_DR1
+ X86_REG_DR2
+ X86_REG_DR3
+ X86_REG_DR4
+ X86_REG_DR5
+ X86_REG_DR6
+ X86_REG_DR7
+ X86_REG_FP0
+ X86_REG_FP1
+ X86_REG_FP2
+ X86_REG_FP3
+ X86_REG_FP4
+ X86_REG_FP5
+ X86_REG_FP6
+ X86_REG_FP7
+ X86_REG_K0
+ X86_REG_K1
+ X86_REG_K2
+ X86_REG_K3
+ X86_REG_K4
+ X86_REG_K5
+ X86_REG_K6
+ X86_REG_K7
+ X86_REG_MM0
+ X86_REG_MM1
+ X86_REG_MM2
+ X86_REG_MM3
+ X86_REG_MM4
+ X86_REG_MM5
+ X86_REG_MM6
+ X86_REG_MM7
+ X86_REG_R8
+ X86_REG_R9
+ X86_REG_R10
+ X86_REG_R11
+ X86_REG_R12
+ X86_REG_R13
+ X86_REG_R14
+ X86_REG_R15
+ X86_REG_ST0
+ X86_REG_ST1
+ X86_REG_ST2
+ X86_REG_ST3
+ X86_REG_ST4
+ X86_REG_ST5
+ X86_REG_ST6
+ X86_REG_ST7
+ X86_REG_XMM0
+ X86_REG_XMM1
+ X86_REG_XMM2
+ X86_REG_XMM3
+ X86_REG_XMM4
+ X86_REG_XMM5
+ X86_REG_XMM6
+ X86_REG_XMM7
+ X86_REG_XMM8
+ X86_REG_XMM9
+ X86_REG_XMM10
+ X86_REG_XMM11
+ X86_REG_XMM12
+ X86_REG_XMM13
+ X86_REG_XMM14
+ X86_REG_XMM15
+ X86_REG_XMM16
+ X86_REG_XMM17
+ X86_REG_XMM18
+ X86_REG_XMM19
+ X86_REG_XMM20
+ X86_REG_XMM21
+ X86_REG_XMM22
+ X86_REG_XMM23
+ X86_REG_XMM24
+ X86_REG_XMM25
+ X86_REG_XMM26
+ X86_REG_XMM27
+ X86_REG_XMM28
+ X86_REG_XMM29
+ X86_REG_XMM30
+ X86_REG_XMM31
+ X86_REG_YMM0
+ X86_REG_YMM1
+ X86_REG_YMM2
+ X86_REG_YMM3
+ X86_REG_YMM4
+ X86_REG_YMM5
+ X86_REG_YMM6
+ X86_REG_YMM7
+ X86_REG_YMM8
+ X86_REG_YMM9
+ X86_REG_YMM10
+ X86_REG_YMM11
+ X86_REG_YMM12
+ X86_REG_YMM13
+ X86_REG_YMM14
+ X86_REG_YMM15
+ X86_REG_YMM16
+ X86_REG_YMM17
+ X86_REG_YMM18
+ X86_REG_YMM19
+ X86_REG_YMM20
+ X86_REG_YMM21
+ X86_REG_YMM22
+ X86_REG_YMM23
+ X86_REG_YMM24
+ X86_REG_YMM25
+ X86_REG_YMM26
+ X86_REG_YMM27
+ X86_REG_YMM28
+ X86_REG_YMM29
+ X86_REG_YMM30
+ X86_REG_YMM31
+ X86_REG_ZMM0
+ X86_REG_ZMM1
+ X86_REG_ZMM2
+ X86_REG_ZMM3
+ X86_REG_ZMM4
+ X86_REG_ZMM5
+ X86_REG_ZMM6
+ X86_REG_ZMM7
+ X86_REG_ZMM8
+ X86_REG_ZMM9
+ X86_REG_ZMM10
+ X86_REG_ZMM11
+ X86_REG_ZMM12
+ X86_REG_ZMM13
+ X86_REG_ZMM14
+ X86_REG_ZMM15
+ X86_REG_ZMM16
+ X86_REG_ZMM17
+ X86_REG_ZMM18
+ X86_REG_ZMM19
+ X86_REG_ZMM20
+ X86_REG_ZMM21
+ X86_REG_ZMM22
+ X86_REG_ZMM23
+ X86_REG_ZMM24
+ X86_REG_ZMM25
+ X86_REG_ZMM26
+ X86_REG_ZMM27
+ X86_REG_ZMM28
+ X86_REG_ZMM29
+ X86_REG_ZMM30
+ X86_REG_ZMM31
+ X86_REG_R8B
+ X86_REG_R9B
+ X86_REG_R10B
+ X86_REG_R11B
+ X86_REG_R12B
+ X86_REG_R13B
+ X86_REG_R14B
+ X86_REG_R15B
+ X86_REG_R8D
+ X86_REG_R9D
+ X86_REG_R10D
+ X86_REG_R11D
+ X86_REG_R12D
+ X86_REG_R13D
+ X86_REG_R14D
+ X86_REG_R15D
+ X86_REG_R8W
+ X86_REG_R9W
+ X86_REG_R10W
+ X86_REG_R11W
+ X86_REG_R12W
+ X86_REG_R13W
+ X86_REG_R14W
+ X86_REG_R15W
+ X86_REG_ENDING ' <-- mark the end of the list of registers
+End Enum
+
+'Operand type for instruction's operands
+Enum x86_op_type
+ X86_OP_INVALID = 0 'CS_OP_INVALID (Uninitialized).
+ X86_OP_REG 'CS_OP_REG (Register operand).
+ X86_OP_IMM 'CS_OP_IMM (Immediate operand).
+ x86_op_mem 'CS_OP_MEM (Memory operand).
+ X86_OP_FP 'CS_OP_FP (Floating-Point operand).
+End Enum
+
+'AVX broadcast type
+Public Enum x86_avx_bcast
+ X86_AVX_BCAST_INVALID = 0 ' Uninitialized.
+ X86_AVX_BCAST_2 ' AVX512 broadcast type {1to2}
+ X86_AVX_BCAST_4 ' AVX512 broadcast type {1to4}
+ X86_AVX_BCAST_8 ' AVX512 broadcast type {1to8}
+ X86_AVX_BCAST_16 ' AVX512 broadcast type {1to16}
+End Enum
+
+
+'SSE Code Condition type
+Public Enum x86_sse_cc
+ X86_SSE_CC_INVALID = 0 ' Uninitialized.
+ X86_SSE_CC_EQ
+ X86_SSE_CC_LT
+ X86_SSE_CC_LE
+ X86_SSE_CC_UNORD
+ X86_SSE_CC_NEQ
+ X86_SSE_CC_NLT
+ X86_SSE_CC_NLE
+ X86_SSE_CC_ORD
+ X86_SSE_CC_EQ_UQ
+ X86_SSE_CC_NGE
+ X86_SSE_CC_NGT
+ X86_SSE_CC_FALSE
+ X86_SSE_CC_NEQ_OQ
+ X86_SSE_CC_GE
+ X86_SSE_CC_GT
+ X86_SSE_CC_TRUE
+End Enum
+
+'AVX Code Condition type
+Public Enum x86_avx_cc
+ X86_AVX_CC_INVALID = 0 ' Uninitialized.
+ X86_AVX_CC_EQ
+ X86_AVX_CC_LT
+ X86_AVX_CC_LE
+ X86_AVX_CC_UNORD
+ X86_AVX_CC_NEQ
+ X86_AVX_CC_NLT
+ X86_AVX_CC_NLE
+ X86_AVX_CC_ORD
+ X86_AVX_CC_EQ_UQ
+ X86_AVX_CC_NGE
+ X86_AVX_CC_NGT
+ X86_AVX_CC_FALSE
+ X86_AVX_CC_NEQ_OQ
+ X86_AVX_CC_GE
+ X86_AVX_CC_GT
+ X86_AVX_CC_TRUE
+ X86_AVX_CC_EQ_OS
+ X86_AVX_CC_LT_OQ
+ X86_AVX_CC_LE_OQ
+ X86_AVX_CC_UNORD_S
+ X86_AVX_CC_NEQ_US
+ X86_AVX_CC_NLT_UQ
+ X86_AVX_CC_NLE_UQ
+ X86_AVX_CC_ORD_S
+ X86_AVX_CC_EQ_US
+ X86_AVX_CC_NGE_UQ
+ X86_AVX_CC_NGT_UQ
+ X86_AVX_CC_FALSE_OS
+ X86_AVX_CC_NEQ_OS
+ X86_AVX_CC_GE_OQ
+ X86_AVX_CC_GT_OQ
+ X86_AVX_CC_TRUE_US
+End Enum
+
+'AVX static rounding mode type
+Public Enum x86_avx_rm
+ X86_AVX_RM_INVALID = 0 ' Uninitialized.
+ X86_AVX_RM_RN ' Round to nearest
+ X86_AVX_RM_RD ' Round down
+ X86_AVX_RM_RU ' Round up
+ X86_AVX_RM_RZ ' Round toward zero
+End Enum
+
+'Instruction prefixes - to be used in cs_x86.prefix[]
+Public Enum x86_prefix
+ X86_PREFIX_LOCK = &HF0 ' lock (cs_x86.prefix[0]
+ X86_PREFIX_REP = &HF3 ' rep (cs_x86.prefix[0]
+ X86_PREFIX_REPNE = &HF2 ' repne (cs_x86.prefix[0]
+ X86_PREFIX_CS = &H2E ' segment override CS (cs_x86.prefix[1]
+ X86_PREFIX_SS = &H36 ' segment override SS (cs_x86.prefix[1]
+ X86_PREFIX_DS = &H3E ' segment override DS (cs_x86.prefix[1]
+ X86_PREFIX_ES = &H26 ' segment override ES (cs_x86.prefix[1]
+ X86_PREFIX_FS = &H64 ' segment override FS (cs_x86.prefix[1]
+ X86_PREFIX_GS = &H65 ' segment override GS (cs_x86.prefix[1]
+ X86_PREFIX_OPSIZE = &H66 ' operand-size override (cs_x86.prefix[2]
+ X86_PREFIX_ADDRSIZE = &H67 ' address-size override (cs_x86.prefix[3]
+End Enum
+
+'Instruction's operand referring to memory
+'This is associated with X86_OP_MEM operand type above
+Public Type x86_op_mem
+ segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED
+ base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED
+ index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED
+ scale As Long ' scale for index register
+ disp As Currency ' displacement value
+End Type
+
+'Instruction operand 48 bytes
+'typedef struct cs_x86_op {
+' x86_op_type type; // operand type
+' union {
+' x86_reg reg; // register value for REG operand
+' int64_t imm; // immediate value for IMM operand
+' double fp; // floating point value for FP operand
+' x86_op_mem mem; // base/index/scale/disp value for MEM operand
+' };
+'
+' // size of this operand (in bytes).
+' uint8_t size;
+'
+' // AVX broadcast type, or 0 if irrelevant
+' x86_avx_bcast avx_bcast;
+'
+' // AVX zero opmask {z}
+' bool avx_zero_opmask;
+'} cs_x86_op;
+
+'Instruction structure
+Public Type cs_x86
+ ' Instruction prefix, which can be up to 4 bytes.
+ ' A prefix byte gets value 0 when irrelevant.
+ ' prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)
+ ' prefix[1] indicates segment override (irrelevant for x86_64):
+ ' See X86_PREFIX_CS/SS/DS/ES/FS/GS above.
+ ' prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)
+ ' prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)
+ prefix(0 To 3) As Byte ' UNSIGNED
+
+ ' Instruction opcode, wich can be from 1 to 4 bytes in size.
+ ' This contains VEX opcode as well.
+ ' An trailing opcode byte gets value 0 when irrelevant.
+ opcode(0 To 3) As Byte ' UNSIGNED
+
+ rex As Byte ' REX prefix: only a non-zero value is relavant for x86_64 UNSIGNED
+ addr_size As Byte ' Address size, which can be overrided with above prefix[5]. UNSIGNED
+ modrm As Byte ' ModR/M byte UNSIGNED
+ sib As Byte ' SIB value, or 0 when irrelevant. UNSIGNED
+ disp As Long ' Displacement value, or 0 when irrelevant.
+ sib_index As x86_reg ' SIB index register, or X86_REG_INVALID when irrelevant.
+ sib_scale As Byte ' SIB scale. only applicable if sib_index is relavant.
+ sib_base As x86_reg ' SIB base register, or X86_REG_INVALID when irrelevant.
+ sse_cc As x86_sse_cc ' SSE Code Condition
+ avx_cc As x86_avx_cc ' AVX Code Condition
+ avx_sae As Byte ' AVX Suppress all Exception
+ avx_rm As x86_avx_rm ' AVX static rounding mode
+ op_count As Byte ' Number of operands of this instruction, or 0 when instruction has no operand.UNSIGNED
+
+ 'operands(0 To 7) As cs_x86_op ' operands for this instruction.
+ 'opBuf(0 To 383) As Byte
+
+End Type
+
+'X86 instructions
+Public Enum x86_insn
+ X86_INS_INVALID = 0
+ X86_INS_AAA
+ X86_INS_AAD
+ X86_INS_AAM
+ X86_INS_AAS
+ X86_INS_FABS
+ X86_INS_ADC
+ X86_INS_ADCX
+ X86_INS_ADD
+ X86_INS_ADDPD
+ X86_INS_ADDPS
+ X86_INS_ADDSD
+ X86_INS_ADDSS
+ X86_INS_ADDSUBPD
+ X86_INS_ADDSUBPS
+ X86_INS_FADD
+ X86_INS_FIADD
+ X86_INS_FADDP
+ X86_INS_ADOX
+ X86_INS_AESDECLAST
+ X86_INS_AESDEC
+ X86_INS_AESENCLAST
+ X86_INS_AESENC
+ X86_INS_AESIMC
+ X86_INS_AESKEYGENASSIST
+ X86_INS_AND
+ X86_INS_ANDN
+ X86_INS_ANDNPD
+ X86_INS_ANDNPS
+ X86_INS_ANDPD
+ X86_INS_ANDPS
+ X86_INS_ARPL
+ X86_INS_BEXTR
+ X86_INS_BLCFILL
+ X86_INS_BLCI
+ X86_INS_BLCIC
+ X86_INS_BLCMSK
+ X86_INS_BLCS
+ X86_INS_BLENDPD
+ X86_INS_BLENDPS
+ X86_INS_BLENDVPD
+ X86_INS_BLENDVPS
+ X86_INS_BLSFILL
+ X86_INS_BLSI
+ X86_INS_BLSIC
+ X86_INS_BLSMSK
+ X86_INS_BLSR
+ X86_INS_BOUND
+ X86_INS_BSF
+ X86_INS_BSR
+ X86_INS_BSWAP
+ X86_INS_BT
+ X86_INS_BTC
+ X86_INS_BTR
+ X86_INS_BTS
+ X86_INS_BZHI
+ X86_INS_CALL
+ X86_INS_CBW
+ X86_INS_CDQ
+ X86_INS_CDQE
+ X86_INS_FCHS
+ X86_INS_CLAC
+ X86_INS_CLC
+ X86_INS_CLD
+ X86_INS_CLFLUSH
+ X86_INS_CLGI
+ X86_INS_CLI
+ X86_INS_CLTS
+ X86_INS_CMC
+ X86_INS_CMOVA
+ X86_INS_CMOVAE
+ X86_INS_CMOVB
+ X86_INS_CMOVBE
+ X86_INS_FCMOVBE
+ X86_INS_FCMOVB
+ X86_INS_CMOVE
+ X86_INS_FCMOVE
+ X86_INS_CMOVG
+ X86_INS_CMOVGE
+ X86_INS_CMOVL
+ X86_INS_CMOVLE
+ X86_INS_FCMOVNBE
+ X86_INS_FCMOVNB
+ X86_INS_CMOVNE
+ X86_INS_FCMOVNE
+ X86_INS_CMOVNO
+ X86_INS_CMOVNP
+ X86_INS_FCMOVNU
+ X86_INS_CMOVNS
+ X86_INS_CMOVO
+ X86_INS_CMOVP
+ X86_INS_FCMOVU
+ X86_INS_CMOVS
+ X86_INS_CMP
+ X86_INS_CMPPD
+ X86_INS_CMPPS
+ X86_INS_CMPSB
+ X86_INS_CMPSD
+ X86_INS_CMPSQ
+ X86_INS_CMPSS
+ X86_INS_CMPSW
+ X86_INS_CMPXCHG16B
+ X86_INS_CMPXCHG
+ X86_INS_CMPXCHG8B
+ X86_INS_COMISD
+ X86_INS_COMISS
+ X86_INS_FCOMP
+ X86_INS_FCOMPI
+ X86_INS_FCOMI
+ X86_INS_FCOM
+ X86_INS_FCOS
+ X86_INS_CPUID
+ X86_INS_CQO
+ X86_INS_CRC32
+ X86_INS_CVTDQ2PD
+ X86_INS_CVTDQ2PS
+ X86_INS_CVTPD2DQ
+ X86_INS_CVTPD2PS
+ X86_INS_CVTPS2DQ
+ X86_INS_CVTPS2PD
+ X86_INS_CVTSD2SI
+ X86_INS_CVTSD2SS
+ X86_INS_CVTSI2SD
+ X86_INS_CVTSI2SS
+ X86_INS_CVTSS2SD
+ X86_INS_CVTSS2SI
+ X86_INS_CVTTPD2DQ
+ X86_INS_CVTTPS2DQ
+ X86_INS_CVTTSD2SI
+ X86_INS_CVTTSS2SI
+ X86_INS_CWD
+ X86_INS_CWDE
+ X86_INS_DAA
+ X86_INS_DAS
+ X86_INS_DATA16
+ X86_INS_DEC
+ X86_INS_DIV
+ X86_INS_DIVPD
+ X86_INS_DIVPS
+ X86_INS_FDIVR
+ X86_INS_FIDIVR
+ X86_INS_FDIVRP
+ X86_INS_DIVSD
+ X86_INS_DIVSS
+ X86_INS_FDIV
+ X86_INS_FIDIV
+ X86_INS_FDIVP
+ X86_INS_DPPD
+ X86_INS_DPPS
+ X86_INS_RET
+ X86_INS_ENCLS
+ X86_INS_ENCLU
+ X86_INS_ENTER
+ X86_INS_EXTRACTPS
+ X86_INS_EXTRQ
+ X86_INS_F2XM1
+ X86_INS_LCALL
+ X86_INS_LJMP
+ X86_INS_FBLD
+ X86_INS_FBSTP
+ X86_INS_FCOMPP
+ X86_INS_FDECSTP
+ X86_INS_FEMMS
+ X86_INS_FFREE
+ X86_INS_FICOM
+ X86_INS_FICOMP
+ X86_INS_FINCSTP
+ X86_INS_FLDCW
+ X86_INS_FLDENV
+ X86_INS_FLDL2E
+ X86_INS_FLDL2T
+ X86_INS_FLDLG2
+ X86_INS_FLDLN2
+ X86_INS_FLDPI
+ X86_INS_FNCLEX
+ X86_INS_FNINIT
+ X86_INS_FNOP
+ X86_INS_FNSTCW
+ X86_INS_FNSTSW
+ X86_INS_FPATAN
+ X86_INS_FPREM
+ X86_INS_FPREM1
+ X86_INS_FPTAN
+ X86_INS_FRNDINT
+ X86_INS_FRSTOR
+ X86_INS_FNSAVE
+ X86_INS_FSCALE
+ X86_INS_FSETPM
+ X86_INS_FSINCOS
+ X86_INS_FNSTENV
+ X86_INS_FXAM
+ X86_INS_FXRSTOR
+ X86_INS_FXRSTOR64
+ X86_INS_FXSAVE
+ X86_INS_FXSAVE64
+ X86_INS_FXTRACT
+ X86_INS_FYL2X
+ X86_INS_FYL2XP1
+ X86_INS_MOVAPD
+ X86_INS_MOVAPS
+ X86_INS_ORPD
+ X86_INS_ORPS
+ X86_INS_VMOVAPD
+ X86_INS_VMOVAPS
+ X86_INS_XORPD
+ X86_INS_XORPS
+ X86_INS_GETSEC
+ X86_INS_HADDPD
+ X86_INS_HADDPS
+ X86_INS_HLT
+ X86_INS_HSUBPD
+ X86_INS_HSUBPS
+ X86_INS_IDIV
+ X86_INS_FILD
+ X86_INS_IMUL
+ X86_INS_IN
+ X86_INS_INC
+ X86_INS_INSB
+ X86_INS_INSERTPS
+ X86_INS_INSERTQ
+ X86_INS_INSD
+ X86_INS_INSW
+ X86_INS_INT
+ X86_INS_INT1
+ X86_INS_INT3
+ X86_INS_INTO
+ X86_INS_INVD
+ X86_INS_INVEPT
+ X86_INS_INVLPG
+ X86_INS_INVLPGA
+ X86_INS_INVPCID
+ X86_INS_INVVPID
+ X86_INS_IRET
+ X86_INS_IRETD
+ X86_INS_IRETQ
+ X86_INS_FISTTP
+ X86_INS_FIST
+ X86_INS_FISTP
+ X86_INS_UCOMISD
+ X86_INS_UCOMISS
+ X86_INS_VCMP
+ X86_INS_VCOMISD
+ X86_INS_VCOMISS
+ X86_INS_VCVTSD2SS
+ X86_INS_VCVTSI2SD
+ X86_INS_VCVTSI2SS
+ X86_INS_VCVTSS2SD
+ X86_INS_VCVTTSD2SI
+ X86_INS_VCVTTSD2USI
+ X86_INS_VCVTTSS2SI
+ X86_INS_VCVTTSS2USI
+ X86_INS_VCVTUSI2SD
+ X86_INS_VCVTUSI2SS
+ X86_INS_VUCOMISD
+ X86_INS_VUCOMISS
+ X86_INS_JAE
+ X86_INS_JA
+ X86_INS_JBE
+ X86_INS_JB
+ X86_INS_JCXZ
+ X86_INS_JECXZ
+ X86_INS_JE
+ X86_INS_JGE
+ X86_INS_JG
+ X86_INS_JLE
+ X86_INS_JL
+ X86_INS_JMP
+ X86_INS_JNE
+ X86_INS_JNO
+ X86_INS_JNP
+ X86_INS_JNS
+ X86_INS_JO
+ X86_INS_JP
+ X86_INS_JRCXZ
+ X86_INS_JS
+ X86_INS_KANDB
+ X86_INS_KANDD
+ X86_INS_KANDNB
+ X86_INS_KANDND
+ X86_INS_KANDNQ
+ X86_INS_KANDNW
+ X86_INS_KANDQ
+ X86_INS_KANDW
+ X86_INS_KMOVB
+ X86_INS_KMOVD
+ X86_INS_KMOVQ
+ X86_INS_KMOVW
+ X86_INS_KNOTB
+ X86_INS_KNOTD
+ X86_INS_KNOTQ
+ X86_INS_KNOTW
+ X86_INS_KORB
+ X86_INS_KORD
+ X86_INS_KORQ
+ X86_INS_KORTESTW
+ X86_INS_KORW
+ X86_INS_KSHIFTLW
+ X86_INS_KSHIFTRW
+ X86_INS_KUNPCKBW
+ X86_INS_KXNORB
+ X86_INS_KXNORD
+ X86_INS_KXNORQ
+ X86_INS_KXNORW
+ X86_INS_KXORB
+ X86_INS_KXORD
+ X86_INS_KXORQ
+ X86_INS_KXORW
+ X86_INS_LAHF
+ X86_INS_LAR
+ X86_INS_LDDQU
+ X86_INS_LDMXCSR
+ X86_INS_LDS
+ X86_INS_FLDZ
+ X86_INS_FLD1
+ X86_INS_FLD
+ X86_INS_LEA
+ X86_INS_LEAVE
+ X86_INS_LES
+ X86_INS_LFENCE
+ X86_INS_LFS
+ X86_INS_LGDT
+ X86_INS_LGS
+ X86_INS_LIDT
+ X86_INS_LLDT
+ X86_INS_LMSW
+ X86_INS_OR
+ X86_INS_SUB
+ X86_INS_XOR
+ X86_INS_LODSB
+ X86_INS_LODSD
+ X86_INS_LODSQ
+ X86_INS_LODSW
+ X86_INS_LOOP
+ X86_INS_LOOPE
+ X86_INS_LOOPNE
+ X86_INS_RETF
+ X86_INS_RETFQ
+ X86_INS_LSL
+ X86_INS_LSS
+ X86_INS_LTR
+ X86_INS_XADD
+ X86_INS_LZCNT
+ X86_INS_MASKMOVDQU
+ X86_INS_MAXPD
+ X86_INS_MAXPS
+ X86_INS_MAXSD
+ X86_INS_MAXSS
+ X86_INS_MFENCE
+ X86_INS_MINPD
+ X86_INS_MINPS
+ X86_INS_MINSD
+ X86_INS_MINSS
+ X86_INS_CVTPD2PI
+ X86_INS_CVTPI2PD
+ X86_INS_CVTPI2PS
+ X86_INS_CVTPS2PI
+ X86_INS_CVTTPD2PI
+ X86_INS_CVTTPS2PI
+ X86_INS_EMMS
+ X86_INS_MASKMOVQ
+ X86_INS_MOVD
+ X86_INS_MOVDQ2Q
+ X86_INS_MOVNTQ
+ X86_INS_MOVQ2DQ
+ X86_INS_MOVQ
+ X86_INS_PABSB
+ X86_INS_PABSD
+ X86_INS_PABSW
+ X86_INS_PACKSSDW
+ X86_INS_PACKSSWB
+ X86_INS_PACKUSWB
+ X86_INS_PADDB
+ X86_INS_PADDD
+ X86_INS_PADDQ
+ X86_INS_PADDSB
+ X86_INS_PADDSW
+ X86_INS_PADDUSB
+ X86_INS_PADDUSW
+ X86_INS_PADDW
+ X86_INS_PALIGNR
+ X86_INS_PANDN
+ X86_INS_PAND
+ X86_INS_PAVGB
+ X86_INS_PAVGW
+ X86_INS_PCMPEQB
+ X86_INS_PCMPEQD
+ X86_INS_PCMPEQW
+ X86_INS_PCMPGTB
+ X86_INS_PCMPGTD
+ X86_INS_PCMPGTW
+ X86_INS_PEXTRW
+ X86_INS_PHADDSW
+ X86_INS_PHADDW
+ X86_INS_PHADDD
+ X86_INS_PHSUBD
+ X86_INS_PHSUBSW
+ X86_INS_PHSUBW
+ X86_INS_PINSRW
+ X86_INS_PMADDUBSW
+ X86_INS_PMADDWD
+ X86_INS_PMAXSW
+ X86_INS_PMAXUB
+ X86_INS_PMINSW
+ X86_INS_PMINUB
+ X86_INS_PMOVMSKB
+ X86_INS_PMULHRSW
+ X86_INS_PMULHUW
+ X86_INS_PMULHW
+ X86_INS_PMULLW
+ X86_INS_PMULUDQ
+ X86_INS_POR
+ X86_INS_PSADBW
+ X86_INS_PSHUFB
+ X86_INS_PSHUFW
+ X86_INS_PSIGNB
+ X86_INS_PSIGND
+ X86_INS_PSIGNW
+ X86_INS_PSLLD
+ X86_INS_PSLLQ
+ X86_INS_PSLLW
+ X86_INS_PSRAD
+ X86_INS_PSRAW
+ X86_INS_PSRLD
+ X86_INS_PSRLQ
+ X86_INS_PSRLW
+ X86_INS_PSUBB
+ X86_INS_PSUBD
+ X86_INS_PSUBQ
+ X86_INS_PSUBSB
+ X86_INS_PSUBSW
+ X86_INS_PSUBUSB
+ X86_INS_PSUBUSW
+ X86_INS_PSUBW
+ X86_INS_PUNPCKHBW
+ X86_INS_PUNPCKHDQ
+ X86_INS_PUNPCKHWD
+ X86_INS_PUNPCKLBW
+ X86_INS_PUNPCKLDQ
+ X86_INS_PUNPCKLWD
+ X86_INS_PXOR
+ X86_INS_MONITOR
+ X86_INS_MONTMUL
+ X86_INS_MOV
+ X86_INS_MOVABS
+ X86_INS_MOVBE
+ X86_INS_MOVDDUP
+ X86_INS_MOVDQA
+ X86_INS_MOVDQU
+ X86_INS_MOVHLPS
+ X86_INS_MOVHPD
+ X86_INS_MOVHPS
+ X86_INS_MOVLHPS
+ X86_INS_MOVLPD
+ X86_INS_MOVLPS
+ X86_INS_MOVMSKPD
+ X86_INS_MOVMSKPS
+ X86_INS_MOVNTDQA
+ X86_INS_MOVNTDQ
+ X86_INS_MOVNTI
+ X86_INS_MOVNTPD
+ X86_INS_MOVNTPS
+ X86_INS_MOVNTSD
+ X86_INS_MOVNTSS
+ X86_INS_MOVSB
+ X86_INS_MOVSD
+ X86_INS_MOVSHDUP
+ X86_INS_MOVSLDUP
+ X86_INS_MOVSQ
+ X86_INS_MOVSS
+ X86_INS_MOVSW
+ X86_INS_MOVSX
+ X86_INS_MOVSXD
+ X86_INS_MOVUPD
+ X86_INS_MOVUPS
+ X86_INS_MOVZX
+ X86_INS_MPSADBW
+ X86_INS_MUL
+ X86_INS_MULPD
+ X86_INS_MULPS
+ X86_INS_MULSD
+ X86_INS_MULSS
+ X86_INS_MULX
+ X86_INS_FMUL
+ X86_INS_FIMUL
+ X86_INS_FMULP
+ X86_INS_MWAIT
+ X86_INS_NEG
+ X86_INS_NOP
+ X86_INS_NOT
+ X86_INS_OUT
+ X86_INS_OUTSB
+ X86_INS_OUTSD
+ X86_INS_OUTSW
+ X86_INS_PACKUSDW
+ X86_INS_PAUSE
+ X86_INS_PAVGUSB
+ X86_INS_PBLENDVB
+ X86_INS_PBLENDW
+ X86_INS_PCLMULQDQ
+ X86_INS_PCMPEQQ
+ X86_INS_PCMPESTRI
+ X86_INS_PCMPESTRM
+ X86_INS_PCMPGTQ
+ X86_INS_PCMPISTRI
+ X86_INS_PCMPISTRM
+ X86_INS_PDEP
+ X86_INS_PEXT
+ X86_INS_PEXTRB
+ X86_INS_PEXTRD
+ X86_INS_PEXTRQ
+ X86_INS_PF2ID
+ X86_INS_PF2IW
+ X86_INS_PFACC
+ X86_INS_PFADD
+ X86_INS_PFCMPEQ
+ X86_INS_PFCMPGE
+ X86_INS_PFCMPGT
+ X86_INS_PFMAX
+ X86_INS_PFMIN
+ X86_INS_PFMUL
+ X86_INS_PFNACC
+ X86_INS_PFPNACC
+ X86_INS_PFRCPIT1
+ X86_INS_PFRCPIT2
+ X86_INS_PFRCP
+ X86_INS_PFRSQIT1
+ X86_INS_PFRSQRT
+ X86_INS_PFSUBR
+ X86_INS_PFSUB
+ X86_INS_PHMINPOSUW
+ X86_INS_PI2FD
+ X86_INS_PI2FW
+ X86_INS_PINSRB
+ X86_INS_PINSRD
+ X86_INS_PINSRQ
+ X86_INS_PMAXSB
+ X86_INS_PMAXSD
+ X86_INS_PMAXUD
+ X86_INS_PMAXUW
+ X86_INS_PMINSB
+ X86_INS_PMINSD
+ X86_INS_PMINUD
+ X86_INS_PMINUW
+ X86_INS_PMOVSXBD
+ X86_INS_PMOVSXBQ
+ X86_INS_PMOVSXBW
+ X86_INS_PMOVSXDQ
+ X86_INS_PMOVSXWD
+ X86_INS_PMOVSXWQ
+ X86_INS_PMOVZXBD
+ X86_INS_PMOVZXBQ
+ X86_INS_PMOVZXBW
+ X86_INS_PMOVZXDQ
+ X86_INS_PMOVZXWD
+ X86_INS_PMOVZXWQ
+ X86_INS_PMULDQ
+ X86_INS_PMULHRW
+ X86_INS_PMULLD
+ X86_INS_POP
+ X86_INS_POPAW
+ X86_INS_POPAL
+ X86_INS_POPCNT
+ X86_INS_POPF
+ X86_INS_POPFD
+ X86_INS_POPFQ
+ X86_INS_PREFETCH
+ X86_INS_PREFETCHNTA
+ X86_INS_PREFETCHT0
+ X86_INS_PREFETCHT1
+ X86_INS_PREFETCHT2
+ X86_INS_PREFETCHW
+ X86_INS_PSHUFD
+ X86_INS_PSHUFHW
+ X86_INS_PSHUFLW
+ X86_INS_PSLLDQ
+ X86_INS_PSRLDQ
+ X86_INS_PSWAPD
+ X86_INS_PTEST
+ X86_INS_PUNPCKHQDQ
+ X86_INS_PUNPCKLQDQ
+ X86_INS_PUSH
+ X86_INS_PUSHAW
+ X86_INS_PUSHAL
+ X86_INS_PUSHF
+ X86_INS_PUSHFD
+ X86_INS_PUSHFQ
+ X86_INS_RCL
+ X86_INS_RCPPS
+ X86_INS_RCPSS
+ X86_INS_RCR
+ X86_INS_RDFSBASE
+ X86_INS_RDGSBASE
+ X86_INS_RDMSR
+ X86_INS_RDPMC
+ X86_INS_RDRAND
+ X86_INS_RDSEED
+ X86_INS_RDTSC
+ X86_INS_RDTSCP
+ X86_INS_ROL
+ X86_INS_ROR
+ X86_INS_RORX
+ X86_INS_ROUNDPD
+ X86_INS_ROUNDPS
+ X86_INS_ROUNDSD
+ X86_INS_ROUNDSS
+ X86_INS_RSM
+ X86_INS_RSQRTPS
+ X86_INS_RSQRTSS
+ X86_INS_SAHF
+ X86_INS_SAL
+ X86_INS_SALC
+ X86_INS_SAR
+ X86_INS_SARX
+ X86_INS_SBB
+ X86_INS_SCASB
+ X86_INS_SCASD
+ X86_INS_SCASQ
+ X86_INS_SCASW
+ X86_INS_SETAE
+ X86_INS_SETA
+ X86_INS_SETBE
+ X86_INS_SETB
+ X86_INS_SETE
+ X86_INS_SETGE
+ X86_INS_SETG
+ X86_INS_SETLE
+ X86_INS_SETL
+ X86_INS_SETNE
+ X86_INS_SETNO
+ X86_INS_SETNP
+ X86_INS_SETNS
+ X86_INS_SETO
+ X86_INS_SETP
+ X86_INS_SETS
+ X86_INS_SFENCE
+ X86_INS_SGDT
+ X86_INS_SHA1MSG1
+ X86_INS_SHA1MSG2
+ X86_INS_SHA1NEXTE
+ X86_INS_SHA1RNDS4
+ X86_INS_SHA256MSG1
+ X86_INS_SHA256MSG2
+ X86_INS_SHA256RNDS2
+ X86_INS_SHL
+ X86_INS_SHLD
+ X86_INS_SHLX
+ X86_INS_SHR
+ X86_INS_SHRD
+ X86_INS_SHRX
+ X86_INS_SHUFPD
+ X86_INS_SHUFPS
+ X86_INS_SIDT
+ X86_INS_FSIN
+ X86_INS_SKINIT
+ X86_INS_SLDT
+ X86_INS_SMSW
+ X86_INS_SQRTPD
+ X86_INS_SQRTPS
+ X86_INS_SQRTSD
+ X86_INS_SQRTSS
+ X86_INS_FSQRT
+ X86_INS_STAC
+ X86_INS_STC
+ X86_INS_STD
+ X86_INS_STGI
+ X86_INS_STI
+ X86_INS_STMXCSR
+ X86_INS_STOSB
+ X86_INS_STOSD
+ X86_INS_STOSQ
+ X86_INS_STOSW
+ X86_INS_STR
+ X86_INS_FST
+ X86_INS_FSTP
+ X86_INS_FSTPNCE
+ X86_INS_SUBPD
+ X86_INS_SUBPS
+ X86_INS_FSUBR
+ X86_INS_FISUBR
+ X86_INS_FSUBRP
+ X86_INS_SUBSD
+ X86_INS_SUBSS
+ X86_INS_FSUB
+ X86_INS_FISUB
+ X86_INS_FSUBP
+ X86_INS_SWAPGS
+ X86_INS_SYSCALL
+ X86_INS_SYSENTER
+ X86_INS_SYSEXIT
+ X86_INS_SYSRET
+ X86_INS_T1MSKC
+ X86_INS_TEST
+ X86_INS_UD2
+ X86_INS_FTST
+ X86_INS_TZCNT
+ X86_INS_TZMSK
+ X86_INS_FUCOMPI
+ X86_INS_FUCOMI
+ X86_INS_FUCOMPP
+ X86_INS_FUCOMP
+ X86_INS_FUCOM
+ X86_INS_UD2B
+ X86_INS_UNPCKHPD
+ X86_INS_UNPCKHPS
+ X86_INS_UNPCKLPD
+ X86_INS_UNPCKLPS
+ X86_INS_VADDPD
+ X86_INS_VADDPS
+ X86_INS_VADDSD
+ X86_INS_VADDSS
+ X86_INS_VADDSUBPD
+ X86_INS_VADDSUBPS
+ X86_INS_VAESDECLAST
+ X86_INS_VAESDEC
+ X86_INS_VAESENCLAST
+ X86_INS_VAESENC
+ X86_INS_VAESIMC
+ X86_INS_VAESKEYGENASSIST
+ X86_INS_VALIGND
+ X86_INS_VALIGNQ
+ X86_INS_VANDNPD
+ X86_INS_VANDNPS
+ X86_INS_VANDPD
+ X86_INS_VANDPS
+ X86_INS_VBLENDMPD
+ X86_INS_VBLENDMPS
+ X86_INS_VBLENDPD
+ X86_INS_VBLENDPS
+ X86_INS_VBLENDVPD
+ X86_INS_VBLENDVPS
+ X86_INS_VBROADCASTF128
+ X86_INS_VBROADCASTI128
+ X86_INS_VBROADCASTI32X4
+ X86_INS_VBROADCASTI64X4
+ X86_INS_VBROADCASTSD
+ X86_INS_VBROADCASTSS
+ X86_INS_VCMPPD
+ X86_INS_VCMPPS
+ X86_INS_VCMPSD
+ X86_INS_VCMPSS
+ X86_INS_VCVTDQ2PD
+ X86_INS_VCVTDQ2PS
+ X86_INS_VCVTPD2DQX
+ X86_INS_VCVTPD2DQ
+ X86_INS_VCVTPD2PSX
+ X86_INS_VCVTPD2PS
+ X86_INS_VCVTPD2UDQ
+ X86_INS_VCVTPH2PS
+ X86_INS_VCVTPS2DQ
+ X86_INS_VCVTPS2PD
+ X86_INS_VCVTPS2PH
+ X86_INS_VCVTPS2UDQ
+ X86_INS_VCVTSD2SI
+ X86_INS_VCVTSD2USI
+ X86_INS_VCVTSS2SI
+ X86_INS_VCVTSS2USI
+ X86_INS_VCVTTPD2DQX
+ X86_INS_VCVTTPD2DQ
+ X86_INS_VCVTTPD2UDQ
+ X86_INS_VCVTTPS2DQ
+ X86_INS_VCVTTPS2UDQ
+ X86_INS_VCVTUDQ2PD
+ X86_INS_VCVTUDQ2PS
+ X86_INS_VDIVPD
+ X86_INS_VDIVPS
+ X86_INS_VDIVSD
+ X86_INS_VDIVSS
+ X86_INS_VDPPD
+ X86_INS_VDPPS
+ X86_INS_VERR
+ X86_INS_VERW
+ X86_INS_VEXTRACTF128
+ X86_INS_VEXTRACTF32X4
+ X86_INS_VEXTRACTF64X4
+ X86_INS_VEXTRACTI128
+ X86_INS_VEXTRACTI32X4
+ X86_INS_VEXTRACTI64X4
+ X86_INS_VEXTRACTPS
+ X86_INS_VFMADD132PD
+ X86_INS_VFMADD132PS
+ X86_INS_VFMADD213PD
+ X86_INS_VFMADD213PS
+ X86_INS_VFMADDPD
+ X86_INS_VFMADD231PD
+ X86_INS_VFMADDPS
+ X86_INS_VFMADD231PS
+ X86_INS_VFMADDSD
+ X86_INS_VFMADD213SD
+ X86_INS_VFMADD132SD
+ X86_INS_VFMADD231SD
+ X86_INS_VFMADDSS
+ X86_INS_VFMADD213SS
+ X86_INS_VFMADD132SS
+ X86_INS_VFMADD231SS
+ X86_INS_VFMADDSUB132PD
+ X86_INS_VFMADDSUB132PS
+ X86_INS_VFMADDSUB213PD
+ X86_INS_VFMADDSUB213PS
+ X86_INS_VFMADDSUBPD
+ X86_INS_VFMADDSUB231PD
+ X86_INS_VFMADDSUBPS
+ X86_INS_VFMADDSUB231PS
+ X86_INS_VFMSUB132PD
+ X86_INS_VFMSUB132PS
+ X86_INS_VFMSUB213PD
+ X86_INS_VFMSUB213PS
+ X86_INS_VFMSUBADD132PD
+ X86_INS_VFMSUBADD132PS
+ X86_INS_VFMSUBADD213PD
+ X86_INS_VFMSUBADD213PS
+ X86_INS_VFMSUBADDPD
+ X86_INS_VFMSUBADD231PD
+ X86_INS_VFMSUBADDPS
+ X86_INS_VFMSUBADD231PS
+ X86_INS_VFMSUBPD
+ X86_INS_VFMSUB231PD
+ X86_INS_VFMSUBPS
+ X86_INS_VFMSUB231PS
+ X86_INS_VFMSUBSD
+ X86_INS_VFMSUB213SD
+ X86_INS_VFMSUB132SD
+ X86_INS_VFMSUB231SD
+ X86_INS_VFMSUBSS
+ X86_INS_VFMSUB213SS
+ X86_INS_VFMSUB132SS
+ X86_INS_VFMSUB231SS
+ X86_INS_VFNMADD132PD
+ X86_INS_VFNMADD132PS
+ X86_INS_VFNMADD213PD
+ X86_INS_VFNMADD213PS
+ X86_INS_VFNMADDPD
+ X86_INS_VFNMADD231PD
+ X86_INS_VFNMADDPS
+ X86_INS_VFNMADD231PS
+ X86_INS_VFNMADDSD
+ X86_INS_VFNMADD213SD
+ X86_INS_VFNMADD132SD
+ X86_INS_VFNMADD231SD
+ X86_INS_VFNMADDSS
+ X86_INS_VFNMADD213SS
+ X86_INS_VFNMADD132SS
+ X86_INS_VFNMADD231SS
+ X86_INS_VFNMSUB132PD
+ X86_INS_VFNMSUB132PS
+ X86_INS_VFNMSUB213PD
+ X86_INS_VFNMSUB213PS
+ X86_INS_VFNMSUBPD
+ X86_INS_VFNMSUB231PD
+ X86_INS_VFNMSUBPS
+ X86_INS_VFNMSUB231PS
+ X86_INS_VFNMSUBSD
+ X86_INS_VFNMSUB213SD
+ X86_INS_VFNMSUB132SD
+ X86_INS_VFNMSUB231SD
+ X86_INS_VFNMSUBSS
+ X86_INS_VFNMSUB213SS
+ X86_INS_VFNMSUB132SS
+ X86_INS_VFNMSUB231SS
+ X86_INS_VFRCZPD
+ X86_INS_VFRCZPS
+ X86_INS_VFRCZSD
+ X86_INS_VFRCZSS
+ X86_INS_VORPD
+ X86_INS_VORPS
+ X86_INS_VXORPD
+ X86_INS_VXORPS
+ X86_INS_VGATHERDPD
+ X86_INS_VGATHERDPS
+ X86_INS_VGATHERPF0DPD
+ X86_INS_VGATHERPF0DPS
+ X86_INS_VGATHERPF0QPD
+ X86_INS_VGATHERPF0QPS
+ X86_INS_VGATHERPF1DPD
+ X86_INS_VGATHERPF1DPS
+ X86_INS_VGATHERPF1QPD
+ X86_INS_VGATHERPF1QPS
+ X86_INS_VGATHERQPD
+ X86_INS_VGATHERQPS
+ X86_INS_VHADDPD
+ X86_INS_VHADDPS
+ X86_INS_VHSUBPD
+ X86_INS_VHSUBPS
+ X86_INS_VINSERTF128
+ X86_INS_VINSERTF32X4
+ X86_INS_VINSERTF64X4
+ X86_INS_VINSERTI128
+ X86_INS_VINSERTI32X4
+ X86_INS_VINSERTI64X4
+ X86_INS_VINSERTPS
+ X86_INS_VLDDQU
+ X86_INS_VLDMXCSR
+ X86_INS_VMASKMOVDQU
+ X86_INS_VMASKMOVPD
+ X86_INS_VMASKMOVPS
+ X86_INS_VMAXPD
+ X86_INS_VMAXPS
+ X86_INS_VMAXSD
+ X86_INS_VMAXSS
+ X86_INS_VMCALL
+ X86_INS_VMCLEAR
+ X86_INS_VMFUNC
+ X86_INS_VMINPD
+ X86_INS_VMINPS
+ X86_INS_VMINSD
+ X86_INS_VMINSS
+ X86_INS_VMLAUNCH
+ X86_INS_VMLOAD
+ X86_INS_VMMCALL
+ X86_INS_VMOVQ
+ X86_INS_VMOVDDUP
+ X86_INS_VMOVD
+ X86_INS_VMOVDQA32
+ X86_INS_VMOVDQA64
+ X86_INS_VMOVDQA
+ X86_INS_VMOVDQU16
+ X86_INS_VMOVDQU32
+ X86_INS_VMOVDQU64
+ X86_INS_VMOVDQU8
+ X86_INS_VMOVDQU
+ X86_INS_VMOVHLPS
+ X86_INS_VMOVHPD
+ X86_INS_VMOVHPS
+ X86_INS_VMOVLHPS
+ X86_INS_VMOVLPD
+ X86_INS_VMOVLPS
+ X86_INS_VMOVMSKPD
+ X86_INS_VMOVMSKPS
+ X86_INS_VMOVNTDQA
+ X86_INS_VMOVNTDQ
+ X86_INS_VMOVNTPD
+ X86_INS_VMOVNTPS
+ X86_INS_VMOVSD
+ X86_INS_VMOVSHDUP
+ X86_INS_VMOVSLDUP
+ X86_INS_VMOVSS
+ X86_INS_VMOVUPD
+ X86_INS_VMOVUPS
+ X86_INS_VMPSADBW
+ X86_INS_VMPTRLD
+ X86_INS_VMPTRST
+ X86_INS_VMREAD
+ X86_INS_VMRESUME
+ X86_INS_VMRUN
+ X86_INS_VMSAVE
+ X86_INS_VMULPD
+ X86_INS_VMULPS
+ X86_INS_VMULSD
+ X86_INS_VMULSS
+ X86_INS_VMWRITE
+ X86_INS_VMXOFF
+ X86_INS_VMXON
+ X86_INS_VPABSB
+ X86_INS_VPABSD
+ X86_INS_VPABSQ
+ X86_INS_VPABSW
+ X86_INS_VPACKSSDW
+ X86_INS_VPACKSSWB
+ X86_INS_VPACKUSDW
+ X86_INS_VPACKUSWB
+ X86_INS_VPADDB
+ X86_INS_VPADDD
+ X86_INS_VPADDQ
+ X86_INS_VPADDSB
+ X86_INS_VPADDSW
+ X86_INS_VPADDUSB
+ X86_INS_VPADDUSW
+ X86_INS_VPADDW
+ X86_INS_VPALIGNR
+ X86_INS_VPANDD
+ X86_INS_VPANDND
+ X86_INS_VPANDNQ
+ X86_INS_VPANDN
+ X86_INS_VPANDQ
+ X86_INS_VPAND
+ X86_INS_VPAVGB
+ X86_INS_VPAVGW
+ X86_INS_VPBLENDD
+ X86_INS_VPBLENDMD
+ X86_INS_VPBLENDMQ
+ X86_INS_VPBLENDVB
+ X86_INS_VPBLENDW
+ X86_INS_VPBROADCASTB
+ X86_INS_VPBROADCASTD
+ X86_INS_VPBROADCASTMB2Q
+ X86_INS_VPBROADCASTMW2D
+ X86_INS_VPBROADCASTQ
+ X86_INS_VPBROADCASTW
+ X86_INS_VPCLMULQDQ
+ X86_INS_VPCMOV
+ X86_INS_VPCMP
+ X86_INS_VPCMPD
+ X86_INS_VPCMPEQB
+ X86_INS_VPCMPEQD
+ X86_INS_VPCMPEQQ
+ X86_INS_VPCMPEQW
+ X86_INS_VPCMPESTRI
+ X86_INS_VPCMPESTRM
+ X86_INS_VPCMPGTB
+ X86_INS_VPCMPGTD
+ X86_INS_VPCMPGTQ
+ X86_INS_VPCMPGTW
+ X86_INS_VPCMPISTRI
+ X86_INS_VPCMPISTRM
+ X86_INS_VPCMPQ
+ X86_INS_VPCMPUD
+ X86_INS_VPCMPUQ
+ X86_INS_VPCOMB
+ X86_INS_VPCOMD
+ X86_INS_VPCOMQ
+ X86_INS_VPCOMUB
+ X86_INS_VPCOMUD
+ X86_INS_VPCOMUQ
+ X86_INS_VPCOMUW
+ X86_INS_VPCOMW
+ X86_INS_VPCONFLICTD
+ X86_INS_VPCONFLICTQ
+ X86_INS_VPERM2F128
+ X86_INS_VPERM2I128
+ X86_INS_VPERMD
+ X86_INS_VPERMI2D
+ X86_INS_VPERMI2PD
+ X86_INS_VPERMI2PS
+ X86_INS_VPERMI2Q
+ X86_INS_VPERMIL2PD
+ X86_INS_VPERMIL2PS
+ X86_INS_VPERMILPD
+ X86_INS_VPERMILPS
+ X86_INS_VPERMPD
+ X86_INS_VPERMPS
+ X86_INS_VPERMQ
+ X86_INS_VPERMT2D
+ X86_INS_VPERMT2PD
+ X86_INS_VPERMT2PS
+ X86_INS_VPERMT2Q
+ X86_INS_VPEXTRB
+ X86_INS_VPEXTRD
+ X86_INS_VPEXTRQ
+ X86_INS_VPEXTRW
+ X86_INS_VPGATHERDD
+ X86_INS_VPGATHERDQ
+ X86_INS_VPGATHERQD
+ X86_INS_VPGATHERQQ
+ X86_INS_VPHADDBD
+ X86_INS_VPHADDBQ
+ X86_INS_VPHADDBW
+ X86_INS_VPHADDDQ
+ X86_INS_VPHADDD
+ X86_INS_VPHADDSW
+ X86_INS_VPHADDUBD
+ X86_INS_VPHADDUBQ
+ X86_INS_VPHADDUBW
+ X86_INS_VPHADDUDQ
+ X86_INS_VPHADDUWD
+ X86_INS_VPHADDUWQ
+ X86_INS_VPHADDWD
+ X86_INS_VPHADDWQ
+ X86_INS_VPHADDW
+ X86_INS_VPHMINPOSUW
+ X86_INS_VPHSUBBW
+ X86_INS_VPHSUBDQ
+ X86_INS_VPHSUBD
+ X86_INS_VPHSUBSW
+ X86_INS_VPHSUBWD
+ X86_INS_VPHSUBW
+ X86_INS_VPINSRB
+ X86_INS_VPINSRD
+ X86_INS_VPINSRQ
+ X86_INS_VPINSRW
+ X86_INS_VPLZCNTD
+ X86_INS_VPLZCNTQ
+ X86_INS_VPMACSDD
+ X86_INS_VPMACSDQH
+ X86_INS_VPMACSDQL
+ X86_INS_VPMACSSDD
+ X86_INS_VPMACSSDQH
+ X86_INS_VPMACSSDQL
+ X86_INS_VPMACSSWD
+ X86_INS_VPMACSSWW
+ X86_INS_VPMACSWD
+ X86_INS_VPMACSWW
+ X86_INS_VPMADCSSWD
+ X86_INS_VPMADCSWD
+ X86_INS_VPMADDUBSW
+ X86_INS_VPMADDWD
+ X86_INS_VPMASKMOVD
+ X86_INS_VPMASKMOVQ
+ X86_INS_VPMAXSB
+ X86_INS_VPMAXSD
+ X86_INS_VPMAXSQ
+ X86_INS_VPMAXSW
+ X86_INS_VPMAXUB
+ X86_INS_VPMAXUD
+ X86_INS_VPMAXUQ
+ X86_INS_VPMAXUW
+ X86_INS_VPMINSB
+ X86_INS_VPMINSD
+ X86_INS_VPMINSQ
+ X86_INS_VPMINSW
+ X86_INS_VPMINUB
+ X86_INS_VPMINUD
+ X86_INS_VPMINUQ
+ X86_INS_VPMINUW
+ X86_INS_VPMOVDB
+ X86_INS_VPMOVDW
+ X86_INS_VPMOVMSKB
+ X86_INS_VPMOVQB
+ X86_INS_VPMOVQD
+ X86_INS_VPMOVQW
+ X86_INS_VPMOVSDB
+ X86_INS_VPMOVSDW
+ X86_INS_VPMOVSQB
+ X86_INS_VPMOVSQD
+ X86_INS_VPMOVSQW
+ X86_INS_VPMOVSXBD
+ X86_INS_VPMOVSXBQ
+ X86_INS_VPMOVSXBW
+ X86_INS_VPMOVSXDQ
+ X86_INS_VPMOVSXWD
+ X86_INS_VPMOVSXWQ
+ X86_INS_VPMOVUSDB
+ X86_INS_VPMOVUSDW
+ X86_INS_VPMOVUSQB
+ X86_INS_VPMOVUSQD
+ X86_INS_VPMOVUSQW
+ X86_INS_VPMOVZXBD
+ X86_INS_VPMOVZXBQ
+ X86_INS_VPMOVZXBW
+ X86_INS_VPMOVZXDQ
+ X86_INS_VPMOVZXWD
+ X86_INS_VPMOVZXWQ
+ X86_INS_VPMULDQ
+ X86_INS_VPMULHRSW
+ X86_INS_VPMULHUW
+ X86_INS_VPMULHW
+ X86_INS_VPMULLD
+ X86_INS_VPMULLW
+ X86_INS_VPMULUDQ
+ X86_INS_VPORD
+ X86_INS_VPORQ
+ X86_INS_VPOR
+ X86_INS_VPPERM
+ X86_INS_VPROTB
+ X86_INS_VPROTD
+ X86_INS_VPROTQ
+ X86_INS_VPROTW
+ X86_INS_VPSADBW
+ X86_INS_VPSCATTERDD
+ X86_INS_VPSCATTERDQ
+ X86_INS_VPSCATTERQD
+ X86_INS_VPSCATTERQQ
+ X86_INS_VPSHAB
+ X86_INS_VPSHAD
+ X86_INS_VPSHAQ
+ X86_INS_VPSHAW
+ X86_INS_VPSHLB
+ X86_INS_VPSHLD
+ X86_INS_VPSHLQ
+ X86_INS_VPSHLW
+ X86_INS_VPSHUFB
+ X86_INS_VPSHUFD
+ X86_INS_VPSHUFHW
+ X86_INS_VPSHUFLW
+ X86_INS_VPSIGNB
+ X86_INS_VPSIGND
+ X86_INS_VPSIGNW
+ X86_INS_VPSLLDQ
+ X86_INS_VPSLLD
+ X86_INS_VPSLLQ
+ X86_INS_VPSLLVD
+ X86_INS_VPSLLVQ
+ X86_INS_VPSLLW
+ X86_INS_VPSRAD
+ X86_INS_VPSRAQ
+ X86_INS_VPSRAVD
+ X86_INS_VPSRAVQ
+ X86_INS_VPSRAW
+ X86_INS_VPSRLDQ
+ X86_INS_VPSRLD
+ X86_INS_VPSRLQ
+ X86_INS_VPSRLVD
+ X86_INS_VPSRLVQ
+ X86_INS_VPSRLW
+ X86_INS_VPSUBB
+ X86_INS_VPSUBD
+ X86_INS_VPSUBQ
+ X86_INS_VPSUBSB
+ X86_INS_VPSUBSW
+ X86_INS_VPSUBUSB
+ X86_INS_VPSUBUSW
+ X86_INS_VPSUBW
+ X86_INS_VPTESTMD
+ X86_INS_VPTESTMQ
+ X86_INS_VPTESTNMD
+ X86_INS_VPTESTNMQ
+ X86_INS_VPTEST
+ X86_INS_VPUNPCKHBW
+ X86_INS_VPUNPCKHDQ
+ X86_INS_VPUNPCKHQDQ
+ X86_INS_VPUNPCKHWD
+ X86_INS_VPUNPCKLBW
+ X86_INS_VPUNPCKLDQ
+ X86_INS_VPUNPCKLQDQ
+ X86_INS_VPUNPCKLWD
+ X86_INS_VPXORD
+ X86_INS_VPXORQ
+ X86_INS_VPXOR
+ X86_INS_VRCP14PD
+ X86_INS_VRCP14PS
+ X86_INS_VRCP14SD
+ X86_INS_VRCP14SS
+ X86_INS_VRCP28PD
+ X86_INS_VRCP28PS
+ X86_INS_VRCP28SD
+ X86_INS_VRCP28SS
+ X86_INS_VRCPPS
+ X86_INS_VRCPSS
+ X86_INS_VRNDSCALEPD
+ X86_INS_VRNDSCALEPS
+ X86_INS_VRNDSCALESD
+ X86_INS_VRNDSCALESS
+ X86_INS_VROUNDPD
+ X86_INS_VROUNDPS
+ X86_INS_VROUNDSD
+ X86_INS_VROUNDSS
+ X86_INS_VRSQRT14PD
+ X86_INS_VRSQRT14PS
+ X86_INS_VRSQRT14SD
+ X86_INS_VRSQRT14SS
+ X86_INS_VRSQRT28PD
+ X86_INS_VRSQRT28PS
+ X86_INS_VRSQRT28SD
+ X86_INS_VRSQRT28SS
+ X86_INS_VRSQRTPS
+ X86_INS_VRSQRTSS
+ X86_INS_VSCATTERDPD
+ X86_INS_VSCATTERDPS
+ X86_INS_VSCATTERPF0DPD
+ X86_INS_VSCATTERPF0DPS
+ X86_INS_VSCATTERPF0QPD
+ X86_INS_VSCATTERPF0QPS
+ X86_INS_VSCATTERPF1DPD
+ X86_INS_VSCATTERPF1DPS
+ X86_INS_VSCATTERPF1QPD
+ X86_INS_VSCATTERPF1QPS
+ X86_INS_VSCATTERQPD
+ X86_INS_VSCATTERQPS
+ X86_INS_VSHUFPD
+ X86_INS_VSHUFPS
+ X86_INS_VSQRTPD
+ X86_INS_VSQRTPS
+ X86_INS_VSQRTSD
+ X86_INS_VSQRTSS
+ X86_INS_VSTMXCSR
+ X86_INS_VSUBPD
+ X86_INS_VSUBPS
+ X86_INS_VSUBSD
+ X86_INS_VSUBSS
+ X86_INS_VTESTPD
+ X86_INS_VTESTPS
+ X86_INS_VUNPCKHPD
+ X86_INS_VUNPCKHPS
+ X86_INS_VUNPCKLPD
+ X86_INS_VUNPCKLPS
+ X86_INS_VZEROALL
+ X86_INS_VZEROUPPER
+ X86_INS_WAIT
+ X86_INS_WBINVD
+ X86_INS_WRFSBASE
+ X86_INS_WRGSBASE
+ X86_INS_WRMSR
+ X86_INS_XABORT
+ X86_INS_XACQUIRE
+ X86_INS_XBEGIN
+ X86_INS_XCHG
+ X86_INS_FXCH
+ X86_INS_XCRYPTCBC
+ X86_INS_XCRYPTCFB
+ X86_INS_XCRYPTCTR
+ X86_INS_XCRYPTECB
+ X86_INS_XCRYPTOFB
+ X86_INS_XEND
+ X86_INS_XGETBV
+ X86_INS_XLATB
+ X86_INS_XRELEASE
+ X86_INS_XRSTOR
+ X86_INS_XRSTOR64
+ X86_INS_XSAVE
+ X86_INS_XSAVE64
+ X86_INS_XSAVEOPT
+ X86_INS_XSAVEOPT64
+ X86_INS_XSETBV
+ X86_INS_XSHA1
+ X86_INS_XSHA256
+ X86_INS_XSTORE
+ X86_INS_XTEST
+ X86_INS_ENDING ' mark the end of the list of insn
+End Enum
+
+'Group of X86 instructions
+Public Enum x86_insn_group
+ X86_GRP_INVALID = 0 ' = CS_GRP_INVALID
+
+ ' > Generic groups '
+ X86_GRP_JUMP 'all jump instructions (conditional+direct+indirect jumps) = CS_GRP_JUMP
+ X86_GRP_CALL 'all call instructions = CS_GRP_CALL
+ X86_GRP_RET ' all return instructions = CS_GRP_RET
+ X86_GRP_INT 'all interrupt instructions (int+syscall) = CS_GRP_INT
+ X86_GRP_IRET 'all interrupt return instructions = CS_GRP_IRET
+
+ ' > Architecture-specific groups
+ X86_GRP_VM = 128 ' all virtualization instructions (VT-x + AMD-V)
+ X86_GRP_3DNOW
+ X86_GRP_AES
+ X86_GRP_ADX
+ X86_GRP_AVX
+ X86_GRP_AVX2
+ X86_GRP_AVX512
+ X86_GRP_BMI
+ X86_GRP_BMI2
+ X86_GRP_CMOV
+ X86_GRP_F16C
+ X86_GRP_FMA
+ X86_GRP_FMA4
+ X86_GRP_FSGSBASE
+ X86_GRP_HLE
+ X86_GRP_MMX
+ X86_GRP_MODE32
+ X86_GRP_MODE64
+ X86_GRP_RTM
+ X86_GRP_SHA
+ X86_GRP_SSE1
+ X86_GRP_SSE2
+ X86_GRP_SSE3
+ X86_GRP_SSE41
+ X86_GRP_SSE42
+ X86_GRP_SSE4A
+ X86_GRP_SSSE3
+ X86_GRP_PCLMUL
+ X86_GRP_XOP
+ X86_GRP_CDI
+ X86_GRP_ERI
+ X86_GRP_TBM
+ X86_GRP_16BITMODE
+ X86_GRP_NOT64BITMODE
+ X86_GRP_SGX
+ X86_GRP_DQI
+ X86_GRP_BWI
+ X86_GRP_PFI
+ X86_GRP_VLX
+ X86_GRP_SMAP
+ X86_GRP_NOVLX
+ X86_GRP_ENDING
+End Enum
+
+
+
+Function x86_sse_cc2str(v As x86_sse_cc) As String
+ Dim r As String
+ If v = X86_SSE_CC_INVALID Then r = "X86_SSE_CC_INVALID"
+ If v = X86_SSE_CC_EQ Then r = "X86_SSE_CC_EQ"
+ If v = X86_SSE_CC_LT Then r = "X86_SSE_CC_LT"
+ If v = X86_SSE_CC_LE Then r = "X86_SSE_CC_LE"
+ If v = X86_SSE_CC_UNORD Then r = "X86_SSE_CC_UNORD"
+ If v = X86_SSE_CC_NEQ Then r = "X86_SSE_CC_NEQ"
+ If v = X86_SSE_CC_NLT Then r = "X86_SSE_CC_NLT"
+ If v = X86_SSE_CC_NLE Then r = "X86_SSE_CC_NLE"
+ If v = X86_SSE_CC_ORD Then r = "X86_SSE_CC_ORD"
+ If v = X86_SSE_CC_EQ_UQ Then r = "X86_SSE_CC_EQ_UQ"
+ If v = X86_SSE_CC_NGE Then r = "X86_SSE_CC_NGE"
+ If v = X86_SSE_CC_NGT Then r = "X86_SSE_CC_NGT"
+ If v = X86_SSE_CC_FALSE Then r = "X86_SSE_CC_FALSE"
+ If v = X86_SSE_CC_NEQ_OQ Then r = "X86_SSE_CC_NEQ_OQ"
+ If v = X86_SSE_CC_GE Then r = "X86_SSE_CC_GE"
+ If v = X86_SSE_CC_GT Then r = "X86_SSE_CC_GT"
+ If v = X86_SSE_CC_TRUE Then r = "X86_SSE_CC_TRUE"
+
+ If Len(r) = 0 Then
+ r = "Unknown: " & Hex(v)
+ ElseIf DEBUG_DUMP Then
+ r = r & " (" & Hex(v) & ")"
+ End If
+
+ x86_sse_cc2str = r
+
+End Function
+
+Function x86_avx_cc2str(v As x86_avx_cc) As String
+ Dim r As String
+ If v = X86_AVX_CC_INVALID Then r = "X86_AVX_CC_INVALID"
+ If v = X86_AVX_CC_EQ Then r = "X86_AVX_CC_EQ"
+ If v = X86_AVX_CC_LT Then r = "X86_AVX_CC_LT"
+ If v = X86_AVX_CC_LE Then r = "X86_AVX_CC_LE"
+ If v = X86_AVX_CC_UNORD Then r = "X86_AVX_CC_UNORD"
+ If v = X86_AVX_CC_NEQ Then r = "X86_AVX_CC_NEQ"
+ If v = X86_AVX_CC_NLT Then r = "X86_AVX_CC_NLT"
+ If v = X86_AVX_CC_NLE Then r = "X86_AVX_CC_NLE"
+ If v = X86_AVX_CC_ORD Then r = "X86_AVX_CC_ORD"
+ If v = X86_AVX_CC_EQ_UQ Then r = "X86_AVX_CC_EQ_UQ"
+ If v = X86_AVX_CC_NGE Then r = "X86_AVX_CC_NGE"
+ If v = X86_AVX_CC_NGT Then r = "X86_AVX_CC_NGT"
+ If v = X86_AVX_CC_FALSE Then r = "X86_AVX_CC_FALSE"
+ If v = X86_AVX_CC_NEQ_OQ Then r = "X86_AVX_CC_NEQ_OQ"
+ If v = X86_AVX_CC_GE Then r = "X86_AVX_CC_GE"
+ If v = X86_AVX_CC_GT Then r = "X86_AVX_CC_GT"
+ If v = X86_AVX_CC_TRUE Then r = "X86_AVX_CC_TRUE"
+ If v = X86_AVX_CC_EQ_OS Then r = "X86_AVX_CC_EQ_OS"
+ If v = X86_AVX_CC_LT_OQ Then r = "X86_AVX_CC_LT_OQ"
+ If v = X86_AVX_CC_LE_OQ Then r = "X86_AVX_CC_LE_OQ"
+ If v = X86_AVX_CC_UNORD_S Then r = "X86_AVX_CC_UNORD_S"
+ If v = X86_AVX_CC_NEQ_US Then r = "X86_AVX_CC_NEQ_US"
+ If v = X86_AVX_CC_NLT_UQ Then r = "X86_AVX_CC_NLT_UQ"
+ If v = X86_AVX_CC_NLE_UQ Then r = "X86_AVX_CC_NLE_UQ"
+ If v = X86_AVX_CC_ORD_S Then r = "X86_AVX_CC_ORD_S"
+ If v = X86_AVX_CC_EQ_US Then r = "X86_AVX_CC_EQ_US"
+ If v = X86_AVX_CC_NGE_UQ Then r = "X86_AVX_CC_NGE_UQ"
+ If v = X86_AVX_CC_NGT_UQ Then r = "X86_AVX_CC_NGT_UQ"
+ If v = X86_AVX_CC_FALSE_OS Then r = "X86_AVX_CC_FALSE_OS"
+ If v = X86_AVX_CC_NEQ_OS Then r = "X86_AVX_CC_NEQ_OS"
+ If v = X86_AVX_CC_GE_OQ Then r = "X86_AVX_CC_GE_OQ"
+ If v = X86_AVX_CC_GT_OQ Then r = "X86_AVX_CC_GT_OQ"
+ If v = X86_AVX_CC_TRUE_US Then r = "X86_AVX_CC_TRUE_US"
+
+ If Len(r) = 0 Then
+ r = "Unknown: " & Hex(v)
+ ElseIf DEBUG_DUMP Then
+ r = r & " (" & Hex(v) & ")"
+ End If
+
+ x86_avx_cc2str = r
+
+End Function
+
+
+Function x86_avx_rm2str(v As x86_avx_rm) As String
+ Dim r As String
+
+ If v = X86_AVX_RM_INVALID Then r = "X86_AVX_RM_INVALID"
+ If v = X86_AVX_RM_RN Then r = "X86_AVX_RM_RN"
+ If v = X86_AVX_RM_RD Then r = "X86_AVX_RM_RD"
+ If v = X86_AVX_RM_RU Then r = "X86_AVX_RM_RU"
+ If v = X86_AVX_RM_RZ Then r = "X86_AVX_RM_RZ"
+
+ If Len(r) = 0 Then
+ r = "Unknown: " & Hex(v)
+ ElseIf DEBUG_DUMP Then
+ r = r & " (" & Hex(v) & ")"
+ End If
+
+ x86_avx_rm2str = r
+End Function
+
+
diff --git a/bindings/vb6/screenshot.png b/bindings/vb6/screenshot.png
new file mode 100644
index 0000000..3780f67
--- /dev/null
+++ b/bindings/vb6/screenshot.png
Binary files differ
diff --git a/bindings/vb6/vbCapstone.cpp b/bindings/vb6/vbCapstone.cpp
new file mode 100644
index 0000000..90ee165
--- /dev/null
+++ b/bindings/vb6/vbCapstone.cpp
@@ -0,0 +1,119 @@
+/*
+ Capstone Disassembly Engine bindings for VB6
+ Contributed by FireEye FLARE Team
+ Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
+ License: Apache
+ Copyright: FireEye 2017
+
+ This dll is a small stdcall shim so VB6 can access the capstone API
+*/
+
+#include <stdio.h>
+#include <conio.h>
+#include <string.h>
+
+#include <capstone.h>
+#pragma comment(lib, "capstone.lib")
+
+#define EXPORT comment(linker, "/EXPORT:"__FUNCTION__"="__FUNCDNAME__)
+
+unsigned int __stdcall bs_version(int *major, int *minor){
+#pragma EXPORT
+ return cs_version(major,minor);
+}
+
+bool __stdcall bs_support(int query){
+#pragma EXPORT
+ return cs_support(query);
+}
+
+cs_err __stdcall bs_open(cs_arch arch, cs_mode mode, csh *handle){
+#pragma EXPORT
+ return cs_open(arch, mode, handle);
+}
+
+cs_err __stdcall bs_close(csh *handle){
+#pragma EXPORT
+ return cs_close(handle);
+}
+
+cs_err __stdcall bs_option(csh handle, cs_opt_type type, size_t value){
+#pragma EXPORT
+ return cs_option(handle, type, value);
+}
+
+cs_err __stdcall bs_errno(csh handle){
+#pragma EXPORT
+ return cs_errno(handle);
+}
+
+const char* __stdcall bs_strerror(cs_err code){
+#pragma EXPORT
+ return cs_strerror(code);
+}
+
+size_t __stdcall bs_disasm(csh handle, const uint8_t *code, size_t code_size, uint64_t address, size_t count, cs_insn **insn){
+#pragma EXPORT
+ return cs_disasm(handle, code, code_size, address, count, insn);
+}
+
+void __stdcall getInstruction(cs_insn *insn, uint32_t index, void* curInst, uint32_t bufSize){
+#pragma EXPORT
+ memcpy(curInst, (void*)&insn[index], bufSize); //size lets us get a partial version of whatever we have implemented in the vbstruct...
+}
+
+const char* __stdcall bs_reg_name(csh handle, unsigned int reg_id){
+#pragma EXPORT
+ return cs_reg_name(handle, reg_id);
+}
+
+void __stdcall bs_free(cs_insn *insn, size_t count){
+#pragma EXPORT
+ return cs_free(insn, count);
+}
+
+cs_insn* __stdcall bs_malloc(csh handle){
+#pragma EXPORT
+ return cs_malloc(handle);
+}
+
+
+int __stdcall bs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, unsigned int position){
+#pragma EXPORT
+ return cs_op_index(handle,insn,op_type,position);
+}
+
+int __stdcall bs_op_count(csh handle, const cs_insn *insn, unsigned int op_type){
+#pragma EXPORT
+ return cs_op_count(handle,insn,op_type);
+}
+
+bool __stdcall bs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id){
+#pragma EXPORT
+ return cs_reg_write(handle,insn,reg_id);
+}
+
+bool __stdcall bs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id){
+#pragma EXPORT
+ return cs_reg_read(handle,insn,reg_id);
+}
+
+bool __stdcall bs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id){
+#pragma EXPORT
+ return cs_insn_group(handle,insn,group_id);
+}
+
+const char* __stdcall bcs_group_name(csh handle, unsigned int group_id){
+#pragma EXPORT
+ return cs_group_name(handle,group_id);
+}
+
+const char* __stdcall bs_insn_name(csh handle, unsigned int insn_id){
+#pragma EXPORT
+ return cs_insn_name(handle,insn_id);
+}
+
+bool __stdcall bs_disasm_iter(csh handle, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn){
+#pragma EXPORT
+ return cs_disasm_iter(handle, code, size, address, insn);
+}
diff --git a/bindings/vb6/vbCapstone.sln b/bindings/vb6/vbCapstone.sln
new file mode 100644
index 0000000..8451d60
--- /dev/null
+++ b/bindings/vb6/vbCapstone.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 10.00
+# Visual Studio 2008
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "vbCapstone", "vbCapstone.vcproj", "{B693CA7B-8B91-4413-AAED-14F1947F012A}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|Win32 = Debug|Win32
+ Release|Win32 = Release|Win32
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {B693CA7B-8B91-4413-AAED-14F1947F012A}.Debug|Win32.ActiveCfg = Debug|Win32
+ {B693CA7B-8B91-4413-AAED-14F1947F012A}.Debug|Win32.Build.0 = Debug|Win32
+ {B693CA7B-8B91-4413-AAED-14F1947F012A}.Release|Win32.ActiveCfg = Release|Win32
+ {B693CA7B-8B91-4413-AAED-14F1947F012A}.Release|Win32.Build.0 = Release|Win32
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/bindings/vb6/vbCapstone.vcproj b/bindings/vb6/vbCapstone.vcproj
new file mode 100644
index 0000000..3085c8e
--- /dev/null
+++ b/bindings/vb6/vbCapstone.vcproj
@@ -0,0 +1,182 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<VisualStudioProject
+ ProjectType="Visual C++"
+ Version="9.00"
+ Name="vbCapstone"
+ ProjectGUID="{B693CA7B-8B91-4413-AAED-14F1947F012A}"
+ RootNamespace="yy"
+ Keyword="Win32Proj"
+ TargetFrameworkVersion="196613"
+ >
+ <Platforms>
+ <Platform
+ Name="Win32"
+ />
+ </Platforms>
+ <ToolFiles>
+ </ToolFiles>
+ <Configurations>
+ <Configuration
+ Name="Debug|Win32"
+ OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+ IntermediateDirectory="$(ConfigurationName)"
+ ConfigurationType="2"
+ CharacterSet="2"
+ >
+ <Tool
+ Name="VCPreBuildEventTool"
+ />
+ <Tool
+ Name="VCCustomBuildTool"
+ />
+ <Tool
+ Name="VCXMLDataGeneratorTool"
+ />
+ <Tool
+ Name="VCWebServiceProxyGeneratorTool"
+ />
+ <Tool
+ Name="VCMIDLTool"
+ />
+ <Tool
+ Name="VCCLCompilerTool"
+ Optimization="0"
+ AdditionalIncludeDirectories="./../../include/"
+ PreprocessorDefinitions="WIN32;_DEBUG;_CONSOLE"
+ MinimalRebuild="true"
+ BasicRuntimeChecks="3"
+ RuntimeLibrary="1"
+ UsePrecompiledHeader="0"
+ WarningLevel="3"
+ DebugInformationFormat="4"
+ />
+ <Tool
+ Name="VCManagedResourceCompilerTool"
+ />
+ <Tool
+ Name="VCResourceCompilerTool"
+ />
+ <Tool
+ Name="VCPreLinkEventTool"
+ />
+ <Tool
+ Name="VCLinkerTool"
+ OutputFile="./vbCapstone.dll"
+ LinkIncremental="2"
+ GenerateManifest="false"
+ GenerateDebugInformation="true"
+ SubSystem="1"
+ TargetMachine="1"
+ />
+ <Tool
+ Name="VCALinkTool"
+ />
+ <Tool
+ Name="VCManifestTool"
+ EmbedManifest="false"
+ />
+ <Tool
+ Name="VCXDCMakeTool"
+ />
+ <Tool
+ Name="VCBscMakeTool"
+ />
+ <Tool
+ Name="VCFxCopTool"
+ />
+ <Tool
+ Name="VCAppVerifierTool"
+ />
+ <Tool
+ Name="VCPostBuildEventTool"
+ />
+ </Configuration>
+ <Configuration
+ Name="Release|Win32"
+ OutputDirectory="$(SolutionDir)$(ConfigurationName)"
+ IntermediateDirectory="$(ConfigurationName)"
+ ConfigurationType="2"
+ CharacterSet="2"
+ WholeProgramOptimization="1"
+ >
+ <Tool
+ Name="VCPreBuildEventTool"
+ />
+ <Tool
+ Name="VCCustomBuildTool"
+ />
+ <Tool
+ Name="VCXMLDataGeneratorTool"
+ />
+ <Tool
+ Name="VCWebServiceProxyGeneratorTool"
+ />
+ <Tool
+ Name="VCMIDLTool"
+ />
+ <Tool
+ Name="VCCLCompilerTool"
+ Optimization="2"
+ EnableIntrinsicFunctions="true"
+ AdditionalIncludeDirectories="./../../include/"
+ PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE"
+ RuntimeLibrary="0"
+ EnableFunctionLevelLinking="true"
+ UsePrecompiledHeader="0"
+ WarningLevel="3"
+ DebugInformationFormat="3"
+ />
+ <Tool
+ Name="VCManagedResourceCompilerTool"
+ />
+ <Tool
+ Name="VCResourceCompilerTool"
+ />
+ <Tool
+ Name="VCPreLinkEventTool"
+ />
+ <Tool
+ Name="VCLinkerTool"
+ OutputFile="./vbCapstone.dll"
+ LinkIncremental="1"
+ GenerateManifest="false"
+ GenerateDebugInformation="true"
+ SubSystem="1"
+ OptimizeReferences="2"
+ EnableCOMDATFolding="2"
+ TargetMachine="1"
+ />
+ <Tool
+ Name="VCALinkTool"
+ />
+ <Tool
+ Name="VCManifestTool"
+ />
+ <Tool
+ Name="VCXDCMakeTool"
+ />
+ <Tool
+ Name="VCBscMakeTool"
+ />
+ <Tool
+ Name="VCFxCopTool"
+ />
+ <Tool
+ Name="VCAppVerifierTool"
+ />
+ <Tool
+ Name="VCPostBuildEventTool"
+ />
+ </Configuration>
+ </Configurations>
+ <References>
+ </References>
+ <Files>
+ <File
+ RelativePath=".\vbCapstone.cpp"
+ >
+ </File>
+ </Files>
+ <Globals>
+ </Globals>
+</VisualStudioProject>
diff --git a/contrib/windows_kernel/libc.cpp b/contrib/windows_kernel/libc.cpp
index 101b26a..b5b7d5d 100644
--- a/contrib/windows_kernel/libc.cpp
+++ b/contrib/windows_kernel/libc.cpp
@@ -5,6 +5,7 @@
#include "libc.h"
#include <memory>
+#include <Ntintsafe.h>
#pragma warning(push)
#pragma warning (disable : 4565)
@@ -33,10 +34,17 @@
__in size_t size
)
{
+ /* A specially crafted size value can trigger the overflow.
+ If the sum in a value that overflows or underflows the capacity of the type,
+ the function returns nullptr. */
+ size_t number_of_bytes = 0;
+ if (!NT_SUCCESS(RtlSizeTAdd(size, sizeof(MEMBLOCK), &number_of_bytes))){
+ return nullptr;
+ }
MEMBLOCK *pBlock = static_cast<MEMBLOCK*>(
ExAllocatePoolWithTag(
NonPagedPoolNxCacheAligned,
- size + sizeof(MEMBLOCK),
+ number_of_bytes,
_LIBC_POOL_TAG));
if (nullptr == pBlock)
diff --git a/cs.c b/cs.c
index d2ffecc..98f30f7 100644
--- a/cs.c
+++ b/cs.c
@@ -326,7 +326,6 @@
cs_realloc_t cs_mem_realloc = cs_winkernel_realloc;
cs_free_t cs_mem_free = cs_winkernel_free;
cs_vsnprintf_t cs_vsnprintf = cs_winkernel_vsnprintf;
-
#else
// OSX kernel
extern void* kern_os_malloc(size_t size);
@@ -343,7 +342,6 @@
cs_realloc_t cs_mem_realloc = kern_os_realloc;
cs_free_t cs_mem_free = kern_os_free;
cs_vsnprintf_t cs_vsnprintf = vsnprintf;
-
#endif // !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE)
#else
// User-defined
@@ -880,6 +878,7 @@
mci.flat_insn->size = insn_size;
// map internal instruction opcode to public insn ID
+
handle->insn_id(handle, insn_cache, mci.Opcode);
handle->printer(&mci, &ss, handle->printer_info);
diff --git a/cs_priv.h b/cs_priv.h
index 0aa0738..2e6c88f 100644
--- a/cs_priv.h
+++ b/cs_priv.h
@@ -22,7 +22,7 @@
typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
// return register name, given register ID
-typedef char *(*GetRegisterName_t)(unsigned RegNo);
+typedef const char *(*GetRegisterName_t)(unsigned RegNo);
// return registers accessed by instruction
typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
@@ -70,7 +70,7 @@
bool skipdata; // set this to True if we skip data when disassembling
uint8_t skipdata_size; // how many bytes to skip
cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
- uint8_t *regsize_map; // map to register size (x86-only for now)
+ const uint8_t *regsize_map; // map to register size (x86-only for now)
GetRegisterAccess_t reg_access;
struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
};
diff --git a/cstool/README b/cstool/README
index c5ab5c6..a6b0208 100644
--- a/cstool/README
+++ b/cstool/README
@@ -45,4 +45,3 @@
EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF
To see all the supported options, run ./cstool
-
diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
index 71dfeb0..c63ea6b 100644
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@@ -583,7 +583,7 @@
@handle: handle returned by cs_open()
@code: buffer containing raw binary code to be disassembled
- @code_size: size of above code
+ @size: size of above code
@address: address of the first insn in given raw code buffer
@insn: pointer to instruction to be filled in by this API.
diff --git a/include/platform.h b/include/platform.h
new file mode 100644
index 0000000..b0d1a2d
--- /dev/null
+++ b/include/platform.h
@@ -0,0 +1,110 @@
+/* Capstone Disassembly Engine */
+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
+
+#ifndef CAPSTONE_PLATFORM_H
+#define CAPSTONE_PLATFORM_H
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+// MSVC
+
+// stdbool.h
+#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
+// this system does not have stdbool.h
+#ifndef __cplusplus
+typedef unsigned char bool;
+#define false 0
+#define true 1
+#endif
+
+#else
+// VisualStudio 2013+ -> C99 is supported
+#include <stdbool.h>
+#endif
+
+#else
+// not MSVC -> C99 is supported
+#include <stdbool.h>
+#endif
+
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
+// this system does not have inttypes.h
+
+#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
+// this system does not have stdint.h
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed int int32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef signed long long int64_t;
+typedef unsigned long long uint64_t;
+
+#define INT8_MIN (-127i8 - 1)
+#define INT16_MIN (-32767i16 - 1)
+#define INT32_MIN (-2147483647i32 - 1)
+#define INT64_MIN (-9223372036854775807i64 - 1)
+#define INT8_MAX 127i8
+#define INT16_MAX 32767i16
+#define INT32_MAX 2147483647i32
+#define INT64_MAX 9223372036854775807i64
+#define UINT8_MAX 0xffui8
+#define UINT16_MAX 0xffffui16
+#define UINT32_MAX 0xffffffffui32
+#define UINT64_MAX 0xffffffffffffffffui64
+#endif
+
+#define __PRI_8_LENGTH_MODIFIER__ "hh"
+#define __PRI_64_LENGTH_MODIFIER__ "ll"
+
+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
+
+#define PRId16 "hd"
+#define PRIi16 "hi"
+#define PRIo16 "ho"
+#define PRIu16 "hu"
+#define PRIx16 "hx"
+#define PRIX16 "hX"
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+#define PRId32 "ld"
+#define PRIi32 "li"
+#define PRIo32 "lo"
+#define PRIu32 "lu"
+#define PRIx32 "lx"
+#define PRIX32 "lX"
+#else // OSX
+#define PRId32 "d"
+#define PRIi32 "i"
+#define PRIo32 "o"
+#define PRIu32 "u"
+#define PRIx32 "x"
+#define PRIX32 "X"
+#endif
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+// redefine functions from inttypes.h used in cstool
+#define strtoull _strtoui64
+#endif
+
+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
+
+#else
+// this system has inttypes.h by default
+#include <inttypes.h>
+#endif
+
+#endif
diff --git a/msvc/capstone_dll/capstone_dll.vcxproj b/msvc/capstone_dll/capstone_dll.vcxproj
index e70234d..91aa03e 100644
--- a/msvc/capstone_dll/capstone_dll.vcxproj
+++ b/msvc/capstone_dll/capstone_dll.vcxproj
@@ -208,4 +208,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
+</Project>
\ No newline at end of file
diff --git a/msvc/capstone_static/capstone_static.vcxproj b/msvc/capstone_static/capstone_static.vcxproj
index 6e42f4f..6e34b1d 100644
--- a/msvc/capstone_static/capstone_static.vcxproj
+++ b/msvc/capstone_static/capstone_static.vcxproj
@@ -197,4 +197,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
+</Project>
\ No newline at end of file
diff --git a/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj b/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj
index 2420031..3f414dd 100644
--- a/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj
+++ b/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj
@@ -172,4 +172,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
\ No newline at end of file
+</Project>
diff --git a/msvc/cstool/cstool.vcxproj b/msvc/cstool/cstool.vcxproj
index 7b7f5f2..d7fa36e 100644
--- a/msvc/cstool/cstool.vcxproj
+++ b/msvc/cstool/cstool.vcxproj
@@ -170,4 +170,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
\ No newline at end of file
+</Project>
diff --git a/msvc/test_basic/test_basic.vcxproj b/msvc/test_basic/test_basic.vcxproj
deleted file mode 100644
index c410ccd..0000000
--- a/msvc/test_basic/test_basic.vcxproj
+++ /dev/null
@@ -1,164 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
- <ItemGroup Label="ProjectConfigurations">
- <ProjectConfiguration Include="Debug|Win32">
- <Configuration>Debug</Configuration>
- <Platform>Win32</Platform>
- </ProjectConfiguration>
- <ProjectConfiguration Include="Debug|x64">
- <Configuration>Debug</Configuration>
- <Platform>x64</Platform>
- </ProjectConfiguration>
- <ProjectConfiguration Include="Release|Win32">
- <Configuration>Release</Configuration>
- <Platform>Win32</Platform>
- </ProjectConfiguration>
- <ProjectConfiguration Include="Release|x64">
- <Configuration>Release</Configuration>
- <Platform>x64</Platform>
- </ProjectConfiguration>
- </ItemGroup>
- <PropertyGroup Label="Globals">
- <ProjectGuid>{B291E0D9-4B39-4AF8-971D-A015B78D54A1}</ProjectGuid>
- <Keyword>Win32Proj</Keyword>
- <RootNamespace>capstonetest</RootNamespace>
- <ProjectName>test_basic</ProjectName>
- </PropertyGroup>
- <Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
- <ConfigurationType>Application</ConfigurationType>
- <UseDebugLibraries>true</UseDebugLibraries>
- <CharacterSet>Unicode</CharacterSet>
- </PropertyGroup>
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'" Label="Configuration">
- <ConfigurationType>Application</ConfigurationType>
- <UseDebugLibraries>true</UseDebugLibraries>
- <CharacterSet>Unicode</CharacterSet>
- </PropertyGroup>
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
- <ConfigurationType>Application</ConfigurationType>
- <UseDebugLibraries>false</UseDebugLibraries>
- <WholeProgramOptimization>true</WholeProgramOptimization>
- <CharacterSet>Unicode</CharacterSet>
- </PropertyGroup>
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="Configuration">
- <ConfigurationType>Application</ConfigurationType>
- <UseDebugLibraries>false</UseDebugLibraries>
- <WholeProgramOptimization>true</WholeProgramOptimization>
- <CharacterSet>Unicode</CharacterSet>
- </PropertyGroup>
- <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
- <ImportGroup Label="ExtensionSettings">
- </ImportGroup>
- <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
- <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
- </ImportGroup>
- <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'" Label="PropertySheets">
- <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
- </ImportGroup>
- <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
- <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
- </ImportGroup>
- <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="PropertySheets">
- <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
- </ImportGroup>
- <PropertyGroup Label="UserMacros" />
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
- <LinkIncremental>true</LinkIncremental>
- </PropertyGroup>
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
- <LinkIncremental>true</LinkIncremental>
- </PropertyGroup>
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
- <LinkIncremental>false</LinkIncremental>
- </PropertyGroup>
- <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
- <LinkIncremental>false</LinkIncremental>
- </PropertyGroup>
- <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
- <ClCompile>
- <PrecompiledHeader>
- </PrecompiledHeader>
- <WarningLevel>Level3</WarningLevel>
- <Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
- <SDLCheck>true</SDLCheck>
- <AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
- <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
- </ClCompile>
- <Link>
- <SubSystem>Console</SubSystem>
- <GenerateDebugInformation>true</GenerateDebugInformation>
- <AdditionalLibraryDirectories>..\Debug;%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
- <AdditionalDependencies>capstone.lib;%(AdditionalDependencies)</AdditionalDependencies>
- </Link>
- </ItemDefinitionGroup>
- <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
- <ClCompile>
- <PrecompiledHeader>
- </PrecompiledHeader>
- <WarningLevel>Level3</WarningLevel>
- <Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
- <SDLCheck>true</SDLCheck>
- <AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
- <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
- </ClCompile>
- <Link>
- <SubSystem>Console</SubSystem>
- <GenerateDebugInformation>true</GenerateDebugInformation>
- <AdditionalLibraryDirectories>..\x64\Debug;%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
- <AdditionalDependencies>capstone.lib;%(AdditionalDependencies)</AdditionalDependencies>
- </Link>
- </ItemDefinitionGroup>
- <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
- <ClCompile>
- <WarningLevel>Level3</WarningLevel>
- <PrecompiledHeader>
- </PrecompiledHeader>
- <Optimization>MaxSpeed</Optimization>
- <FunctionLevelLinking>true</FunctionLevelLinking>
- <IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
- <SDLCheck>true</SDLCheck>
- <AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
- <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
- </ClCompile>
- <Link>
- <SubSystem>Console</SubSystem>
- <GenerateDebugInformation>true</GenerateDebugInformation>
- <EnableCOMDATFolding>true</EnableCOMDATFolding>
- <OptimizeReferences>true</OptimizeReferences>
- <AdditionalLibraryDirectories>..\Release;%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
- <AdditionalDependencies>capstone.lib;%(AdditionalDependencies)</AdditionalDependencies>
- </Link>
- </ItemDefinitionGroup>
- <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
- <ClCompile>
- <WarningLevel>Level3</WarningLevel>
- <PrecompiledHeader>
- </PrecompiledHeader>
- <Optimization>MaxSpeed</Optimization>
- <FunctionLevelLinking>true</FunctionLevelLinking>
- <IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
- <SDLCheck>true</SDLCheck>
- <AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
- <RuntimeLibrary>MultiThreaded</RuntimeLibrary>
- </ClCompile>
- <Link>
- <SubSystem>Console</SubSystem>
- <GenerateDebugInformation>true</GenerateDebugInformation>
- <EnableCOMDATFolding>true</EnableCOMDATFolding>
- <OptimizeReferences>true</OptimizeReferences>
- <AdditionalLibraryDirectories>..\x64\Release;%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
- <AdditionalDependencies>capstone.lib;%(AdditionalDependencies)</AdditionalDependencies>
- </Link>
- </ItemDefinitionGroup>
- <ItemGroup>
- <ClCompile Include="..\..\tests\test_basic.c" />
- </ItemGroup>
- <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
- <ImportGroup Label="ExtensionTargets">
- </ImportGroup>
-</Project>
diff --git a/msvc/test_detail/test_detail.vcxproj b/msvc/test_detail/test_detail.vcxproj
index 42c44cd..27ce08a 100644
--- a/msvc/test_detail/test_detail.vcxproj
+++ b/msvc/test_detail/test_detail.vcxproj
@@ -161,4 +161,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
+</Project>
\ No newline at end of file
diff --git a/msvc/test_skipdata/test_skipdata.vcxproj b/msvc/test_skipdata/test_skipdata.vcxproj
index 2f7d01f..d041e9c 100644
--- a/msvc/test_skipdata/test_skipdata.vcxproj
+++ b/msvc/test_skipdata/test_skipdata.vcxproj
@@ -161,4 +161,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
+</Project>
\ No newline at end of file
diff --git a/msvc/test_winkernel/test_winkernel.vcxproj b/msvc/test_winkernel/test_winkernel.vcxproj
index ce84275..a489b9e 100644
--- a/msvc/test_winkernel/test_winkernel.vcxproj
+++ b/msvc/test_winkernel/test_winkernel.vcxproj
@@ -135,4 +135,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
-</Project>
\ No newline at end of file
+</Project>
diff --git a/packages/freebsd/ports/devel/capstone/Makefile b/packages/freebsd/ports/devel/capstone/Makefile
index a429710..8d457d9 100644
--- a/packages/freebsd/ports/devel/capstone/Makefile
+++ b/packages/freebsd/ports/devel/capstone/Makefile
@@ -1,7 +1,7 @@
# $FreeBSD$
PORTNAME= capstone
-PORTVERSION= 3.0.1
+PORTVERSION= 4.0.0
CATEGORIES= devel
MASTER_SITES= http://capstone-engine.org/download/${PORTVERSION}/
diff --git a/packages/rpm/capstone.spec b/packages/rpm/capstone.spec
new file mode 100644
index 0000000..7486bd5
--- /dev/null
+++ b/packages/rpm/capstone.spec
@@ -0,0 +1,167 @@
+Name: capstone
+Version: 3.0.4
+Release: 2
+Summary: A lightweight multi-platform, multi-architecture disassembly framework
+
+License: BSD
+URL: http://www.capstone-engine.org/
+Source0: http://www.capstone-engine.org/download/%{version}/%{name}-%{version}.tar.gz
+
+%if 0%{?fedora} > 12
+%global with_python3 1
+%else
+%{!?__python2: %global __python2 /usr/bin/python2}
+%{!?python2_sitelib: %global python2_sitelib %(%{__python2} -c "from distutils.sysconfig import get_python_lib; print (get_python_lib())")}
+%endif
+
+%global srcname distribute
+
+BuildRequires: python2-devel
+BuildRequires: jna
+BuildRequires: java-devel
+%if 0%{?with_python3}
+BuildRequires: python3-devel
+%endif # if with_python3
+%global _hardened_build 1
+
+
+%description
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+%package devel
+Summary: Development files for %{name}
+Requires: %{name}%{?_isa} = %{version}-%{release}
+
+%description devel
+The %{name}-devel package contains libraries and header files for
+developing applications that use %{name}.
+
+%package python
+Summary: Python bindings for %{name}
+Requires: %{name}%{?_isa} = %{version}-%{release}
+
+%description python
+The %{name}-python package contains python bindings for %{name}.
+
+%if 0%{?with_python3}
+%package python3
+Summary: Python3 bindings for %{name}
+Requires: %{name}%{?_isa} = %{version}-%{release}
+
+%description python3
+The %{name}-python3 package contains python3 bindings for %{name}.
+%endif # with_python3
+
+%package java
+Summary: Java bindings for %{name}
+Requires: %{name} = %{version}-%{release}
+BuildArch: noarch
+
+%description java
+The %{name}-java package contains java bindings for %{name}.
+
+%prep
+%setup -q
+
+%build
+DESTDIR="%{buildroot}" V=1 CFLAGS="%{optflags}" \
+LIBDIRARCH="%{_lib}" INCDIR="%{_includedir}" make %{?_smp_mflags}
+
+# Fix pkgconfig file
+sed -i 's;%{buildroot};;' capstone.pc
+grep -v archive capstone.pc > capstone.pc.tmp
+mv capstone.pc.tmp capstone.pc
+
+# build python bindings
+pushd bindings/python
+CFLAGS="%{optflags}" %{__python2} setup.py build
+%if 0%{?with_python3}
+CFLAGS="%{optflags}" %{__python3} setup.py build
+%endif # with_python3
+popd
+
+# build java bindings
+pushd bindings/java
+make CFLAGS="%{optflags}" # %{?_smp_mflags} parallel seems broken
+popd
+
+%install
+DESTDIR=%{buildroot} LIBDIRARCH=%{_lib} \
+INCDIR="%{_includedir}" make install
+find %{buildroot} -name '*.la' -exec rm -f {} ';'
+find %{buildroot} -name '*.a' -exec rm -f {} ';'
+
+# install python bindings
+pushd bindings/python
+%{__python2} setup.py install --skip-build --root %{buildroot}
+%if 0%{?with_python3}
+%{__python3} setup.py install --skip-build --root %{buildroot}
+%endif # with_python3
+popd
+
+# install java bindings
+install -D -p -m 0644 bindings/java/%{name}.jar %{buildroot}/%{_javadir}/%{name}.jar
+
+%check
+ln -s libcapstone.so libcapstone.so.3
+make check LD_LIBRARY_PATH="`pwd`"
+
+%post -p /sbin/ldconfig
+
+%postun -p /sbin/ldconfig
+
+
+%files
+# %license does not work for RHEL<7
+%if 0%{?rhel} || 0%{?fedora} < 21
+%doc LICENSE.TXT LICENSE_LLVM.TXT
+%else
+%license LICENSE.TXT LICENSE_LLVM.TXT
+%endif # %license workarond for RHEL<7
+%doc README ChangeLog
+%{_libdir}/*.so.*
+
+%files devel
+%{_includedir}/*
+%{_libdir}/*.so
+%{_libdir}/pkgconfig/*
+
+%files python
+%{python2_sitelib}/*egg-info
+%{python2_sitelib}/%{name}
+
+%if 0%{?with_python3}
+%files python3
+%{python3_sitelib}/*egg-info
+%{python3_sitelib}/%{name}
+%endif # _with_python3
+
+%files java
+%{_javadir}/
+
+%changelog
+* Thu Jul 16 2015 Stefan Cornelius <scorneli@redhat.com> - 3.0.4-2
+- Fix EPEL6 build problems
+
+* Wed Jul 15 2015 Stefan Cornelius <scorneli@redhat.com> - 3.0.4-1
+- new version 3.0.4. Includes security fixes.
+
+* Tue May 12 2015 Stefan Cornelius <scorneli@redhat.com> - 3.0.3-2
+- Addressed issues found during package review.
+
+* Fri May 08 2015 Stefan Cornelius <scorneli@redhat.com> - 3.0.3-1
+- Update to version 3.0.3
+
+* Fri May 08 2015 Stefan Cornelius <scorneli@redhat.com> - 3.0.2-3
+- Added python3 and hardened build support. Update java building.
+- Various cleanups.
+
+* Wed May 06 2015 Stefan Cornelius <scorneli@redhat.com> - 3.0.2-2
+- Update to 3.0.2. Fix 64bit issues. add %check.
+
+* Sat Sep 27 2014 Adel Gadllah <adel.gadllah@gmail.com> - 2.1.2-2
+- Addressed issues found during package review.
+
+* Mon May 19 2014 Adel Gadllah <adel.gadllah@gmail.com> - 2.1.2-1
+- Initial package
diff --git a/suite/MC/AArch64/basic-a64-instructions.s.cs b/suite/MC/AArch64/basic-a64-instructions.s.cs
index 8a13171..5509356 100644
--- a/suite/MC/AArch64/basic-a64-instructions.s.cs
+++ b/suite/MC/AArch64/basic-a64-instructions.s.cs
@@ -668,9 +668,9 @@
0x41,0x05,0xa0,0xd4 = dcps1 #42
0x22,0x01,0xa0,0xd4 = dcps2 #9
0x03,0x7d,0xa0,0xd4 = dcps3 #1000
-0x01,0x00,0xa0,0xd4 = dcps1
-0x02,0x00,0xa0,0xd4 = dcps2
-0x03,0x00,0xa0,0xd4 = dcps3
+0x01,0x00,0xa0,0xd4 = dcps1
+0x02,0x00,0xa0,0xd4 = dcps2
+0x03,0x00,0xa0,0xd4 = dcps3
0xa3,0x00,0x87,0x13 = extr w3, w5, w7, #0
0xab,0x7d,0x91,0x13 = extr w11, w13, w17, #31
0xa3,0x3c,0xc7,0x93 = extr x3, x5, x7, #15
@@ -1337,18 +1337,18 @@
0x02,0x00,0x80,0x10 = adr x2, #-1048576
0xe9,0xff,0x7f,0xf0 = adrp x9, #4294963200
0x14,0x00,0x80,0x90 = adrp x20, #-4294967296
-0x1f,0x20,0x03,0xd5 = nop
+0x1f,0x20,0x03,0xd5 = nop
0xff,0x2f,0x03,0xd5 = hint #127
-0x1f,0x20,0x03,0xd5 = nop
-0x3f,0x20,0x03,0xd5 = yield
-0x5f,0x20,0x03,0xd5 = wfe
-0x7f,0x20,0x03,0xd5 = wfi
-0x9f,0x20,0x03,0xd5 = sev
-0xbf,0x20,0x03,0xd5 = sevl
-0x5f,0x3f,0x03,0xd5 = clrex
+0x1f,0x20,0x03,0xd5 = nop
+0x3f,0x20,0x03,0xd5 = yield
+0x5f,0x20,0x03,0xd5 = wfe
+0x7f,0x20,0x03,0xd5 = wfi
+0x9f,0x20,0x03,0xd5 = sev
+0xbf,0x20,0x03,0xd5 = sevl
+0x5f,0x3f,0x03,0xd5 = clrex
0x5f,0x30,0x03,0xd5 = clrex #0
0x5f,0x37,0x03,0xd5 = clrex #7
-0x5f,0x3f,0x03,0xd5 = clrex
+0x5f,0x3f,0x03,0xd5 = clrex
0x9f,0x30,0x03,0xd5 = dsb #0
0x9f,0x3c,0x03,0xd5 = dsb #12
0x9f,0x3f,0x03,0xd5 = dsb sy
@@ -1379,12 +1379,14 @@
0xbf,0x3d,0x03,0xd5 = dmb ld
0xbf,0x3e,0x03,0xd5 = dmb st
0xbf,0x3f,0x03,0xd5 = dmb sy
-0xdf,0x3f,0x03,0xd5 = isb
-0xdf,0x3f,0x03,0xd5 = isb
+0xdf,0x3f,0x03,0xd5 = isb
+0xdf,0x3f,0x03,0xd5 = isb
0xdf,0x3c,0x03,0xd5 = isb #12
0xbf,0x40,0x00,0xd5 = msr spsel, #0
0xdf,0x4f,0x03,0xd5 = msr daifset, #15
0xff,0x4c,0x03,0xd5 = msr daifclr, #12
+0x9f,0x40,0x00,0xd5 = msr pan, #0
+0x7f,0x40,0x00,0xd5 = msr uao, #0
0xe5,0x59,0x0f,0xd5 = sys #7, c5, c9, #7, x5
0x5f,0xff,0x08,0xd5 = sys #0, c15, c15, #2, xzr
0xe9,0x59,0x2f,0xd5 = sysl x9, #7, c5, c9, #7
@@ -1575,9 +1577,11 @@
0x2c,0x45,0x1b,0xd5 = msr dlr_el0, x12
0x2c,0x50,0x1c,0xd5 = msr ifsr32_el2, x12
0x0c,0x51,0x18,0xd5 = msr afsr0_el1, x12
+
0x0c,0x51,0x1c,0xd5 = msr afsr0_el2, x12
0x0c,0x51,0x1e,0xd5 = msr afsr0_el3, x12
0x2c,0x51,0x18,0xd5 = msr afsr1_el1, x12
+0x2c,0x51,0x1d,0xd5 = msr afsr1_el12, x12
0x2c,0x51,0x1c,0xd5 = msr afsr1_el2, x12
0x2c,0x51,0x1e,0xd5 = msr afsr1_el3, x12
0x0c,0x52,0x18,0xd5 = msr esr_el1, x12
@@ -1633,6 +1637,7 @@
0x4c,0xe2,0x1c,0xd5 = msr cnthp_cval_el2, x12
0x4c,0xe2,0x1f,0xd5 = msr cntps_cval_el1, x12
0x0c,0xe3,0x1b,0xd5 = msr cntv_tval_el0, x12
+0x0c,0xe3,0x1d,0xd5 = msr cntv_tval_el02, x12
0x2c,0xe3,0x1b,0xd5 = msr cntv_ctl_el0, x12
0x4c,0xe3,0x1b,0xd5 = msr cntv_cval_el0, x12
0x0c,0xe8,0x1b,0xd5 = msr pmevcntr0_el0, x12
@@ -1698,6 +1703,8 @@
0x8c,0xef,0x1b,0xd5 = msr pmevtyper28_el0, x12
0xac,0xef,0x1b,0xd5 = msr pmevtyper29_el0, x12
0xcc,0xef,0x1b,0xd5 = msr pmevtyper30_el0, x12
+0x69,0x42,0x38,0xd5 = mrs x9, pan
+0x89,0x42,0x38,0xd5 = mrs x9, uao
0x09,0x00,0x32,0xd5 = mrs x9, teecr32_el1
0x49,0x00,0x30,0xd5 = mrs x9, osdtrrx_el1
0x09,0x01,0x33,0xd5 = mrs x9, mdccsr_el0
@@ -1799,6 +1806,7 @@
0xa9,0x01,0x38,0xd5 = mrs x9, id_mmfr1_el1
0xc9,0x01,0x38,0xd5 = mrs x9, id_mmfr2_el1
0xe9,0x01,0x38,0xd5 = mrs x9, id_mmfr3_el1
+0xc9,0x02,0x38,0xd5 = mrs x9, id_mmfr4_el1
0x09,0x02,0x38,0xd5 = mrs x9, id_isar0_el1
0x29,0x02,0x38,0xd5 = mrs x9, id_isar1_el1
0x49,0x02,0x38,0xd5 = mrs x9, id_isar2_el1
@@ -1818,13 +1826,21 @@
0x29,0x06,0x38,0xd5 = mrs x9, id_aa64isar1_el1
0x09,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr0_el1
0x29,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr1_el1
+0x49,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr2_el1
+0x69,0xa4,0x38,0xd5 = mrs x9, lorc_el1
+0x29,0xa4,0x38,0xd5 = mrs x9, lorea_el1
+0xe9,0xa4,0x38,0xd5 = mrs x9, lorid_el1
+0x49,0xa4,0x38,0xd5 = mrs x9, lorn_el1
+0x09,0xa4,0x38,0xd5 = mrs x9, lorsa_el1
0x09,0x10,0x38,0xd5 = mrs x9, sctlr_el1
+0x09,0x10,0x3d,0xd5 = mrs x9, sctlr_el12
0x09,0x10,0x3c,0xd5 = mrs x9, sctlr_el2
0x09,0x10,0x3e,0xd5 = mrs x9, sctlr_el3
0x29,0x10,0x38,0xd5 = mrs x9, actlr_el1
0x29,0x10,0x3c,0xd5 = mrs x9, actlr_el2
0x29,0x10,0x3e,0xd5 = mrs x9, actlr_el3
0x49,0x10,0x38,0xd5 = mrs x9, cpacr_el1
+0x49,0x10,0x3d,0xd5 = mrs x9, cpacr_el12
0x09,0x11,0x3c,0xd5 = mrs x9, hcr_el2
0x09,0x11,0x3e,0xd5 = mrs x9, scr_el3
0x29,0x11,0x3c,0xd5 = mrs x9, mdcr_el2
@@ -1835,19 +1851,25 @@
0xe9,0x11,0x3c,0xd5 = mrs x9, hacr_el2
0x29,0x13,0x3e,0xd5 = mrs x9, mdcr_el3
0x09,0x20,0x38,0xd5 = mrs x9, ttbr0_el1
+0x09,0x20,0x3d,0xd5 = mrs x9, ttbr0_el12
0x09,0x20,0x3c,0xd5 = mrs x9, ttbr0_el2
0x09,0x20,0x3e,0xd5 = mrs x9, ttbr0_el3
0x29,0x20,0x38,0xd5 = mrs x9, ttbr1_el1
+0x29,0x20,0x3d,0xd5 = mrs x9, ttbr1_el12
+0x29,0x20,0x3c,0xd5 = mrs x9, ttbr1_el2
0x49,0x20,0x38,0xd5 = mrs x9, tcr_el1
+0x49,0x20,0x3d,0xd5 = mrs x9, tcr_el12
0x49,0x20,0x3c,0xd5 = mrs x9, tcr_el2
0x49,0x20,0x3e,0xd5 = mrs x9, tcr_el3
0x09,0x21,0x3c,0xd5 = mrs x9, vttbr_el2
0x49,0x21,0x3c,0xd5 = mrs x9, vtcr_el2
0x09,0x30,0x3c,0xd5 = mrs x9, dacr32_el2
0x09,0x40,0x38,0xd5 = mrs x9, spsr_el1
+0x09,0x40,0x3d,0xd5 = mrs x9, spsr_el12
0x09,0x40,0x3c,0xd5 = mrs x9, spsr_el2
0x09,0x40,0x3e,0xd5 = mrs x9, spsr_el3
0x29,0x40,0x38,0xd5 = mrs x9, elr_el1
+0x29,0x40,0x3d,0xd5 = mrs x9, elr_el12
0x29,0x40,0x3c,0xd5 = mrs x9, elr_el2
0x29,0x40,0x3e,0xd5 = mrs x9, elr_el3
0x09,0x41,0x38,0xd5 = mrs x9, sp_el0
@@ -1867,16 +1889,19 @@
0x29,0x45,0x3b,0xd5 = mrs x9, dlr_el0
0x29,0x50,0x3c,0xd5 = mrs x9, ifsr32_el2
0x09,0x51,0x38,0xd5 = mrs x9, afsr0_el1
+0x09,0x51,0x3d,0xd5 = mrs x9, afsr0_el12
0x09,0x51,0x3c,0xd5 = mrs x9, afsr0_el2
0x09,0x51,0x3e,0xd5 = mrs x9, afsr0_el3
0x29,0x51,0x38,0xd5 = mrs x9, afsr1_el1
0x29,0x51,0x3c,0xd5 = mrs x9, afsr1_el2
0x29,0x51,0x3e,0xd5 = mrs x9, afsr1_el3
0x09,0x52,0x38,0xd5 = mrs x9, esr_el1
+0x09,0x52,0x3d,0xd5 = mrs x9, esr_el12
0x09,0x52,0x3c,0xd5 = mrs x9, esr_el2
0x09,0x52,0x3e,0xd5 = mrs x9, esr_el3
0x09,0x53,0x3c,0xd5 = mrs x9, fpexc32_el2
0x09,0x60,0x38,0xd5 = mrs x9, far_el1
+0x09,0x60,0x3d,0xd5 = mrs x9, far_el12
0x09,0x60,0x3c,0xd5 = mrs x9, far_el2
0x09,0x60,0x3e,0xd5 = mrs x9, far_el3
0x89,0x60,0x3c,0xd5 = mrs x9, hpfar_el2
@@ -1896,12 +1921,15 @@
0x49,0x9e,0x38,0xd5 = mrs x9, pmintenclr_el1
0x69,0x9e,0x3b,0xd5 = mrs x9, pmovsset_el0
0x09,0xa2,0x38,0xd5 = mrs x9, mair_el1
+0x09,0xa2,0x3d,0xd5 = mrs x9, mair_el12
0x09,0xa2,0x3c,0xd5 = mrs x9, mair_el2
0x09,0xa2,0x3e,0xd5 = mrs x9, mair_el3
0x09,0xa3,0x38,0xd5 = mrs x9, amair_el1
+0x09,0xa3,0x3d,0xd5 = mrs x9, amair_el12
0x09,0xa3,0x3c,0xd5 = mrs x9, amair_el2
0x09,0xa3,0x3e,0xd5 = mrs x9, amair_el3
0x09,0xc0,0x38,0xd5 = mrs x9, vbar_el1
+0x09,0xc0,0x3d,0xd5 = mrs x9, vbar_el12
0x09,0xc0,0x3c,0xd5 = mrs x9, vbar_el2
0x09,0xc0,0x3e,0xd5 = mrs x9, vbar_el3
0x29,0xc0,0x38,0xd5 = mrs x9, rvbar_el1
@@ -1912,6 +1940,8 @@
0x49,0xc0,0x3e,0xd5 = mrs x9, rmr_el3
0x09,0xc1,0x38,0xd5 = mrs x9, isr_el1
0x29,0xd0,0x38,0xd5 = mrs x9, contextidr_el1
+0x29,0xd0,0x3d,0xd5 = mrs x9, contextidr_el12
+0x29,0xd0,0x3c,0xd5 = mrs x9, contextdir_el2
0x49,0xd0,0x3b,0xd5 = mrs x9, tpidr_el0
0x49,0xd0,0x3c,0xd5 = mrs x9, tpidr_el2
0x49,0xd0,0x3e,0xd5 = mrs x9, tpidr_el3
@@ -1922,19 +1952,27 @@
0x49,0xe0,0x3b,0xd5 = mrs x9, cntvct_el0
0x69,0xe0,0x3c,0xd5 = mrs x9, cntvoff_el2
0x09,0xe1,0x38,0xd5 = mrs x9, cntkctl_el1
+0x09,0xe1,0x3d,0xd5 = mrs x9, cntkctl_el12
0x09,0xe1,0x3c,0xd5 = mrs x9, cnthctl_el2
0x09,0xe2,0x3b,0xd5 = mrs x9, cntp_tval_el0
+0x09,0xe2,0x3d,0xd5 = mrs x9, cntp_tval_el02
0x09,0xe2,0x3c,0xd5 = mrs x9, cnthp_tval_el2
0x09,0xe2,0x3f,0xd5 = mrs x9, cntps_tval_el1
0x29,0xe2,0x3b,0xd5 = mrs x9, cntp_ctl_el0
0x29,0xe2,0x3c,0xd5 = mrs x9, cnthp_ctl_el2
0x29,0xe2,0x3f,0xd5 = mrs x9, cntps_ctl_el1
0x49,0xe2,0x3b,0xd5 = mrs x9, cntp_cval_el0
+0x49,0xe2,0x3d,0xd5 = mrs x9, cntp_cval_el02
0x49,0xe2,0x3c,0xd5 = mrs x9, cnthp_cval_el2
+0x20,0xe3,0x3c,0xd5 = mrs x9, cnthv_ctl_el2
+0x49,0xe3,0x3c,0xd5 = mrs x9, cnthv_cval_el2
+0x09,0xe3,0x3c,0xd5 = mrs x9, cnthv_tval_el2
0x49,0xe2,0x3f,0xd5 = mrs x9, cntps_cval_el1
0x09,0xe3,0x3b,0xd5 = mrs x9, cntv_tval_el0
0x29,0xe3,0x3b,0xd5 = mrs x9, cntv_ctl_el0
+0x29,0xe3,0x3d,0xd5 = mrs x9, cntv_ctl_el02
0x49,0xe3,0x3b,0xd5 = mrs x9, cntv_cval_el0
+0x49,0xe3,0x3d,0xd5 = mrs x9, cntv_cval_el02
0x09,0xe8,0x3b,0xd5 = mrs x9, pmevcntr0_el0
0x29,0xe8,0x3b,0xd5 = mrs x9, pmevcntr1_el0
0x49,0xe8,0x3b,0xd5 = mrs x9, pmevcntr2_el0
@@ -1998,6 +2036,19 @@
0x89,0xef,0x3b,0xd5 = mrs x9, pmevtyper28_el0
0xa9,0xef,0x3b,0xd5 = mrs x9, pmevtyper29_el0
0xc9,0xef,0x3b,0xd5 = mrs x9, pmevtyper30_el0
+0xe9,0x99,0x38,0xd5 = mrs x9, pmsidr_el1
+0xe9,0x9a,0x38,0xd5 = mrs x9, pmbidr_el1
+0x09,0x9a,0x38,0xd5 = mrs x9, pmblimitr_el1
+0x29,0x9a,0x38,0xd5 = mrs x9, pmbptr_el1
+0x69,0x9a,0x38,0xd5 = mrs x9, pmbsr_el1
+0x09,0x99,0x38,0xd5 = mrs x9, pmscr_el1
+0x09,0x99,0x3d,0xd5 = mrs x9, pmscr_el12
+0x09,0x99,0x3c,0xd5 = mrs x9, pmscr_el2
+0x49,0x99,0x38,0xd5 = mrs x9, pmsicr_el1
+0x69,0x99,0x38,0xd5 = mrs x9, pmsirr_el1
+0x89,0x99,0x38,0xd5 = mrs x9, pmsfcr_el1
+0xa9,0x99,0x38,0xd5 = mrs x9, pmsevfr_el1
+0xc9,0x99,0x38,0xd5 = mrs x9, pmslatfr_el1
0xac,0xf1,0x3f,0xd5 = mrs x12, s3_7_c15_c1_5
0xed,0xbf,0x3a,0xd5 = mrs x13, s3_2_c11_c15_7
0x0c,0xf0,0x18,0xd5 = msr s3_0_c15_c0_0, x12
@@ -2009,6 +2060,6 @@
0x80,0x02,0x1f,0xd6 = br x20
0xe0,0x03,0x3f,0xd6 = blr xzr
0x40,0x01,0x5f,0xd6 = ret x10
-0xc0,0x03,0x5f,0xd6 = ret
-0xe0,0x03,0x9f,0xd6 = eret
-0xe0,0x03,0xbf,0xd6 = drps
+0xc0,0x03,0x5f,0xd6 = ret
+0xe0,0x03,0x9f,0xd6 = eret
+0xe0,0x03,0xbf,0xd6 = drps
diff --git a/suite/regress/Makefile b/suite/regress/Makefile
new file mode 100644
index 0000000..bbc73c7
--- /dev/null
+++ b/suite/regress/Makefile
@@ -0,0 +1,10 @@
+LIBNAME = capstone
+
+invalid_read_in_print_operand: invalid_read_in_print_operand.o
+ ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@
+
+%.o: %.c
+ ${CC} -c -I../../include $< -o $@
+
+clean:
+ rm -rf *.o invalid_read_in_print_operand
diff --git a/suite/regress/invalid_read_in_print_operand.c b/suite/regress/invalid_read_in_print_operand.c
new file mode 100644
index 0000000..144ae94
--- /dev/null
+++ b/suite/regress/invalid_read_in_print_operand.c
@@ -0,0 +1,14 @@
+#include <capstone.h>
+
+#define BINARY "\x3b\x30\x62\x93\x5d\x61\x03\xe8"
+
+int main(int argc, char **argv, char **envp) {
+ csh handle;
+ if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle)) {
+ printf("cs_open(…) failed\n");
+ return 1;
+ }
+ cs_insn *insn;
+ cs_disasm(handle, (uint8_t *)BINARY, sizeof(BINARY) - 1, 0x1000, 0, &insn);
+ return 0;
+}
diff --git a/utils.c b/utils.c
index d18e9af..2432097 100644
--- a/utils.c
+++ b/utils.c
@@ -12,7 +12,7 @@
#include "utils.h"
// create a cache for fast id lookup
-static unsigned short *make_id2insn(insn_map *insns, unsigned int size)
+static unsigned short *make_id2insn(const insn_map *insns, unsigned int size)
{
// NOTE: assume that the max id is always put at the end of insns array
unsigned short max_id = insns[size - 1].id;
@@ -28,7 +28,7 @@
// look for @id in @insns, given its size in @max. first time call will update @cache.
// return 0 if not found
-unsigned short insn_find(insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache)
+unsigned short insn_find(const insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache)
{
if (id > insns[max - 1].id)
return 0;
@@ -39,7 +39,7 @@
return (*cache)[id];
}
-int name2id(name_map* map, int max, const char *name)
+int name2id(const name_map* map, int max, const char *name)
{
int i;
@@ -53,7 +53,7 @@
return -1;
}
-char *id2name(name_map* map, int max, const unsigned int id)
+const char *id2name(const name_map* map, int max, const unsigned int id)
{
int i;
@@ -69,7 +69,7 @@
// count number of positive members in a list.
// NOTE: list must be guaranteed to end in 0
-unsigned int count_positive(uint16_t *list)
+unsigned int count_positive(const uint16_t *list)
{
unsigned int c;
@@ -80,7 +80,7 @@
// count number of positive members in a list.
// NOTE: list must be guaranteed to end in 0
-unsigned int count_positive8(unsigned char *list)
+unsigned int count_positive8(const unsigned char *list)
{
unsigned int c;
diff --git a/utils.h b/utils.h
index e1d9ad6..1cd6c2a 100644
--- a/utils.h
+++ b/utils.h
@@ -30,26 +30,26 @@
// look for @id in @m, given its size in @max. first time call will update @cache.
// return 0 if not found
-unsigned short insn_find(insn_map *m, unsigned int max, unsigned int id, unsigned short **cache);
+unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id, unsigned short **cache);
// map id to string
typedef struct name_map {
unsigned int id;
- char *name;
+ const char *name;
} name_map;
// map a name to its ID
// return 0 if not found
-int name2id(name_map* map, int max, const char *name);
+int name2id(const name_map* map, int max, const char *name);
// map ID to a name
// return NULL if not found
-char *id2name(name_map* map, int max, const unsigned int id);
+const char *id2name(const name_map* map, int max, const unsigned int id);
// count number of positive members in a list.
// NOTE: list must be guaranteed to end in 0
-unsigned int count_positive(uint16_t *list);
-unsigned int count_positive8(unsigned char *list);
+unsigned int count_positive(const uint16_t *list);
+unsigned int count_positive8(const unsigned char *list);
#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
#define MATRIX_SIZE(a) (sizeof(a[0])/sizeof(a[0][0]))
diff --git a/xcode/Capstone.xcodeproj/project.pbxproj b/xcode/Capstone.xcodeproj/project.pbxproj
index c07fe69..9d0f370 100644
--- a/xcode/Capstone.xcodeproj/project.pbxproj
+++ b/xcode/Capstone.xcodeproj/project.pbxproj
@@ -1017,7 +1017,7 @@
};
DC474E6319DDEA5F00BCA449 /* test */ = {
isa = PBXNativeTarget;
- buildConfigurationList = DC474E6A19DDEA5F00BCA449 /* Build configuration list for PBXNativeTarget "test" */;
+ buildConfigurationList = DC474E6A19DDEA5F00BCA449 /* Build configuration list for PBXNativeTarget "test_basic" */;
buildPhases = (
DC474E6019DDEA5F00BCA449 /* Sources */,
DC474E6119DDEA5F00BCA449 /* Frameworks */,
@@ -1027,8 +1027,8 @@
);
dependencies = (
);
- name = test;
- productName = test;
+ name = test_basic;
+ productName = test_basic;
productReference = DC474E6419DDEA5F00BCA449 /* test */;
productType = "com.apple.product-type.tool";
};
@@ -1364,7 +1364,7 @@
DCFE23BC19DDCC2D00EF8EA9 /* CapstoneStatic */,
DCFE23CC19DDCC9500EF8EA9 /* CapstoneDynamic */,
DC474F6719DE6F3B00BCA449 /* CapstoneFramework */,
- DC474E6319DDEA5F00BCA449 /* test */,
+ DC474E6319DDEA5F00BCA449 /* test_basic */,
DC474E8519DDEAA200BCA449 /* test_arm */,
DC474EE919DDEAE400BCA449 /* test_arm64 */,
DC3A28DA1AF29BEB00FC9913 /* test_customized_mnem */,
